CN214848588U - Semiconductor package - Google Patents

Abstract

The utility model relates to a semiconductor package. According to some embodiments of the present invention, a semiconductor package comprises: the electronic component, the heat-conducting layer and the first heat-conducting element. An electronic component has a first surface and a second surface opposite the first surface. A thermally conductive layer is located proximate to the first surface of the electronic component. A first thermally conductive element is located in the electronic component, wherein the first thermally conductive element extends from the first surface of the electronic component and is thermally coupled to the thermally conductive layer.

Description

Semiconductor package

Technical Field

The present application relates generally to semiconductor packaging technology and, more particularly, to embedded heat dissipation structures.

Background

As semiconductor technology evolves and integration continues to increase, existing memory packages may include not only memory dies, but also memory controllers or other various functional dies.

During operation, there tends to be significant differences in the power densities of the various dies in the memory package, resulting in very uneven temperature distributions in different areas within the memory package. For example, an area with a higher power density may create several hot spots, such that the temperature of the area is significantly higher than the temperature of an area with a lower power density. Since the high temperature region and the low temperature region are adjacent to each other within the memory package, heat of the high temperature region is inevitably conducted to the adjacent low temperature region, resulting in a temperature rise of the low temperature region.

Generally, the dies in the low temperature region (e.g., memory dies of NAND, DRAM, 3DXP, etc. type) are relatively sensitive to temperature and have a low temperature tolerance, and are prone to performance degradation and even reliability problems under the influence of heat radiation from adjacent high temperature regions. However, the prior art lacks a solution capable of effectively reducing or removing the above-mentioned hot spots.

In view of the above, there is a strong need in the art to provide improved solutions to the above-mentioned problems.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present application provides a semiconductor package that provides an embedded heat dissipation structure.

According to some embodiments of the present application, a semiconductor package includes: the electronic component, the heat-conducting layer and the first heat-conducting element. An electronic component has a first surface and a second surface opposite the first surface. A thermally conductive layer is located proximate to the first surface of the electronic component. A first thermally conductive element is located in the electronic component, wherein the first thermally conductive element extends from the first surface of the electronic component and is thermally coupled to the thermally conductive layer.

According to some embodiments of the present application, the electronic component in a semiconductor package includes a first region and a second region, wherein the first region consumes more power than the second region and the first thermally conductive element is located near the first region.

According to some embodiments of the present application, the first thermally conductive element in a semiconductor package is thermally coupled to the first region.

According to some embodiments of the present application, further comprising a redistribution layer located near the second surface of the electronic component, wherein the first region and the second region are thermally connected to each other through the redistribution layer.

According to some embodiments of the present application, the semiconductor package further comprises a second thermally conductive element located in the electronic component, wherein the second thermally conductive element extends from the first surface of the electronic component and is located near the second region.

According to some embodiments of the present application, the second thermally conductive element in the semiconductor package is thermally coupled to the second region.

According to some embodiments of the present application, the redistribution layer in the semiconductor package is thermally coupled to at least one electrical connector.

According to some embodiments of the present application, the electronic component in the semiconductor package is electrically connected to the substrate through the electrical connector.

According to some embodiments of the application, the semiconductor package further comprises a redistribution layer located near the second surface of the electronic component, wherein the first thermally conductive element extends from the first surface of the electronic component to the redistribution layer.

According to some embodiments of the present application, the thermally conductive layer in a semiconductor package comprises at least one metal layer and at least one graphene layer.

According to some embodiments of the present application, the first thermally conductive element in a semiconductor package includes at least one wall and/or at least one through-hole.

According to some embodiments of the present application, the first thermally conductive element in a semiconductor package includes copper.

According to some embodiments of the present application, the electronic component in a semiconductor package further comprises a third area and a third heat conducting element, wherein the third area consumes more power than the second area, and the third heat conducting element thermally couples the heat conducting layer to the third area.

According to some embodiments of the present application, a thickness of the thermally conductive layer in the semiconductor package is greater than or equal to 5 μm.

Additional aspects and advantages of the present application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of the present application.

Drawings

Drawings necessary for describing embodiments of the present application or the prior art will be briefly described below in order to describe the embodiments of the present application. It is to be understood that the drawings in the following description are only some of the embodiments of the present application. It will be apparent to those skilled in the art that other embodiments of the drawings can be obtained from the structures illustrated in these drawings without the need for inventive work.

Figure 1 shows a top view of a die in a semiconductor package according to some embodiments of the present application.

Fig. 2 shows a schematic longitudinal cross-sectional view of a semiconductor package according to some embodiments of the present application.

Fig. 3 shows a schematic longitudinal cross-sectional view of a semiconductor package according to some embodiments of the present application.

Fig. 4-7 illustrate top views of different morphology heat-conducting components according to some embodiments of the present application.

Fig. 8, 9 and 10 illustrate a method for forming an embodiment of a semiconductor package such as that shown in fig. 2.

Detailed Description

In order to better understand the spirit of the present application, it is further described below in conjunction with some preferred embodiments of the present application.

The following disclosure provides various embodiments or illustrations that can be used to implement various features of the disclosure. The embodiments of components and arrangements described below serve to simplify the present disclosure. It is to be understood that such descriptions are merely illustrative and are not intended to limit the present disclosure. For example, in the description that follows, forming a first feature on or over a second feature may include certain embodiments in which the first and second features are in direct contact with each other; and may also include embodiments in which additional elements are formed between the first and second features described above, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.

Various embodiments of the present application are discussed in detail below. While specific implementations are discussed, it should be understood that these implementations are for illustrative purposes only. One skilled in the relevant art will recognize that other components and configurations may be used without departing from the spirit and scope of the present application.

Figure 1 shows a top view of a die in a semiconductor package according to some embodiments of the present application. As shown in FIG. 1, semiconductor die (10) may be, but is not limited to, an Application Specific Integrated Circuit (ASIC) die including modules such as memory circuit (101), memory control circuit (102), analog circuit (103), and the like. The memory circuit (101) may include circuits for implementing data storage, such as NAND, DRAM, and/or 3DXP, for example. However, the modules usually have different power densities during operation, for example, the power consumption of the memory control circuit (102) and the analog circuit (103) can be significantly higher than the power density of the memory circuit (101), resulting in non-uniform power density in the ASIC die area. Modules with higher power densities will generate more heat, thereby significantly raising the temperature of the area of the die in which they are located, which may also be referred to as hot spots. More disadvantageously, high temperature regions containing hot spots also spread heat to adjacent low temperature regions, causing the adjacent die regions to increase in temperature. For example, during operation, high temperatures in the area where the memory control circuitry (102) and the analog circuitry (103) are located will cause adjacent memory circuitry (101) to heat up, thereby disadvantageously causing performance degradation and/or reliability problems for memory circuitry that is typically temperature sensitive and has low temperature tolerances.

Fig. 2 shows a schematic longitudinal cross-sectional view of a semiconductor package according to some embodiments of the present application. As shown in fig. 2, the semiconductor package (20) may include an electronic component (201), a thermally conductive layer (205), and a first thermally conductive element (204).

The electronic component (201) has a first surface (201') and a second surface (201 ") opposite to the first surface, wherein the first surface and the second surface may correspond to an upper surface and a lower surface of the electronic component (201), respectively. It is to be understood that the first and second surfaces may also correspond to the lower and upper surfaces of the electronic component (201), respectively. The electronic component (201) may be any type of die or chip such as, but not limited to, a memory, a processor, an interdigital transducer, an Application Specific Integrated Circuit (ASIC) die, and the like. In some embodiments, the electronic component (201) is an ASIC die.

During operation, the electronic component (201) may comprise a first region (203) of relatively higher temperature and a second region (203') of relatively lower temperature. The first area (203) may consume more power than the second area (203'). The first region (203) may, for example, contain at least a portion of memory control circuitry and/or analog circuitry. In some embodiments, the first region (203) substantially corresponds to at least a portion of the area in which the memory control circuitry (102) and/or the analog circuitry (103) are located as shown in FIG. 1. In some embodiments, the first region (203) is near the second surface of the electronic component (201). The second region (203') may comprise at least a portion of a memory circuit, for example. In some embodiments, the second region (203') corresponds substantially to at least a portion of the region in which the memory circuit (101) shown in fig. 1 is located. In some embodiments, the second region (203') corresponds approximately to the edge of the region where the memory circuit (101) is located as shown in fig. 1. In some embodiments, the second region (203') is near the second surface of the electronic component (201). In some embodiments, the first region (203) and the second region (203') are spatially adjacent and thermally connected to each other such that the first region (203) having a higher temperature automatically transfers heat to the second region (203') having a lower temperature, thereby adversely affecting the performance and/or reliability of the memory circuitry in the second region (203 ').

The thermally conductive layer (205) is located near a first surface of the electronic component (201). The thermally conductive layer (205) may be thermally coupled to the electronic component (201). In some embodiments, the thermally conductive layer (205) is disposed directly (e.g., in physical contact) on the first surface of the electronic component (201). The thermally conductive layer (205) may be a single layer or a multi-layer structure. In some embodiments, the thermally conductive layer (205) includes at least one first layer (2051) of thermally conductive material and at least one second layer (2052) of thermally conductive material. The first layer of thermally conductive material (2051) and the second layer of thermally conductive material (2052) can independently comprise a metal, graphene, or other suitable thermally conductive material. The materials of the first layer of thermally conductive material (2051) and the second layer of thermally conductive material (2052) can be the same or different. In some embodiments, the first layer of thermally conductive material (2051) and the second layer of thermally conductive material (2052) are different materials, the first layer of thermally conductive material (2051) and the second layer of thermally conductive material (2052) can be alternately stacked. In some embodiments, when the first thermal conductive material layer (2051) and the second thermal conductive material layer (2052) are made of different materials, the thermal conductive layer (205) may include a plurality of first thermal conductive material layers (2051) and a second thermal conductive material layer (2052) in a set structure or a plurality of second thermal conductive material layers (2052) and a first thermal conductive material layer (2051) in a set structure. The two structures may also be stacked alternately.

In some embodiments, the thermally conductive layer (205) comprises at least one metal layer (2051) and at least one graphene layer (2052) for better heat dissipation. In some embodiments, the metal layers (2051) and graphene layers (2052) are alternately stacked in the thermally conductive layer (205). The heat conducting layer (205) may include a plurality of metal layers (2051) with one graphene layer (2052) as a group structure or a plurality of graphene layers (2052) with one metal layer (2051) as a group structure. The two structures may also be stacked alternately. The metal layer (2051) may comprise, for example, but not limited to, copper, aluminum. The multilayer copper-graphene stacked structure can fully exert the excellent heat-conducting property (3500-5000W/mK) of graphene, so as to remarkably improve the heat-dissipating capability.

In some embodiments, in the thermally conductive layer (205), the metal layer (2051) and/or the graphene layer (2052) are at least 5 layers. In some embodiments, the total thickness of the thermally conductive layer (205) may be greater than or equal to 5 μm. In some embodiments, a thickness of 5 μm corresponds to at least 5 layers of the metal layer (2051) and/or the graphene layer (2052). In some embodiments, when the thermally conductive layer (205) includes at least one metal layer (2051) and at least one graphene layer (2052), the first surface of the electronic component (201) may be in contact with the metal layer (2051) or the graphene layer (2052). In some embodiments, the first surface of the thermally conductive layer (205) is in contact with the metal layer (2051).

The first heat conducting element (204) is located in the electronic component (201) and is thermally coupled to the heat conducting layer (205) to dissipate heat from the interior of the electronic component (201) through the heat conducting layer (205). In some embodiments, the first thermally conductive element (204) extends from the first surface of the electronic component (201) (e.g., extends from the first surface downward toward the second surface). In some embodiments, the first thermally conductive element (204) extends from the first surface of the electronic component (201) (e.g., extends from the first surface downward toward the second surface) and stops before reaching the electronic component (201). In some embodiments, the first thermally conductive element (204) extends from the first surface of the electronic component (201) (e.g., extends from the first surface downward toward the second surface) to reach the second surface of the electronic component (201). In some embodiments, the first thermally conductive element (204) extends from the first surface of the electronic component (201) (e.g., extends from the first surface down towards the second surface) to the vicinity of the first region (203). In some embodiments, the first heat conducting element (204) extends from near the first region (203) to the heat conducting layer (205), in contact with the heat conducting layer (205). In some embodiments, the first heat conducting element (204) is thermally coupled to the first region (203) and the heat conducting layer (205) to transfer heat from the first region (203) through the heat conducting layer (205) for heat dissipation. This prevents the first region (203) from directly transferring heat laterally to the lower temperature second region (203'), thereby effectively reducing the temperature inside the electronic component (201). In some embodiments, the first heat-conducting element (204) is thermally coupled to the first region (203) and extends to the heat-conducting layer (205), in contact with the metal layer (2051) of the heat-conducting layer (205). In some embodiments, the first heat conducting element (204) is thermally coupled from the first region (203) and extends to the heat conducting layer (205) and is in contact with the graphene layer (2052) of the heat conducting layer (205).

In some embodiments, the semiconductor package (20) may further include a second thermally conductive element (206) located in the electronic component (201) thermally coupled to the thermally conductive layer (205). In some embodiments, the second thermally conductive element (206) extends from the first surface of the electronic component (201) (e.g., extends from the first surface downward toward the second surface). In some embodiments, the second thermally conductive element (206) extends from the first surface of the electronic component (201) (e.g., extends from the first surface downward toward the second surface) and stops before reaching the electronic component (201). In some embodiments, the second thermally conductive element (206) extends from the first surface of the electronic component (201) (e.g., extends from the first surface downward toward the second surface) to reach the second surface of the electronic component (201). In some embodiments, the second thermally conductive assembly (206) extends from the first surface of the electronic component (201) (e.g., extends from the first surface down toward the second surface) to the vicinity of the second region (203'). In some embodiments, the second heat conducting assembly (206) extends from proximate the second region (203') to the heat conducting layer (205), and is in contact with the heat conducting layer (205). In some embodiments, the second heat-conducting component (206) is thermally coupled to the second region (203') and extends to the heat-conducting layer (205), in contact with the metal layer (2051) of the heat-conducting layer (205). In some embodiments, the second thermally conductive assembly (206) is thermally coupled from the second region (203') and extends to the thermally conductive layer (205) and is in contact with the graphene layer (2052) of the thermally conductive layer (205).

The second heat conducting element (206) can be disposed near the second region (203') with lower temperature and thermally coupled to the heat conducting layer (205), so that heat can be transferred from the first region (203) with higher temperature to the second region (203') with lower temperature through the first heat conducting element (204), the heat conducting layer (205) and the second heat conducting element (206) to achieve the effect of heat dissipation. Since the heat transfer path is extended to form a heat cycle, the heat dissipation effect can be further improved. This prevents the first region (203) from transferring heat directly laterally to the second region (203'), thereby effectively reducing the temperature inside the electronic component (201). Furthermore, if the distance between the first heat conducting element (204) and the second heat conducting element (206) is elongated, for example, arranged at two distal ends of the electronic component (201), respectively (for example, near two sides of the electronic component (201)), heat can be transferred along the entire horizontal surface of the electronic component (201). In this way, the first thermally conductive element (204) and the second thermally conductive element (206) disposed at both ends of the electronic component (201) are able to take full advantage of the overall span of the die surface for optimal thermal conduction.

In some embodiments, the first thermally conductive assembly (204) and the second thermally conductive element (206) may independently comprise at least one wall and/or at least one through-hole. In some embodiments, the first heat-conducting element (204) and the second heat-conducting element (206) may have a curved or broken line form extending from the first surface of the electronic component (201) as seen from a side view. In some embodiments, the first heat-conducting element (204) and the second heat-conducting element (206) may extend from the first surface of the electronic component (201) substantially perpendicular to the first surface and/or the second surface of the electronic component (201) from a side view. In some embodiments, the first thermally conductive element (204) and the second thermally conductive element (206) may independently comprise copper, aluminum, or other suitable thermally conductive material. The width and spacing of the walls or vias in the first thermally conductive element (204) and the second thermally conductive element (206) can be adjusted as desired.

In some embodiments, the semiconductor package (20) may further include a Redistribution layer (RDL) (202). The redistribution layer (202) may be located near the second surface of the electronic component (201). In some embodiments, the redistribution layer (202) may be thermally coupled with the first region (203) and/or the second region (203'). In some embodiments, the redistribution layer (202) is thermally coupled to the first region (203), such that heat from the first region (203) can be transferred through the first heat conducting element (204) and the heat conducting layer (205) up and through the redistribution layer (202) down, further increasing the heat dissipation effect by increasing the heat dissipation area. In some embodiments, the redistribution layer (202) may be thermally coupled to the first region (203) and the second region (203'), such that heat of the first region (203) may be transferred to the second region (203') through the first heat conducting element (204), the heat conducting layer (205), the second heat conducting element (206) on the one hand, and the redistribution layer (202) on the other hand, to the second region (203'), which may further increase heat dissipation by increasing the heat dissipation area. In some embodiments, the redistribution layer (202) is electrically connected with memory circuitry, memory control circuitry, and/or analog circuitry in the electronic component (201). Thus, heat generated by the memory circuitry, the memory control circuitry, and/or the analog circuitry may be transferred outward via the redistribution layer (202) in the manner described above. In some embodiments, the first heat conducting element (204) and/or the second heat conducting element (206) are adjacent to or in direct contact with the redistribution layer (202) to conduct heat in the first region (203) more intensively and accurately to the heat conducting layer (205) or the second region (203') and then to achieve heat dissipation through the heat conducting layer (205) or the second region (203'). In some embodiments, the redistribution layer (202) may be 4 μm to 5 μm thick.

Fig. 3 shows a schematic longitudinal cross-sectional view of a semiconductor package according to some embodiments of the present application. The semiconductor package (30) in fig. 3 may comprise an electronic component (301), a thermally conductive layer (305), and a first thermally conductive element (304), wherein the electronic component (301) has a first surface (301') and a second surface (301 ") opposite the first surface, and there may be a first region (303) of higher temperature and a second region (303') of lower temperature adjacent the second surface. Heat inside the electronic component (301) can be conducted to the heat conducting layer (305) through the first heat conducting element (304), and then the heat is radiated through the heat conducting layer (305) so as to effectively reduce the temperature inside the electronic component (301).

The semiconductor package of fig. 3 differs from that of fig. 2 at least in that the vicinity of the second surface in fig. 3 further comprises at least one second region of higher temperature (e.g., higher than the second region (303'), such as the third region (303') shown in fig. 3). The third region (303 ") may consume more power than the second region (303'). In some embodiments, it is located substantially in the middle of the second surface of the electronic component (301). Therefore, in order to reduce the temperature of the third area (303 "), a third heat conducting element (304') may be further arranged above the third area (303") and thermally coupled to the heat conducting layer (305) and extending from the first surface of the electronic component (301) (e.g. extending from the first surface down towards the second surface). In this way, heat from the third region (303 ") can be conducted through the third heat conducting element (304') to the heat conducting layer (305) and further dissipated through the heat conducting layer (305).

Similar to the embodiment shown in fig. 2, the electronic component (301) in fig. 3 may further comprise a second heat conducting element (306) thermally coupled to the heat conducting layer (305) and extending from the first surface of the electronic component (301) (e.g., extending from the first surface downward toward the second surface), wherein the second heat conducting element (306) may be located above the second region (303') of lower temperature. In this way, the heat in the first region (303) and the third region (303 ") having the higher temperature may be conducted first to the heat conducting layer (305) via the first heat conducting element (304) and the third heat conducting element (304'), respectively, and further from the heat conducting layer (305) to the second region (303') having the lower temperature via the second heat conducting element (306), thereby forming an additional heat cycle for a better heat dissipation effect.

In some embodiments, the semiconductor package (30) may further include a redistribution layer (302) located substantially near the second surface of the electronic component (301), electrically connected with the memory circuitry, the memory control circuitry, and/or the analog circuitry in the electronic component (301), and thermally connecting the first region (303) and the second region (303') and the third region (303 ") to each other.

In some embodiments, the semiconductor package (30) may further include at least one electrical connector (307). In some embodiments, the electrical connector (307) is located near one surface of the redistribution layer (302). The redistribution layer (302) may be electrically and/or thermally coupled with the substrate (308) via said electrical connector (307), thereby forming a further thermal circulation path constituted by the redistribution layer (302), the electrical connector (307) and the substrate (308) for performing a further heat dissipation on the basis of the thermal circulation path constituted by the redistribution layer (302), the first heat conducting element (304), the second heat conducting element (306), the third heat conducting element (304') and the heat conducting layer (305). In some embodiments, the electrical connectors (307) are solder balls. In some embodiments, the substrate (308) is a Printed Circuit Board (PCB).

In some embodiments, the first heat-conducting element (304), the second heat-conducting element (306), and the third heat-conducting element (304') may independently comprise at least one wall and/or at least one through-hole. In some embodiments, the first heat-conducting element (304), the second heat-conducting element (306) and the third heat-conducting element (304') may have a curved or broken line form extending from the first surface of the electronic component (301) as seen from a side view. In some embodiments, the first heat-conducting element (304), the second heat-conducting element (306), and the third heat-conducting element (304') may extend substantially perpendicular to the first surface and/or the second surface of the electronic component (301) from the first surface of the electronic component (301) from a side view. In some embodiments, the first thermally conductive element (304), the second thermally conductive element (306), and the third thermally conductive element (304') may independently comprise copper, aluminum, or other suitable thermally conductive material. The widths and spacings of the walls or vias in the first (304), second (306) and third (304') heat-conducting elements can be adjusted as desired.

Fig. 4-7 illustrate top views of different morphology heat-conducting components according to some embodiments of the present application. The top view of the heat-conducting assembly shown therein may correspond to the heat-conducting assembly shown in fig. 2. In some embodiments of the semiconductor package (40) shown in fig. 4, the first thermally conductive element (404) and the second thermally conductive element (406) generally correspond to the thermally conductive assembly (204, 206) shown in fig. 2, with cross-sections that are parallel straight lines and parallel to the narrow sides of the semiconductor package (40). Some embodiments of the semiconductor package (50) shown in fig. 5 are similar to the semiconductor package (40) of fig. 4, except that the first heat conducting element (504) and the second heat conducting element (506) in fig. 5 are perpendicular to the narrow sides of the semiconductor package (50). Further, some embodiments of the semiconductor package (60) shown in fig. 6 incorporate the thermally conductive assembly configurations shown in fig. 4 and 5 to form the first thermally conductive element (604) and the second thermally conductive element (606) in a cross-grid shape for better heat dissipation. Unlike the wall-mounted heat-conducting assemblies of fig. 4-6, in some embodiments of the semiconductor package (70) of fig. 7, the first heat-conducting element (704) and the second heat-conducting element (706) are vias extending through the top and bottom surfaces of the semiconductor package and having a generally circular cross-section.

It should be understood that the heat-conducting component in the present application is not limited to the configuration shown in fig. 4 to 7, but may have any configuration. For example, the straight heat-conducting elements shown in fig. 4 to 6 may be curved or broken lines from a top view, and the width of the walls or the through holes in the heat-conducting elements shown in fig. 4 to 7 and the distance between the walls or the through holes may be further adjusted according to the requirement. It should also be understood that the thermal conduction element structures of fig. 4-7 may also be extended to the embodiment of fig. 3, rather than being limited to both ends of the semiconductor package. Further, the heat conducting assembly shown in fig. 4 to 7 may be disposed not only at two ends of the electronic component, but also substantially around the outer periphery of the electronic component, when viewed from a top view, so as to obtain a better heat dissipation effect.

Fig. 8, 9 and 10 illustrate a method for forming an embodiment of a semiconductor package such as that shown in fig. 2. As shown in fig. 8, a trench or hole (804) and a trench or hole (806) are first etched simultaneously or sequentially on both sides of the top of the electronic component (201) of the semiconductor package (80) and the bottom of the trench or hole (804, 806) is brought into proximity or direct contact with the upper surface of the redistribution layer (802) at the bottom of the electronic component (201).

Next, as shown in fig. 9, a metal (e.g., copper) or other thermally conductive material is deposited or plated in the trenches or holes formed in the step of fig. 8 to form thermally conductive components (904, 906). In some embodiments, the lower end of the thermally conductive assembly (904, 906) is adjacent to or in direct contact with the upper surface of the redistribution layer (902). In some embodiments, to ensure the top of the deposited electronic component (901) is flat, a Chemical Mechanical Polishing (CMP) process may be further performed on the top surface of the electronic component (901).

Finally, as shown in fig. 10, a thermally conductive layer (1005) is formed on the top surface of the electronic component (1001) such that the thermally conductive components (1004, 1006) are thermally coupled to the thermally conductive layer (1005). In some embodiments, forming the thermally conductive layer (1005) may include forming a multi-layer copper-graphene stack structure, wherein the graphene layer may be applied from the inside by growing graphene directly on a silicon wafer, or may be applied from the outside by using a lift-off (Exfoliation) technique to first grow graphene in an external substrate and then transfer it into a die. In some embodiments, the material of the stacked structure is not limited to copper and graphene, but may be aluminum or any other thermally conductive material. Preferably, the number of layers of the stacked structure may be at least five layers, and the total thickness thereof may be greater than or equal to 5 μm.

The embedded heat dissipation structure provided by the application makes full use of the whole span of the surface of the bare chip to realize good heat conduction, and avoids the influence of the heat diffusion effect of a high-temperature area on the performance and/or reliability of a circuit in a low-temperature area with lower temperature tolerance, thereby improving the running speed and reliability of a device. When the embedded heat dissipation structure further comprises a heat circulation path, the overall temperature of the electronic component can be obviously reduced, and therefore the operation speed and the reliability of the device are further improved. In particular, the embedded heat dissipation structure provided by the present application is particularly useful for semiconductor packages with large thickness, and the heat dissipation effect is particularly significant. In addition, the existence of the heat conduction assembly can also provide additional mechanical strength, and the yield, the performance and the reliability of products are further improved. It should be understood that the present application is applicable to a variety of semiconductor packages and is not limited to packages implemented with ASIC dies.

It should be noted that reference throughout this specification to "one embodiment of the present application" or similar terms means that a particular feature, structure, or characteristic described in connection with the other embodiments is included in at least one embodiment and may not necessarily be present in all embodiments. Thus, respective appearances of the phrase "one embodiment of the present application" or similar terms in various places throughout this specification are not necessarily referring to the same embodiment.

Furthermore, the particular features, structures, or characteristics of any specific embodiment may be combined in any suitable manner with one or more other embodiments.

The technical content and the technical features of the present invention have been described in the above related embodiments, however, the above embodiments are only examples for implementing the present invention. Those skilled in the art may make various alterations and modifications based on the teachings and disclosure of this invention without departing from the spirit of this invention. Accordingly, the disclosed embodiments do not limit the scope of the invention. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

Claims (14)

1. A semiconductor package, comprising:

an electronic component having a first surface and a second surface opposite the first surface;

a thermally conductive layer located proximate to the first surface of the electronic component; and

a first thermally conductive element located in the electronic component, wherein the first thermally conductive element extends from the first surface of the electronic component and is thermally coupled to the thermally conductive layer.

2. The semiconductor package of claim 1, wherein the electronic component includes a first area and a second area, wherein the first area consumes more power than the second area and the first thermally conductive element is located near the first area.

3. The semiconductor package of claim 2, wherein the first thermally conductive element is thermally coupled to the first region.

4. The semiconductor package of claim 2, further comprising a redistribution layer located proximate to the second surface of the electronic component, wherein the first region and the second region are thermally connected to each other through the redistribution layer.

5. A semiconductor package as recited in claim 2 or 4, further comprising a second thermally conductive element located in the electronic component, wherein the second thermally conductive element extends from the first surface of the electronic component and is located proximate to the second region.

6. The semiconductor package of claim 5, wherein the second thermally conductive element is thermally coupled with the second region.

7. The semiconductor package of claim 4, wherein the redistribution layer is thermally coupled to at least one electrical connector.

8. The semiconductor package of claim 7, wherein the electronic component is electrically connected to a substrate through the electrical connector.

9. The semiconductor package of claim 1, further comprising a redistribution layer located near the second surface of the electronic component, wherein the first thermally conductive element extends from the first surface of the electronic component to the redistribution layer.

10. The semiconductor package of claim 1, wherein the thermally conductive layer comprises at least one metal layer and at least one graphene layer.

11. The semiconductor package of claim 1, wherein the first thermally conductive element comprises at least one wall and/or at least one through via.

12. The semiconductor package of claim 11, wherein the first thermally conductive element comprises copper.

13. The semiconductor package of claim 2, wherein the electronic component further comprises a third area and a third thermally conductive element, wherein the third area consumes more power than the second area, and the third thermally conductive element thermally couples the thermally conductive layer to the third area.

14. The semiconductor package of claim 10, wherein the thermally conductive layer has a thickness greater than or equal to 5 μ ι η.

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