CN214313178U - Chip packaging body and electronic device - Google Patents

Chip packaging body and electronic device Download PDF

Info

Publication number
CN214313178U
CN214313178U CN202022149330.0U CN202022149330U CN214313178U CN 214313178 U CN214313178 U CN 214313178U CN 202022149330 U CN202022149330 U CN 202022149330U CN 214313178 U CN214313178 U CN 214313178U
Authority
CN
China
Prior art keywords
chip
insulating layer
metal substrate
hole
conductive layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202022149330.0U
Other languages
Chinese (zh)
Inventor
霍佳仁
宋关强
江京
刘建辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sky Chip Interconnection Technology Co Ltd
Original Assignee
Sky Chip Interconnection Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sky Chip Interconnection Technology Co Ltd filed Critical Sky Chip Interconnection Technology Co Ltd
Application granted granted Critical
Publication of CN214313178U publication Critical patent/CN214313178U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect

Abstract

The application discloses chip package and electron device, wherein, this chip package includes: a patterned metal substrate plate, wherein a first through-hole is provided in the metal substrate plate; a chip disposed in the first through hole; the first insulating layer covers the chip and the metal substrate board and fills the first through hole, wherein a second through hole is formed in the first insulating layer to expose part of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer. In this way, the chip package in this application can realize the two-sided heat dissipation of chip, and the structure is comparatively simple, and electric route and heat dissipation path are short, have excellent low resistance characteristic and radiating effect, can realize the miniaturization and the frivolousization of chip package.

Description

Chip packaging body and electronic device
Technical Field
The present disclosure relates to the field of chip packaging technologies, and in particular, to a chip package, a method for manufacturing the chip package, and an electronic device.
Background
In recent years, with the application of Mosfet (Metal Oxide Semiconductor Field Effect Transistor, abbreviated as Mosfet) and IGBT (Insulated Gate Bipolar Transistor) power modules to almost all power industry products, corresponding power devices are steadily developing in the direction of high performance, high speed, small volume and multi-chip connection packaging.
However, conventional wire bonding and double-sided copper interconnect processes and process methods have been increasingly difficult to meet the requirements of high performance, fast speed, small volume, multi-chip connection packaging and modularization of power devices. The power semiconductor packaging process needs to be developed towards a more excellent packaging mode of a PLFO (sheet level Fan out) process.
SUMMERY OF THE UTILITY MODEL
The application provides a chip package and an electronic device, which aim to solve the problem that the chip package in the prior art cannot realize the technical effects of miniaturization, lightness and thinness and excellent electrical and heat dissipation characteristics.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a chip package, wherein the chip package includes: a patterned metal substrate plate, wherein a first through-hole is provided in the metal substrate plate; a chip disposed in the first through hole; the first insulating layer covers the chip and the metal base material plate and fills the first through hole, wherein a second through hole is formed in the first insulating layer to expose part of the metal base material plate and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer.
And a patterned second conductive layer is arranged between the overlapped parts of the first insulating layer and the first conductive layer, and the chip is connected to the second conductive layer and the metal substrate board through the first conductive layer.
The chip packaging body further comprises a conductive metal layer, and the conductive metal layer is arranged on the surface of one side, far away from the first conductive layer, of the metal substrate board and the surface of one side, with the same horizontal plane, of the chip and the first insulating layer.
The chip packaging body further comprises a second insulating layer, and the second insulating layer covers the first conducting layer and the first insulating layer which is partially exposed.
Wherein the thermal conductivity of the second insulating layer is greater than the thermal conductivity of the first insulating layer.
The bottom area of the chip is smaller than that of the first through hole and is not in direct contact with the metal substrate plate.
In order to solve the above technical problem, the present application adopts another technical solution: there is provided an electronic device, wherein the electronic device comprises a chip package as defined in any one of the above.
The beneficial effect of this application is: unlike the case of the prior art, the chip package in the present application includes: a patterned metal substrate plate, wherein a first through-hole is provided in the metal substrate plate; a chip disposed in the first through hole; the first insulating layer covers the chip and the metal substrate board and fills the first through hole, wherein a second through hole is formed in the first insulating layer to expose part of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer. In this way, the chip package in this application can realize the two-sided heat dissipation of chip, and the structure is comparatively simple, and electric route and heat dissipation path are short, have excellent low resistance characteristic and radiating effect, can realize the miniaturization and the frivolousization of chip package.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive efforts, wherein:
fig. 1 is a schematic structural diagram of a chip package according to a first embodiment of the present application;
FIG. 2 is a schematic structural diagram of a second embodiment of a chip package according to the present application;
FIG. 3 is a schematic structural diagram of a third embodiment of a chip package according to the present application;
FIG. 4 is a schematic structural diagram of a fourth embodiment of a chip package according to the present application;
fig. 5 is a schematic structural diagram of a fifth embodiment of the chip package of the present application;
fig. 6 is a schematic structural diagram of an embodiment of an electronic device according to the present application.
Detailed Description
In order to make the technical problems solved, the technical solutions adopted, and the technical effects achieved by the present application clearer, the technical solutions of the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a chip package according to a first embodiment of the present application.
In the present embodiment, the chip package includes the patterned metal base material plate 12, the chip 22, the first insulating layer 32, and the patterned first conductive layer 42. The chip package comprises a metal substrate 12, a chip 22, a first insulating layer 32, a first conductive layer 42, a second conductive layer 42, a first through hole, a chip 22, a second through hole, a first insulating layer 32, a second conductive layer 42 and a second conductive layer 42, wherein the metal substrate 12 is provided with the first through hole, the chip 22 is provided with the first through hole, the first insulating layer 32 is provided with the second through hole to expose a portion of the metal substrate 12 and the chip 22, the first conductive layer 42 is provided with the first conductive layer and the second through hole, the chip 22 is electrically connected with the metal substrate 12 through the first conductive layer 42, and the first through hole and the second through hole are finally formed as a pin of the chip package.
The number of the through holes in the first insulating layer 32 includes at least two, at least one through hole is disposed above the chip 22, at least another through hole is correspondingly disposed on the metal substrate 12, and the at least two through holes are electrically connected to each other through the first conductive layer 42 covering the inside of each through hole. And the part of the structure corresponding to the metal substrate board 12 under the at least two through holes can be used as a package pin of the chip package to electrically connect with an external device or other chips.
The patterning of the metal substrate 12 and the first conductive layer 42 is set to correspond to the logic circuit to be implemented by the chip 22, and the different chip pins correspond to different patterned electrical paths, and the patterning can be performed by chemical etching or ion etching.
Alternatively, the material of the metal substrate 12 may be one of copper, aluminum, gold, silver and their alloys or metal-filled organics, the material used for the first insulating layer 32 may be one of silicon oxide, silicon nitride, silicon oxynitride-filled organic insulator, circuit board material, and ink, and the material of the first conductive layer 42 is selected from one of copper, aluminum, gold, silver, tin, lead and their alloys or metal-filled organics, so that the chip 22 in the chip package can realize double-sided heat dissipation through the metal substrate 12 and the first conductive layer 42 in the through hole, thereby having more excellent heat dissipation characteristics.
Alternatively, the bottom area of the chip 22 is smaller than the bottom area of the first through hole and is not in direct contact with the metal substrate 12, and the first insulating layer 32 is filled in the remaining portion of the first through hole after the chip 22 is removed, while in other embodiments, the bottom area of the chip 22 may be equal to the bottom area of the first through hole, and the first through hole is completely filled by the chip 22, and the first insulating layer 32 covers the chip 22 and the metal substrate 12, which is not limited in this application.
Alternatively, the surface area of the through hole provided in the first insulating layer 32 on the side facing the metal base plate 12 may be set smaller than the surface area on the side away from the metal base plate 12, that is, the bottom areas of the two sides of the through hole may be set to be different, while in other embodiments, the bottom areas of the two sides of the through hole may also be set to be the same, which is not limited in this application.
Alternatively, the edge portions of the first insulating layer 32 corresponding to the respective through holes may be inclined edges having at least two different inclination angles, or may be disposed in any reasonable structural style such as an arc-shaped curved surface, a wavy curved surface, and the like.
Unlike the case of the prior art, the chip package in the present application includes: a patterned metal substrate plate, wherein a first through-hole is provided in the metal substrate plate; a chip disposed in the first through hole; the first insulating layer covers the chip and the metal substrate board and fills the first through hole, wherein a second through hole is formed in the first insulating layer to expose part of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer. In this way, the chip in the chip package of this application can dispel the heat through the metal substrate board of patterning to and set up the patterned conducting layer that has bigger heat radiating area in the insulating layer through-hole, thereby make this chip can realize two-sided heat dissipation, and make corresponding chip package's structure simpler, electric route and heat dissipation path are shorter, thereby have excellent low resistance characteristic and radiating effect, and can realize chip package's miniaturization and frivolousization.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a chip package according to a second embodiment of the present application. The present embodiment is different from the first embodiment of the chip package provided in the present application in fig. 1 in that the chip package further includes a patterned second conductive layer 52, wherein the second conductive layer 52 is disposed between the overlapping portions of the first insulating layer 32 and the first conductive layer 42.
In the present embodiment, the second conductive layer 52 is disposed on the portion of the first insulating layer 32 not opened with the through hole, and the chip 22 is connected to the second conductive layer 52 by the first conductive layer and finally connected to the metal substrate 12.
The material used for the second conductive layer 52 is also selected from one of copper, aluminum, gold, silver, tin, lead, and their alloys or metal-filled organics, which is not limited in this application.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a chip package according to a third embodiment of the present application. This embodiment differs from the first embodiment of the chip package provided in fig. 1 of the present application in that the chip package further comprises a conductive metal layer 62, wherein the conductive metal layer 62 is disposed on the surface of the metal base plate 12 away from the first insulating layer 32, i.e. the conductive metal layer 62 is disposed on the surface of the metal base plate 12 on the other side where the chip 22 is disposed.
In the present embodiment, the conductive metal layer 62 is made of the same material as the metal substrate 12, and is selected from one of copper, aluminum, gold, silver, and their alloys or metal-filled organic substances, and is disposed by thickening and laminating the metal substrate 12 to ensure that the finally formed patterned metal substrate 12, i.e. the corresponding leads of the chip package, have more reliable strength and are not easily bent or broken.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a chip package according to a fourth embodiment of the present application. This embodiment is different from the first embodiment of the chip package provided in fig. 1 of the present application in that the chip package further includes a second insulating layer 72, wherein the second insulating layer 72 covers the first conductive layer 42 and the partially exposed first insulating layer 32.
In the present embodiment, the patterned first insulating layer 32 is partially exposed and is not completely covered by the first conductive layer 42, wherein the second insulating layer 72 is further disposed in the chip package to cover the first conductive layer 42 and the partially exposed first insulating layer 32, so as to effectively protect the first conductive layer 42 from being damaged by an external force, thereby preventing the logic circuit of the corresponding pin of the chip package from being unable to be effectively implemented due to the external force.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a chip package according to a fifth embodiment of the present application.
Optionally, in an embodiment, the chip package specifically includes: a patterned metal substrate board 12, a chip 22, a first insulating layer 32, a patterned first conductive layer 42, a patterned second conductive layer 52, a conductive metal layer 62, and a second insulating layer 72.
Wherein a first through-hole is provided in the patterned metal base plate 12, and the chip 22 is provided in the first through-hole, and the first insulating layer 32 covers the chip 22 and the metal base material plate 12, the patterned second conductive layer 52 is further disposed on the first insulating layer 32, wherein the first insulating layer 32 and the second conductive layer 52 are provided therein with second through holes to expose portions of the metal base plate 12 and the chip 22, and patterned first conductive layer 42 is disposed on second conductive layer 52 and within the second via, so that the chip 22 can be connected to the patterned second conductive layer 52 and the patterned metal substrate board 12 by the patterned first conductive layer 42 to finally constitute the leads of the chip package, therefore, the chip package has a short electric path and a short heat dissipation path, and has excellent low resistance and heat dissipation effects.
The conductive metal layer 62 is disposed on a surface of the metal substrate 12 away from the first insulating layer 32 and a surface of the chip 22 and the first insulating layer 32 on a same horizontal plane, and the conductive metal layer 62 is a thickened and stacked layer on the metal substrate 12 to ensure that the patterned metal substrate 12 is finally formed, i.e., the corresponding pins of the chip package have more reliable strength, and are not easily bent or broken. The second insulating layer 72 covers the first conductive layer 42 and the partially exposed second conductive layer 52 to effectively protect the first conductive layer 42 and the second conductive layer 52 from being damaged by external force, so as to prevent the logic circuit of the corresponding pin of the chip package from being unable to be effectively implemented due to the external force.
Alternatively, the material of the metal substrate 12 and the conductive metal layer 62 may be one of copper, aluminum, gold, silver and their alloys or metal-filled organics, the material used for the first insulating layer 32 and the second insulating layer 72 may be one of silicon dioxide, silicon nitride, silicon oxynitride-filled organic insulator, circuit board material, and ink, and the material of the first conductive layer 42 and the second conductive layer 52 may be one of copper, aluminum, gold, silver, tin, lead and their alloys or metal-filled organics, so that the chip 22 in the chip package can realize double-sided heat dissipation through the metal substrate 12 and the first conductive layer 42 in the second through hole, thereby having more excellent heat dissipation characteristics.
Alternatively, the bottom area of the chip 22 is smaller than the bottom area of the first through hole and is not in direct contact with the metal substrate 12, and the first insulating layer 32 is filled in the remaining portion of the first through hole after the chip 22 is removed, while in other embodiments, the bottom area of the chip 22 may be equal to the bottom area of the first through hole, and the first through hole is completely filled by the chip 22, and the first insulating layer 32 covers the chip 22 and the metal substrate 12, which is not limited in this application.
Optionally, the insulating material used for the second insulating layer 72 is different from the insulating material used for the first insulating layer 32, and the thermal conductivity of the insulating material used for the second insulating layer 72 is better than that of the insulating material used for the first insulating layer 32, that is, the thermal conductivity of the second insulating layer 72 is higher than that of the first insulating layer 32, so that after the first conductive layer 42 and the second conductive layer 52 are coated, the chip 22 can achieve a better heat dissipation effect through the second insulating layer 72.
Optionally, a solder resist insulating layer is further provided on a side of the chip 22 remote from the metal base material plate 12 to allow only the first conductive layer 42 to be connected to the position corresponding to the pad on the side of the chip 22. The bonding pad is a copper layer portion exposed by a side of the chip 22 that needs to be soldered to electrically connect with an external device, and a non-bonding pad portion on the side of the chip 22 is provided as a solder resist insulating layer.
Optionally, the outermost layer of the chip package, that is, the outer side of the conductive metal layer 62 and the second insulating layer 72, is further provided with an insulating envelope material of any reasonable color, such as black, green or yellow, so as to make the appearance of the chip package more ornamental.
Alternatively, the edge portions of the metal substrate 12 corresponding to the corresponding grooves and the remaining structure after etching may be beveled edges having at least two different angles of inclination, or may be arranged in any reasonable structural pattern such as an arc-shaped curved surface, a wavy curved surface, and the like.
Alternatively, there may be a void at a position where the metal base material plate 12 is connected to the first conductive layer 42, or inside the first conductive layer 42, and the void is further filled with an insulating resin to prevent the entry of air and/or water molecules.
Optionally, the metal substrate 12 is filled with an insulating envelope material of one of any reasonable colors, such as black, green or yellow, at patterned gaps on a side thereof remote from the chip 22, to serve to make the appearance of the chip package more ornamental.
Alternatively, the chip package has a plurality of metal base plates 12 and insulating layers disposed in respective stacks, and interconnection of the plurality of metal base plates 12 is achieved by a plurality of conductive layers in respective through holes.
Optionally, solder balls are further disposed on the side of the metal substrate 12 or the conductive metal layer 62 away from the chip 22 to electrically connect with external devices.
Optionally, a side of the chip package away from the metal substrate 12 is further connected to a power module device, such as one or more of any reasonable power devices, such as a resistor, a capacitor, a transistor, etc., through the first conductive layer 42.
Optionally, at least two chips 22 are disposed on a side of the metal substrate 12 close to the chip 22, and the at least two chips 22 may be electrically connected to each other through the metal substrate 12 and the first conductive layer 42, or the at least two chips 22 are independent of each other and are not electrically connected, which is specifically set by a user according to a circuit logic that the user needs to achieve.
Fig. 6 is a schematic structural diagram of an embodiment of an electronic device according to the present application. The electronic device 600 includes the chip package 610 described above.
Unlike the case of the prior art, the chip package in the present application includes: a patterned metal substrate plate, wherein a first through-hole is provided in the metal substrate plate; a chip disposed in the first through hole; the first insulating layer covers the chip and the metal substrate board and fills the first through hole, wherein a second through hole is formed in the first insulating layer to expose part of the metal substrate board and the chip; and the patterned first conductive layer is arranged on the first insulating layer and in the through hole, so that the chip is connected to the metal substrate board through the first conductive layer. In this way, the chip package in this application can realize the two-sided heat dissipation of chip, and the structure is comparatively simple, and electric route and heat dissipation path are short, have excellent low resistance characteristic and radiating effect, can realize the miniaturization and the frivolousization of chip package.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings, or which are directly or indirectly applied to other related technical fields, are intended to be included within the scope of the present application.

Claims (7)

1. A chip package, comprising:
a patterned metal substrate plate, wherein a first through-hole is provided in the metal substrate plate;
a chip disposed in the first through hole;
a first insulating layer covering the chip and the metal base plate and filling the first through hole, wherein a second through hole is provided in the first insulating layer to expose a portion of the metal base plate and the chip;
a patterned first conductive layer disposed on the first insulating layer and within the via such that the chip is connected to the metal substrate board by the first conductive layer.
2. The chip package of claim 1,
a patterned second conductive layer is further arranged between the first insulating layer and the overlapped part of the first conductive layer, and the chip is connected to the second conductive layer and the metal substrate board through the first conductive layer.
3. The chip package of claim 1,
the chip packaging body further comprises a conductive metal layer, and the conductive metal layer is arranged on the surface of one side, far away from the first conductive layer, of the metal substrate plate and the surface of one side, with the horizontal plane, of the chip and the first insulating layer.
4. The chip package of claim 1,
the chip packaging body further comprises a second insulating layer, and the second insulating layer covers the first conducting layer and the first insulating layer which is partially exposed.
5. The chip package of claim 4,
the thermal conductivity of the second insulating layer is greater than the thermal conductivity of the first insulating layer.
6. The chip package of claim 1,
the bottom area of the chip is smaller than that of the first through hole and is not in direct contact with the metal substrate plate.
7. An electronic device comprising the chip package according to any one of claims 1-6.
CN202022149330.0U 2019-09-25 2020-09-25 Chip packaging body and electronic device Active CN214313178U (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910913230 2019-09-25
CN201910913230X 2019-09-25

Publications (1)

Publication Number Publication Date
CN214313178U true CN214313178U (en) 2021-09-28

Family

ID=75042783

Family Applications (6)

Application Number Title Priority Date Filing Date
CN202022150645.7U Active CN214313179U (en) 2019-09-25 2020-09-25 Chip packaging body and electronic device
CN202011025216.5A Pending CN112563220A (en) 2019-09-25 2020-09-25 Chip package, manufacturing method thereof and electronic device
CN202022149330.0U Active CN214313178U (en) 2019-09-25 2020-09-25 Chip packaging body and electronic device
CN202011025222.0A Pending CN112563221A (en) 2019-09-25 2020-09-25 Chip package, manufacturing method thereof and electronic device
CN202011025215.0A Pending CN112563219A (en) 2019-09-25 2020-09-25 Chip package, manufacturing method thereof and electronic device
CN202022151139.XU Active CN214313180U (en) 2019-09-25 2020-09-25 Chip packaging body and electronic device

Family Applications Before (2)

Application Number Title Priority Date Filing Date
CN202022150645.7U Active CN214313179U (en) 2019-09-25 2020-09-25 Chip packaging body and electronic device
CN202011025216.5A Pending CN112563220A (en) 2019-09-25 2020-09-25 Chip package, manufacturing method thereof and electronic device

Family Applications After (3)

Application Number Title Priority Date Filing Date
CN202011025222.0A Pending CN112563221A (en) 2019-09-25 2020-09-25 Chip package, manufacturing method thereof and electronic device
CN202011025215.0A Pending CN112563219A (en) 2019-09-25 2020-09-25 Chip package, manufacturing method thereof and electronic device
CN202022151139.XU Active CN214313180U (en) 2019-09-25 2020-09-25 Chip packaging body and electronic device

Country Status (1)

Country Link
CN (6) CN214313179U (en)

Also Published As

Publication number Publication date
CN112563220A (en) 2021-03-26
CN214313179U (en) 2021-09-28
CN112563219A (en) 2021-03-26
CN112563221A (en) 2021-03-26
CN214313180U (en) 2021-09-28

Similar Documents

Publication Publication Date Title
US10566320B2 (en) Method for fabricating electronic package
CN107452694B (en) Embedded packaging structure
CN112701095B (en) Power chip stacking and packaging structure
TWI654734B (en) Stacked semiconductor package
US8916958B2 (en) Semiconductor package with multiple chips and substrate in metal cap
US20030206401A1 (en) BGA/LGA with built in heat slug/spreader
JP3687435B2 (en) Semiconductor chip and manufacturing method thereof, semiconductor device, computer, circuit board, and electronic device
KR20050064144A (en) Semiconductor module having semiconductor chip package which is vertically mounted on module board
WO2002050899A2 (en) Semiconductor package
US7180166B2 (en) Stacked multi-chip package
US20090321950A1 (en) Stacked semiconductor package with localized cavities for wire bonding
WO2022110936A1 (en) Power element packaging structure and manufacturing method therefor
JP2001085603A (en) Semiconductor device
US8212349B2 (en) Semiconductor package having chip using copper process
JP3731420B2 (en) Manufacturing method of semiconductor device
WO2007147366A1 (en) Ic packages with internal heat dissipation structures
CN214313178U (en) Chip packaging body and electronic device
CN111710668A (en) Semiconductor packaging structure, manufacturing method thereof and electronic equipment
CN111081554A (en) Embedded packaging structure and manufacturing method thereof
JPH07106509A (en) Multilayer structure semiconductor device
KR20020043395A (en) Semiconductor package
KR101027984B1 (en) PBA Having Heat Sink
JP3757766B2 (en) SEMICONDUCTOR DEVICE, ITS MANUFACTURING METHOD, AND ELECTRONIC DEVICE
JP4045717B2 (en) Semiconductor device
CN216084870U (en) Semiconductor package

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant