CN218827096U

CN218827096U - Packaging structure

Info

Publication number: CN218827096U
Application number: CN202222915605.6U
Authority: CN
Inventors: 赖振楠; 吴奕盛
Original assignee: Hosin Global Electronics Co Ltd
Current assignee: Hosin Global Electronics Co Ltd
Priority date: 2022-11-02
Filing date: 2022-11-02
Publication date: 2023-04-07
Anticipated expiration: 2032-11-02

Abstract

The application discloses packaging structure relates to chip package technical field. The packaging structure comprises a lead frame, a first chip and a second chip; the lead frame comprises a first connecting part, a plurality of second connecting parts and a plurality of third connecting parts which are mutually spaced; the first chip comprises a first pin and a plurality of second pins, the first pin is connected with the first connecting part, and the plurality of second pins are connected with the plurality of second connecting parts in a one-to-one correspondence manner; and the second chip comprises a third pin and a plurality of fourth pins, the third pin is connected with the first connecting part, the fourth pins are connected with the third connecting parts in a one-to-one correspondence manner, and the second chip is interconnected with the first chip through the first connecting part to carry out signal transmission. The application provides a packaging structure, can shorten the signal transmission distance between first chip and the second chip.

Description

Packaging structure

Technical Field

The application relates to the technical field of chip packaging, in particular to a packaging structure.

Background

With the development of semiconductor and integrated circuit technologies, electronic circuit design and manufacture are also moving toward smaller size and higher integration density, wherein multi-chip packages are an important part of the electronic circuit design and manufacture process. In the related art, a plurality of power chips, digital integrated circuit chips, micro Chip devices, and the like may be assembled on a Package substrate by a System in a Package (SIP) or System On Chip (SOC) technology and integrated into one Package.

However, in the conventional package, the interconnection between the power chip and the logic chip needs to be implemented through the cooperation of structures such as the substrate and the printed circuit board, which has a long signal transmission distance and affects the signal transmission efficiency between the power chip and the logic chip.

SUMMERY OF THE UTILITY MODEL

The application provides a packaging structure for shortening a signal transmission distance between a first chip and a second chip.

The application provides a package structure, includes:

the lead frame comprises a first connecting part, a plurality of second connecting parts and a plurality of third connecting parts which are mutually spaced;

the first chip comprises a first pin and a plurality of second pins, the first pin is connected with the first connecting part, and the plurality of second pins are connected with the plurality of second connecting parts in a one-to-one correspondence manner; and

the second chip comprises a third pin and a plurality of fourth pins, the third pin is connected with the first connecting portion, the fourth pins are connected with the third connecting portions in a one-to-one correspondence mode, and the second chip is connected with the first chip through the first connecting portion to conduct signal transmission.

In view of the above technical solutions, data interconnection between the first chip and the second chip can be directly achieved through the first connection portion in the lead frame, and structures such as a printed circuit board are not needed. Therefore, the signal transmission distance between the first chip and the second chip can be obviously shortened, and the signal transmission efficiency between the first chip and the second chip is improved.

In some possible embodiments, a side surface of the second chip on which the third pin and the fourth pins are disposed faces the lead frame, the third pin is connected to the first connection portion through a conductive block, and the fourth pin is connected to the third connection portion through a conductive block.

In some possible embodiments, a side surface of the second chip on which the third pin and the fourth pin are disposed faces away from the lead frame, the third pin is indirectly connected to the first connection portion through a wire, and the fourth pin is also indirectly connected to the third connection portion through a wire.

In some possible embodiments, the first connection portion, the plurality of second connection portions, and the plurality of third connection portions are filled with a first insulating gel at positions spaced apart from each other.

In some possible embodiments, the package structure further includes at least one shielding case;

the shielding cover covers the first chip, the shielding cover and the outer side wall of the first chip are arranged at intervals, and a second insulating colloid is bonded on the contact surface of the shielding cover and the lead frame; and/or

The shielding case covers the second chip, the shielding case and the outer side wall of the second chip are arranged at intervals, and a second insulating colloid is bonded on the contact surface of the lead frame.

when the shielding cover covers the first chip, a third insulating colloid is arranged between the shielding cover and one side of the first chip far away from the lead frame; and/or

When the shielding cover covers the second chip, a third insulating colloid is arranged between the shielding cover and one side of the second chip far away from the lead frame.

In some possible embodiments, the package structure further includes a fourth insulating glue;

the fourth insulating colloid is arranged on one side, close to the first chip, of the lead frame, and the fourth insulating colloid coats the first chip and the second chip.

In some possible embodiments, the fourth insulating gel includes an insulating gel and an insulating heat transfer medium, and the heat transfer medium is mixed in the insulating gel.

In some possible embodiments, the fourth insulating colloid covers the outer surfaces of the first chip and the second chip, and a plurality of fin portions are provided, and the fin portions are spaced from each other.

In some possible embodiments, the package structure further includes a heat dissipation member disposed on a side of the fourth insulating encapsulant away from the lead frame.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.

FIG. 1 illustrates a schematic partial cross-sectional view of a package structure in some embodiments;

FIG. 2 is a schematic diagram showing a partial cross-sectional structure of a package structure in further embodiments;

FIG. 3 shows a cross-sectional schematic of a package structure in some embodiments;

fig. 4 is a schematic cross-sectional view of a package structure in another embodiment.

Description of the main element symbols:

1000-a package structure; 100-a lead frame; 110-a first connection; 120-a second connection; 130-a third connection; 200-a first chip; 210-a first pin; 220-a second pin; 221-drain lead; 222-source lead; 300-a second chip; 310-a third pin; 320-a fourth pin; 410-leads; 420-a conductive sheet; 430-a conductive block; 500-a shield can; 610-first insulating glue; 620-second insulating glue; 630-third insulating colloid; 640-a fourth insulating colloid; 6401-fin portion; 700-a heat sink; 710-fins.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative and are only for the purpose of explaining the present application and are not to be construed as limiting the present application.

In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

In this application, unless expressly stated or limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can include, for example, fixed connections, removable connections, or integral parts; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

In this application, unless expressly stated or limited otherwise, a first feature is "on" or "under" a second feature such that the first and second features are in direct contact, or the first and second features are in indirect contact via an intermediary. Also, a first feature "on," "above," and "over" a second feature may be directly on or obliquely above the second feature, or simply mean that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

In the conventional chip package structure, two chips are usually connected to a substrate, and corresponding metal contacts on the substrate are connected to a printed circuit board, so that the two chips are interconnected through the printed circuit board. When signal transmission is performed between two chips, a longer transmission distance is needed, which affects the signal transmission efficiency between the two chips.

Therefore, a new solution for chip packaging is needed to be provided, so as to solve the technical problem that the signal transmission efficiency between two chips is affected due to the long signal transmission distance in the existing chip packaging structure.

As shown in fig. 1 and 2, in an embodiment, the package structure 1000 may include a lead frame 100, a first chip 200, and a second chip 300. Wherein the first chip 200 and the second chip 300 are both bonded to the leadframe 100.

Specifically, the lead frame 100 may include a first connection portion 110, several second connection portions 120, and several third connection portions 130 spaced apart from each other. The first chip 200 includes a first lead 210 and a plurality of second leads 220. The first lead 210 may be bonded to the first connection portion 110 of the lead frame 100. The second leads 220 may be bonded to the second connection portions 120 in a one-to-one correspondence. In addition, the second chip 300 may include a third lead 310 and a plurality of fourth leads 320. The third lead 310 may also be bonded to the first connection portion 110 of the lead frame 100. The fourth pins 320 may be bonded to the third connecting portions 130 in a one-to-one correspondence.

Accordingly, the first pin 210 and the third pin 310 may be electrically connected through the first connection part 110, and signal transmission may be achieved. It is understood that data interconnection between the first chip 200 and the second chip 300 may be achieved through the first connection portion 110 of the lead frame 100 for signal transmission.

In the present application, the first chip 200 and the second chip 300 can be directly connected by the first connecting portion 110 in the lead frame 100, so that the signal transmission distance between the first chip 200 and the second chip 300 is greatly shortened, and the signal transmission efficiency between the first chip 200 and the second chip 300 can also be improved. When the first chip 200 or the second chip 300 is used as an execution end, the response speed of the execution end can be increased, and the performance of the corresponding product can be improved. Meanwhile, the high-density arrangement of the package structure 1000 is also facilitated.

Further, as shown in fig. 1, the lead frame 100 may be stamped from a sheet of metal, such as a sheet of copper or copper alloy, or the like. Specifically, corresponding connection portions may be formed at specific positions of the lead frame 100 according to requirements of the chip connected by the lead frame 100, so as to connect pins of the chip.

In some embodiments, the first chip 200 may be a power chip such as a transformer chip, a frequency conversion chip, or a current conversion chip. In an embodiment, the package structure 1000 may include one, two, or four first chips 200. When the package structure 1000 includes a plurality of first chips 200, the plurality of first chips 200 may be arranged in a similar manner. It should be noted that, in the present embodiment, the package structure 1000 including the first chip 200 is taken as an example for detailed description.

In addition, in some embodiments, the first chip 200 may be a transistor having three pins, for example, a field effect transistor, etc. In other embodiments, the first chip 200 may also be a diode or the like.

As shown in fig. 1, the first pin 210 of the first chip 200 may be a gate pin. The side of the first chip 200 where the first leads 210 are provided may be close to the lead frame 100. Also, the first lead 210 may be bonded and connected to the first connection portion 110 of the lead frame 100.

In an embodiment, the first chip 200 may further include two second leads 220, i.e., a drain lead 221 and a source lead 222. Correspondingly, the lead frame 100 further includes two second connection portions 120. The drain lead 221 and the source lead 222 may be respectively configured with a second connection portion 120, that is, the drain lead 221 and the source lead 222 may be respectively connected to a second connection portion 120 in a bonding manner, so as to connect the drain lead 221 and the source lead 222 to an external circuit, thereby forming an electrical circuit. The drain lead 221 may be located on a side of the first chip 200 facing away from the lead frame 100. In some embodiments, the drain lead 221 may be indirectly connected to the corresponding second connection portion 120 through a conductive sheet 420. The source lead 222 may be located on a side of the first chip 200 close to the lead frame 100, and the source lead 222 may be directly connected to the corresponding second connection portion 120 by soldering or the like.

As shown in fig. 1 and 2, in some embodiments, the second chip 300 may be a logic chip such as a central processing unit, a graphics processor, or a microprocessor. Accordingly, the second chip 300 may include a plurality of pins, wherein one pin may be indirectly connected with the first chip 200 through the first connection portion 110 and may perform signal transmission. For convenience of description, a pin connected to the first chip 200 in the second chip 300 may be referred to as a third pin 310, and the other pins in the second chip 300 may be referred to as fourth pins 320.

As shown in fig. 1, in some embodiments, the second chip 300 may be connected to the lead frame 100 by flip-chip bonding. That is, the side of the second chip 300 provided with the third and

fourth leads

310 and 320 may be close to the lead frame 100. The third pin 310 and the fourth pin 320 may be connected to the corresponding connection portions by the conductive bumps 430. The conductive bump 430 may be a block structure having a conductive property, such as a copper bump or a tin bump.

In other embodiments, the second chip 300 may also be bonded to the leadframe 100 by a positive-fit method, as shown in fig. 2. Specifically, the side of the second chip 300 provided with the third and

fourth leads

310 and 320 may be away from the lead frame 100. The third lead 310 and each of the fourth leads 320 may be indirectly connected to the corresponding connection portion of the lead frame 100 through a wire 410.

As shown in fig. 1, in an embodiment, the third lead 310 may be bonded and connected to the first connection portion 110 of the lead frame 100. Therefore, the first chip 200 and the second chip 300 can be connected through the first connection portion 110, and signal transmission can be performed. Compared with the prior art, the signal transmission distance between the first chip 200 and the second chip 300 can be obviously shortened, the signal transmission efficiency between the first chip 200 and the second chip 300 is improved, and the response speed of the first chip 200 can be further improved.

In addition, the number of the third connection parts 130 in the lead frame 100 may be the same as the number of the fourth pins 320. In one embodiment, each of the fourth leads 320 may be configured with a third connection portion 130, and the fourth leads 320 may be bonded and connected to the corresponding third connection portion 130. Thus, the second chip 300 can be easily connected with external lines to form an electrical circuit.

As shown in fig. 1, the package structure 1000 further includes a first insulating encapsulant 610. The first insulating adhesive 610 may be filled in a space between two adjacent connection portions in the lead frame 100. Therefore, the first insulating colloid 610 can protect the adjacent two connection portions from being insulated, and at the same time, the lead frame 100 can form an integral structure. In one embodiment, the first insulating paste 610 may have the same thickness as the lead frame 100.

As shown in fig. 2, in other embodiments, when the second chip 300 is mounted on the lead frame 100, the second chip 300 may be adhered to the first insulating adhesive 610 at a corresponding position, and the first insulating adhesive 610 provides fixing and supporting functions for the second chip 300, so as to improve stability of the second chip 300 during a packaging process, and facilitate subsequent operations such as soldering the leads 410.

In some embodiments, the first insulating gel 610 may be made of an insulating gel including, but not limited to, an epoxy AB gel or an ultraviolet curing gel.

As shown in fig. 3, in some embodiments, the package structure 1000 further includes at least one shielding can 500, and the shielding can 500 can achieve electromagnetic shielding between the first chip 200 and the second chip 300, so as to reduce electromagnetic interference between the first chip 200 and the second chip 300. Especially, when the first chip 200 is a high power chip, the electromagnetic interference between the first chip 200 and the second chip 300 can be significantly improved, the interference to the transmission signal can be reduced, and the integrity of the transmission signal can be improved. It is understood that the shield can 500 may be made of a metal material.

For example, in some embodiments, the package structure 1000 may include a shield can 500. The shielding cover 500 may cover a side of the first chip 200 away from the lead frame 100, and the shielding cover 500 is spaced apart from, i.e. not in contact with, an outer sidewall of the first chip 200.

Of course, in some embodiments, an end of the shielding can 500 near the leadframe 100 may be adhered to a corresponding position of the leadframe 100 by the second insulating glue 620. Thus, the shield can 500 can be fixed to the lead frame 100. Meanwhile, the second insulating colloid 620 may also insulate the connection portions at corresponding positions in the shield case 500 and the lead frame 100, thereby preventing short circuits and the like. In some embodiments, the second insulating paste 620 may be made of an insulating paste including, but not limited to, an epoxy AB paste or an ultraviolet curing paste.

In other embodiments, the shielding can 500 may also be disposed on a side of the second chip 300 away from the lead frame 100 (not shown), and the shielding can 500 may also be spaced apart from an outer sidewall of the second chip 300.

Of course, in other embodiments, the package structure 1000 may include two shielding cases 500, and a side of the first chip 200 and a side of the second chip 300 away from the lead frame 100 may be covered by one shielding case 500 (not shown).

As shown in fig. 1 and 3, a third insulating paste 630 may be disposed between the shield can 500 and the first chip 200. It will be appreciated that the side of the first chip 200 remote from the leadframe 100 is covered with a conductive sheet 420 connected to the drain lead 221. The side of the third insulating paste 630 away from the shield 500 may be adhered to the side of the conductive plate 420 away from the drain lead 221. Therefore, the shield can 500 can be further fixed by the third insulating colloid 630, and a supporting function is provided for the shield can 500, so that the stability of the installation of the shield can 500 is improved. Meanwhile, the third insulating colloid 630 may also be used to protect the shield 500 from the conductive sheet 420.

In some embodiments, the third insulating gel 630 may be made of an insulating gel including, but not limited to, an epoxy AB gel or an ultraviolet curing gel.

As shown in fig. 3, the package structure 1000 further includes a fourth insulating encapsulant 640, which is used to encapsulate the first chip 200 and the second chip 300, and provide protection for the first chip 200 and the second chip 300, such as water resistance, moisture resistance, shock resistance, dust resistance, heat dissipation, and secrecy. Therefore, the stability and reliability of the first chip 200 and the second chip 300 in the working process can be improved, and the service life of the first chip 200 and the second chip 300 can be prolonged.

In an embodiment, the fourth insulating colloid 640 may be disposed on a side of the lead frame 100 close to the first chip 200, and the fourth insulating colloid 640 may cover the first chip 200 and the second chip 300 at the same time. In some embodiments, other empty spaces within the shielding can 500 may be filled with the fourth insulating gel 640, which may further increase the robustness of the shielding can 500.

In some embodiments, the fourth insulating gel 640 may include an insulating gel and an insulating heat transfer medium. The heat-conducting medium can be uniformly mixed in the insulating glue to improve the overall heat conductivity of the fourth insulating glue 640. Therefore, the fourth insulating colloid 640 can rapidly transfer and dissipate heat generated during the operation of the first chip 200 and the second chip 300, so as to reduce heat accumulation on the first chip 200 and the second chip 300. Furthermore, the stability and reliability of the first chip 200 and the second chip 300 during operation can be further improved, and the service lives of the first chip 200 and the second chip 300 can be prolonged.

In some embodiments, the insulating paste may be made of an insulating paste including, but not limited to, an epoxy AB paste or an ultraviolet curing paste. The heat transfer medium may be made of materials including, but not limited to, silicon nitride or silicon carbide.

In other embodiments, the second insulating colloid 620, the third insulating colloid 630, and the first insulating colloid 610 may be made of the same composition as the fourth insulating colloid 640.

Of course, in other embodiments, the fourth insulating gel 640 may only include insulating gel.

As shown in fig. 3, in some embodiments, the fourth insulating encapsulant 640 covers the first chip 200 and the second chip 300 and has a plurality of fin portions 6401, it is understood that the plurality of fin portions 6401 are located on a side of the fourth insulating encapsulant 640 away from the lead frame 100, and the plurality of fin portions 6401 may be spaced apart from each other. Accordingly, an air channel may be formed between two adjacent fin portions 6401, which may increase the contact area between the air and the fourth insulating encapsulant 640 and accelerate the dissipation of heat in the fourth insulating encapsulant 640. Furthermore, the heat dissipation of the first chip 200 and the second chip 300 can be further accelerated.

In other embodiments, a side of the fourth insulating gel 640 away from the leadframe 100 may be a planar structure (not shown).

In other embodiments, as shown in fig. 4, the side of the fourth insulating gel 640 away from the lead frame 100 may be a planar structure. The package structure 1000 may further include a heat dissipation member 700, and the heat dissipation member 700 may be disposed on a side of the fourth insulating encapsulant 640 away from the lead frame 100. In which the heat sink 700 may be made of a material having a large thermal conductivity, such as copper. Accordingly, heat in the fourth insulating gel 640 may be rapidly dissipated outward through the heat sink 700. In addition, the side of the heat dissipation member 700 away from the fourth insulating gel 640 may include a plurality of spaced fins 710, which may increase the contact area between the heat dissipation member 700 and the air. Further, the heat dissipation rate of the heat dissipation member 700 can be further increased, and the heat accumulation of the first chip 200 and the second chip 300 can be reduced.

In summary, in the package structure 1000 provided in the embodiment, the lead frame 100 is used to interconnect the first chip 200 and the second chip 300, so that the signal transmission distance between the first chip 200 and the second chip 300 can be effectively shortened.

In the description of the present specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent.

Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.

Claims

1. A package structure, comprising:

the second chip comprises a third pin and a plurality of fourth pins, the third pin is connected with the first connecting portion, the fourth pins are connected with the third connecting portions in a one-to-one correspondence mode, and the second chip is interconnected with the first chip through the first connecting portions to perform signal transmission.

2. The package structure according to claim 1, wherein a side surface of the second chip on which the third pin and the fourth pins are disposed faces the lead frame, the third pin is connected to the first connection portion by a conductive bump, and the fourth pin is connected to the third connection portion by a conductive bump.

3. The package structure according to claim 1, wherein a side surface of the second chip on which the third pin and the fourth pin are disposed faces away from the lead frame, the third pin is indirectly connected to the first connection portion through a lead, and the fourth pin is also indirectly connected to the third connection portion through a lead.

4. The package structure according to any one of claims 1 to 3, wherein the first connecting portion, the second connecting portions and the third connecting portions are filled with a first insulating paste at positions spaced apart from each other.

5. The package structure of claim 1, further comprising at least one shield;

The shielding case covers the second chip, the shielding case and the outer side wall of the second chip are arranged at intervals, and the shielding case and the contact surface of the lead frame are bonded with second insulating colloid.

6. The package structure of claim 1, further comprising at least one shield;

7. The package structure of claim 1, further comprising a fourth insulating gel;

8. The package structure of claim 7, wherein a plurality of fin portions are disposed on one side of the fourth insulating encapsulant covering the outer surfaces of the first chip and the second chip, and the fin portions are spaced apart from each other.

9. The package structure according to claim 7, further comprising a heat dissipation member disposed on a side of the fourth insulating gel away from the lead frame.