CN110808233A - Packaging structure for system heat dissipation and packaging process thereof - Google Patents
Packaging structure for system heat dissipation and packaging process thereof Download PDFInfo
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- CN110808233A CN110808233A CN201911273682.2A CN201911273682A CN110808233A CN 110808233 A CN110808233 A CN 110808233A CN 201911273682 A CN201911273682 A CN 201911273682A CN 110808233 A CN110808233 A CN 110808233A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention discloses a packaging structure for system heat dissipation and a packaging process thereof. The packaging structure in the invention comprises: a substrate; an active chip mounted on the substrate; the memory chip is attached to the active chip; the heat conductor and the memory chip are attached to the same surface of the active chip, and a second TSV (through silicon via) interconnected with the active chip is arranged on the heat conductor; and the packaging body is used for packaging the active chip, the memory chip and the heat conductor on the substrate, one end of a second TSV on the heat conductor is interconnected with the active chip, and the other end of the second TSV is exposed out of the surface of the packaging body. The invention enlarges the heat dissipation path of the packaging structure, thereby remarkably improving the heat dissipation performance.
Description
Technical Field
The invention relates to the field of chip packaging, in particular to a packaging structure for system heat dissipation and a packaging process thereof.
Background
Currently, the traditional primary path for heat dissipation from a chip includes two aspects, one is the back side of the chip package and the other is the PCB board. At present, heat dissipation is mainly performed by means of active heat dissipation structures such as adding a heat dissipation cover on the surface of a package, improving thermal conductivity of a thermal interface material, adding forced refrigeration and the like, and by means of improving design of a package substrate and the like. Without adding active heat dissipation structures, most of the heat is conducted through the PCB board, which is mainly faced with some low power consumption products. In products requiring the addition of active heat dissipation structures, the primary heat dissipation path has become the chip back-side-heat sink-air path.
Along with the continuous improvement of the semiconductor process technology and the continuous reduction of process nodes, the power consumption of a chip in unit area is greatly improved; meanwhile, as the 3D stacking technology is applied to high-end products, the multilayer chip stacking structure has the problems of too high heat flux density and too small heat dissipation path, so how to dissipate heat becomes one of the keys affecting the performance of the products. And the active heat radiation mode among the prior art is that increase the active heat radiation structure at the back of encapsulation chip, makes the heat on encapsulation chip back surface transmit for the active heat radiation structure more fast, and then discharges the heat at the back more fast, reaches better heat-sinking capability, if: the micro-channel heat dissipation is added, which only increases the heat dissipation speed of the back surface of the packaged chip, but can not fundamentally and effectively improve the problems of overlarge heat flow density and undersize heat dissipation path in the package. Therefore, the problems of too high heat flow density and too small heat dissipation path inside the packaged chip cannot be solved by adopting the traditional heat dissipation method, and the traditional heat dissipation method cannot meet the heat dissipation requirement when facing high-power products, particularly products with high system integration level.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the existing traditional heat dissipation mode can not improve the problems of overlarge heat flow density and undersize heat dissipation path in the packaged chip; the invention provides a packaging structure for system heat dissipation and a packaging process thereof, which solve the problems.
A package structure for system heat dissipation, comprising:
a substrate;
an active chip mounted on the substrate;
the memory chip is attached to the active chip;
the heat conductor and the memory chip are attached to the same surface of the active chip, and a second TSV (through silicon via) interconnected with the active chip is arranged on the heat conductor;
and the packaging body is used for packaging the active chip, the memory chip and the heat conductor on the substrate, one end of a second TSV on the heat conductor is interconnected with the active chip, and the other end of the second TSV is exposed out of the surface of the packaging body.
The back surface of the active chip is attached to the substrate, and the active chip is provided with a first TSV; the memory chip and the heat conductor are both attached to the front surface of the active chip.
The second TSV is disposed in parallel with the first TSV.
A metal heat conducting piece is arranged in the second TSV; the heat conductor is made of silicon or glass.
And one surface of the substrate opposite to the active chip is provided with BGA balls.
The packaging body comprises a first packaging body and a second packaging body, wherein the first packaging body seals the memory chip and the heat conductor on the front surface of the active chip, the second packaging body is positioned between the active chip and the substrate, and the second packaging body is used for filling a gap between the active chip and the substrate.
The height of the heat conductor is higher than that of the memory chip.
A preparation process of a packaging structure for system heat dissipation comprises the following steps:
mounting the memory chip and the heat conductor with the second TSV on the same surface of the active chip;
carrying out plastic package on the active chip, and forming a first packaging body which packages the heat conductor and the memory chip in the internal part after the plastic package;
and cutting the active chip after plastic packaging to prepare a single module, attaching the single module on the substrate, and finally completing the underfill between the active chip and the substrate to form a second packaging body.
Specifically, a process for preparing a package structure for system heat dissipation includes:
mounting the memory chip and the heat conductor with the second TSV on the front surface of the active chip with the first TSV;
carrying out wafer-level plastic package on the front surface of the active chip, and forming a first packaging body which is used for packaging the heat conductor and the memory chip in the internal part after the plastic package;
processing the back surface of the active chip, cutting the wafer to manufacture a single module, and mounting the single module on the substrate to complete the underfill between the active chip and the substrate to form a second packaging body;
after the second package body is formed, ball mounting operation is carried out on the substrate to form BGA balls.
The height of the heat conductor is higher than that of the memory chip, and after the front side of the active chip is subjected to plastic package, the plastic package wafer is thinned until the surface of the heat conductor containing the second TSV is exposed.
Filling a metal medium in the second TSV; the heat conductor is made of silicon or glass.
The technical scheme of the invention has the following advantages:
1. because the traditional heat dissipation method can not improve the problems of overlarge heat flow density and undersize heat dissipation path in the packaged chip, how to improve the heat dissipation capability becomes a feasible direction for improving the heat dissipation performance through the chip packaging technology. However, for high-power products, especially products with high system integration, there are many difficulties in the arrangement of heat dissipation by chip packaging technology, and mainly there are few ways to improve the packaging. The main factors influencing heat dissipation of the chip package include three aspects, namely, the package thickness is smaller, and the thermal resistance is smaller; the larger the area is, the smaller the thermal resistance is; and thirdly, the heat dissipation performance is improved, namely the heat conductivity of the packaging surface structure is increased. In the prior art, the improvement of the heat dissipation performance of the product is generally performed from the thermal conductivity of the material itself due to the structural limitation; for example: the plastic package material and the heat conducting glue with high heat conductivity can improve heat dissipation to a certain extent, but the heat dissipation performance cannot be greatly improved due to the limitation of the materials. According to the invention, by mounting the heat conductor on the active chip and combining the second TSV which is connected with the active chip on the heat conductor, the heat on the active chip can be effectively transferred to the packaging surface through the heat conductor with the minimum thermal resistance, the heat dissipation path of the packaging structure is enlarged, and the heat dissipation performance is further improved; in consideration of the stress of the whole package, the heat conductor in the invention is made of materials matched with the materials of the surrounding chips in the thermal expansion coefficient, such as silicon or glass; meanwhile, as a large amount of silicon or glass materials are added in the plastic package area of the memory chip, the thermal resistance of the memory chip is greatly reduced, the heat dissipation path of the package structure is further obviously enlarged, and the heat dissipation performance of the invention is obviously improved. Meanwhile, the increase of the whole heat conductor is completed in the process of packaging the chip, so that the heat-conducting chip has good flexibility, namely, in the design process of the subsequent scheme, the structure of the heat-conducting chip can be directly and flexibly provided with a heat-radiating cover, a heat-radiating fin and other active and passive heat-radiating devices according to the requirements of products.
2. The structure of the active chip is further optimized, and particularly, the first TSV is arranged on the active chip, so that the back surface of the active chip and the substrate can be interconnected in the arrangement mode, and the possibility of mounting the memory chip on the front surface of the active chip is further provided. Namely, the memory chip can be pasted on the front surface of the active chip by adding the first TSV, so that the shortest interconnection between the active chip and the memory chip is realized, and therefore, the electrical performance can be effectively improved; the heat conductor which is connected with the active chip is added, so that the heat on the memory chip can be transferred to the packaging surface with the minimum thermal resistance, and the heat on the active chip can be effectively led out through the heat radiation path inside the packaging chip enlarged by the heat conductor, so that the heat radiation performance is remarkably improved; in addition, due to the addition of the TSV holes, the heat transfer performance in the vertical direction can be improved, and the purpose of heat dissipation is better achieved.
3. In the process, the preparation of a finished product can be finished only by packaging twice, a heat conductor for improving the heat dissipation performance can be added in the packaging process, and the flexibility of the packaged finished product is greatly improved, namely, in the subsequent scheme design process of using the packaging structure, active and passive heat dissipation devices such as a heat dissipation cover, a heat dissipation fin and the like can be flexibly added on the packaging structure according to needs; in addition, the packaging process is suitable for wafer-level packaging, and has the advantages of high manufacturability, high packaging efficiency and simplicity and convenience in operation.
Drawings
In order to show the product structure of the invention more clearly, the invention also provides the following drawings.
Fig. 1 is a schematic diagram of a package structure for dissipating heat of a system according to the present invention.
Fig. 2 is a flow chart of the packaging process of the present invention.
Description of reference numerals:
1-substrate, 2-active chip, 3-memory chip, 4-heat conductor, 5-packaging body and 6-BGA ball.
Detailed Description
The following examples are provided to further understand the present invention, not to limit the scope of the present invention, but to provide the best mode, not to limit the content and the protection scope of the present invention, and any product similar or similar to the present invention, which is obtained by combining the present invention with other prior art features, falls within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
A package structure for dissipating heat of a system, as shown in fig. 1, comprising: the chip comprises a substrate 1, an active chip 2, a memory chip 3, a heat conductor 4 and a packaging body 5; wherein, the active chip 2 is mounted on the substrate 1; the memory chip 3 is mounted on the active chip 2; the heat conductor 4 and the memory chip 3 are both attached to the same surface of the active chip 2, and a second TSV which is interconnected with the active chip 2 is arranged on the heat conductor 4; the active chip 2, the memory chip 3 and the heat conductor 4 are packaged on the substrate 1 by the packaging body 5, one end of a second TSV on the heat conductor 4 is connected with the active chip 2, and the other end of the second TSV is exposed out of the surface of the packaging body 5.
Through the setting of above-mentioned structure, can be with the heat conduction on the memory chip 3 to active chip 2 on, then through heat conductor 4 with the heat on the active chip 2 through the second TSV with its a large amount of air of deriving, enlarged among the packaging structure the thermal derivation route of chip, show improvement thermal conductivity. Meanwhile, the heat conductor 4 occupies a large volume of the packaging body 5, so that the thermal resistance of the packaging body 5 is effectively reduced, and the efficiency of radiating heat to the air through the packaging body 5 is further improved.
In the invention, the active chip 2 can cover various types of digital chips such as ASIC, CPU, GPU, FPGA and the like, and the chips are characterized by high power consumption; the memory chip 3 is an HBM chip which has single property and is a dynamic memory. The optimized design of the structure of the invention can effectively solve the problem of system heat dissipation after the operation chip and the memory chip are sealed, and the effect is very obvious.
In the invention, the memory chip 3 is attached to the front surface of the active chip 2, the back surface of the active chip 2 is attached to the substrate 1, and the active chip 2 is communicated with the substrate 1 through a lead wire, wherein the lead wire can bypass the active chip 2 and be communicated with the substrate 1, and a first TSV can be arranged on the active chip 2 and is communicated with the substrate 1 through the first TSV on the active chip 2.
In this embodiment, the active chip 2 having the first TSV is selected to communicate with the substrate 1 through the first TSV. The method specifically comprises the following steps: the back surface of the active chip 2 is attached to the substrate 1, the memory chip 3 and the heat conductor 4 are both attached to the front surface of the active chip 2, and the active chip 2 is communicated with the substrate 1 through a first TSV. Through the arrangement of the structure, the shortest interconnection between the active chip 2 and the memory chip 3 can be realized, the electrical performance is better, and compared with the existing packaging structure, the packaging structure has the characteristics of smaller packaging size, simpler structure and lower cost. Meanwhile, the shortest interconnection mode is combined with the first TSV arranged on the active chip 2, so that another heat dissipation path can be effectively provided for the active chip 2, the heat of the active chip 2 is effectively conducted to the substrate 1, the heat is led out through the substrate, and the heat dissipation performance is improved. The first TSV and the second TSV are both silicon chip through holes.
In order to achieve a better heat dissipation effect, the invention also optimizes and sets the specific structures of each part, such as: the second TSV and the first TSV are arranged in parallel, so that the heat transfer performance in the vertical direction is effectively improved; a metal medium is filled in the second TSV, namely, a metal heat conducting piece is arranged in the second TSV, so that the heat conducting performance is effectively improved; set up BGA ball 6 on the one side relative with active chip 2 on the base plate 1, can effectively transmit the heat transfer on the chip conducts base plate 1 through the wire for other bearing material through BGA ball 6, improve heat dispersion. The packaging body 5 comprises a first packaging body which seals the memory chip 3 and the heat conductor 4 on the front surface of the active chip 2, and a second packaging body which is positioned between the active chip 2 and the substrate 1 and realizes gap filling between the active chip 2 and the substrate 1, and the side surface of the active chip 2 can be effectively exposed to the maximum through the structure, so that the heat dissipation performance of the active chip 2 is improved. The height of the heat conductor 4 is higher than that of the memory chip 3, so that the preparation process can be simplified.
Example 2
The embodiment provides a packaging process of a packaging structure for system heat dissipation, as shown in fig. 2, the specific process is as follows:
step one, a memory chip 3 and a heat conductor 4 with a second TSV are attached to the same surface of an active chip 2. In the present invention, the memory chip 3 is mounted on the active chip 2, and then the heat conductor 4 is mounted on the active chip 2. The memory chip 3 can be mounted on the front side of the active chip 2, and can also be mounted on the back side of the active chip 2; when the chip is attached to the back surface, the active chip 2 and the memory chip 3 can be interconnected through leads; when the memory chip 3 is attached to the front surface, the back surface of the memory chip 3 is attached to the front surface of the active chip 2, and at this time, the interconnection between the memory chip 3 and the active chip 2 can be realized through a lead, or the front surface of the memory chip 3 is attached to the front surface of the active chip 2, and at this time, the shortest interconnection between the active chip 2 and the active chip 2 can be effectively realized. In this embodiment, the shortest interconnection between the memory chip 3 and the active chip 2 is effectively achieved by adopting a manner that the front surface of the active chip 2 and the front surface of the memory chip 3 are attached to each other. After the memory chip 3 is mounted on the active chip 2, the thermal conductor 4 is distributed around the memory chip 3 and mounted on the front surface of the active chip 2, as shown in fig. 2. In this embodiment, the central axis of the second TSV on the heat conductor 4 is perpendicular to the front surface of the active chip 2, so that heat in the chip can be better conducted out to the air.
And step two, carrying out plastic package on the active chip 2, and forming a first packaging body which is used for packaging the heat conductor 4 and the memory chip 3 in the internal part after the plastic package. Set up the mode that highly is higher than memory chip 3 with heat conductor 4 in this embodiment, at this moment, the plastic envelope in this step can adopt wafer level plastic envelope, and after first packaging body was all the cladding of heat conductor 4 and memory chip 3 active chip 2, exposed heat conductor 4 in the mode that adopts the cutting attenuate, under the condition that does not damage memory chip 3, realized a plurality of active chip 2's plastic envelope operation simultaneously, the operation is simpler and quick.
And step three, carrying out wafer cutting on the active chip 2 after plastic packaging to manufacture a single module, and arranging a back bump on the single module, so that the single module is conveniently pasted on the substrate 1, as shown in fig. 2. Finally, the single module is mounted on the substrate 1, and the underfill between the active chip 2 and the substrate 1 is completed to form a second package. The first package and the second package in the present invention together constitute the package 5 in the present invention. Before or after the package 5 is completed, a ball mounting process may be performed on the other side of the substrate 1 to mount the BGA balls 6.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (11)
1. A package structure for dissipating heat from a system, comprising:
a substrate (1);
an active chip (2) mounted on the substrate (1);
the memory chip (3) is attached to the active chip (2);
the heat conductor (4) and the memory chip (3) are attached to the same surface of the active chip (2), and a second TSV (through silicon via) interconnected with the active chip (2) is arranged on the heat conductor (4);
and the packaging body (5) is used for packaging the active chip (2), the memory chip (3) and the heat conductor (4) on the substrate (1), one end of a second TSV on the heat conductor (4) is interconnected with the active chip (2), and the other end of the second TSV is exposed out of the surface of the packaging body (5).
2. The packaging structure for system heat dissipation according to claim 1, wherein the active chip (2) is mounted on the substrate (1) at the back side, and the active chip (2) is provided with a first TSV; the memory chip (3) and the heat conductor (4) are both attached to the front surface of the active chip (2).
3. The package structure for dissipating heat from a system according to claim 2, wherein the second TSV is disposed in parallel with the first TSV.
4. The package structure for dissipating heat of a system according to any one of claims 1 to 3, wherein a metal heat conducting member is disposed in the second TSV; the heat conductor (4) is made of silicon or glass.
5. The package structure for dissipating heat of a system as claimed in any of claims 1 to 4, wherein the substrate (1) has BGA balls (6) on a side thereof opposite to the active chip (2).
6. A package structure for system heat dissipation according to any one of claims 1 to 5, wherein the package body (5) comprises a first package body sealing the memory chip (3) and the heat conductor (4) on the front surface of the active chip (2), and a second package body located between the active chip (2) and the substrate (1).
7. The package structure for dissipating heat of a system as claimed in any of claims 1 to 6, wherein the height of the thermal conductor (4) is higher than that of the memory chip (3).
8. A packaging process of a packaging structure for system heat dissipation is characterized by comprising the following steps:
mounting the memory chip (3) and the heat conductor (4) with the second TSV on the same surface of the active chip (2);
the active chip (2) is subjected to plastic packaging, and a first packaging body which is used for packaging the heat conductor (4) and the memory chip (3) is formed after the plastic packaging;
and cutting the active chip (2) after plastic packaging to prepare a single module, attaching the single module on the substrate (1), and finally completing the underfill between the active chip (2) and the substrate (1) to form a second packaging body.
9. The packaging process of the packaging structure for the system heat dissipation according to claim 8, comprising:
attaching a memory chip (3) and a heat conductor (4) with a second TSV to the front side of an active chip (2) with a first TSV;
carrying out wafer-level plastic package on the front surface of the active chip (2), and forming a first packaging body which is used for packaging the heat conductor (4) and the memory chip (3) in the first packaging body after plastic package;
processing the back surface of the active chip (2), then cutting a wafer to manufacture a single module, attaching the single module on the substrate (1), and completing the bottom filling between the active chip (2) and the substrate (1) to form a second packaging body;
after the second package is formed, a ball mounting operation is performed on the substrate (1) to form BGA balls (6).
10. The packaging process of the packaging structure for system heat dissipation according to claim 8 or 9, wherein the height of the heat conductor (4) is higher than that of the memory chip (3), and after the front surface of the active chip (2) is subjected to plastic molding, the plastic molded wafer is thinned until the surface of the heat conductor (4) containing the second TSV is exposed.
11. The packaging process of the packaging structure for system heat dissipation according to any one of claims 8-10, wherein the second TSV is filled with a metal medium, and the material of the thermal conductor (4) is silicon or glass.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911273682.2A CN110808233A (en) | 2019-12-12 | 2019-12-12 | Packaging structure for system heat dissipation and packaging process thereof |
| PCT/CN2019/128945 WO2021114410A1 (en) | 2019-12-12 | 2019-12-27 | Package structure facilitating system heat dissipation, and packaging process thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911273682.2A CN110808233A (en) | 2019-12-12 | 2019-12-12 | Packaging structure for system heat dissipation and packaging process thereof |
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| CN110808233A true CN110808233A (en) | 2020-02-18 |
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| CN201911273682.2A Pending CN110808233A (en) | 2019-12-12 | 2019-12-12 | Packaging structure for system heat dissipation and packaging process thereof |
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| Country | Link |
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| CN (1) | CN110808233A (en) |
| WO (1) | WO2021114410A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112490208A (en) * | 2020-12-31 | 2021-03-12 | 合肥祖安投资合伙企业(有限合伙) | Chip packaging structure with inductor |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113675093A (en) * | 2021-07-14 | 2021-11-19 | 复旦大学 | Packaging design and preparation method of double-sided plastic-packaged heat dissipation structure |
| CN114698230B (en) * | 2022-02-23 | 2023-05-12 | 中国电子科技集团公司第二十九研究所 | Three-dimensional integrated structure of printed circuit board embedded with micro-channels and preparation method thereof |
| CN117393517A (en) * | 2023-12-08 | 2024-01-12 | 成都智多晶科技有限公司 | Wire bonding type packaging structure and substrate capable of effectively enhancing heat dissipation efficiency |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8378480B2 (en) * | 2010-03-04 | 2013-02-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy wafers in 3DIC package assemblies |
| US8526186B2 (en) * | 2011-07-11 | 2013-09-03 | Texas Instruments Incorporated | Electronic assembly including die on substrate with heat spreader having an open window on the die |
| US20130082365A1 (en) * | 2011-10-03 | 2013-04-04 | International Business Machines Corporation | Interposer for ESD, EMI, and EMC |
| CN210607230U (en) * | 2019-12-12 | 2020-05-22 | 上海先方半导体有限公司 | Packaging structure for system heat dissipation |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112490208A (en) * | 2020-12-31 | 2021-03-12 | 合肥祖安投资合伙企业(有限合伙) | Chip packaging structure with inductor |
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| WO2021114410A1 (en) | 2021-06-17 |
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