KR102170197B1 - Package-on-package structures - Google Patents

Abstract

Embodiments of the present invention provide a package-on-package arrangement comprising a first package 804, 904 comprising a substrate layer 116 comprising an upper side 117a, and a lower side 117b opposite the upper side, , Wherein the upper side of the substrate layer forms a generally flat surface 117a, and the first die 118 is bonded to the lower side of the substrate layer. The arrangement also includes a second package 802, 902 comprising a plurality of rows of solder balls 806, 906 and at least one or both of an active or passive component 810, 910, 920 . The second package is attached to a generally flat surface above the substrate layer of the first package through a plurality of rows of solder balls. Active and/or passive components 810, 910, 920 are attached to a generally flat surface above the substrate layer of the first package.

Description

Package-on-package structures {PACKAGE-ON-PACKAGE STRUCTURES}

Cross-reference to related application

It claims priority to U.S. Patent Application No. 14/176,695, filed Feb. 10, 2014, filed Feb. 11, 2013, U.S. Patent Application No. 61/763,285. , The entire specification thereof is incorporated herein by reference. This is also a partial continuation of U.S. Patent Application No. 13/584,027, filed Aug. 13, 2013, claiming priority to U.S. Provisional Application No. 61/525,521, filed Aug. 19, 2011, which The entire specification of are incorporated herein by reference.

Embodiments of the present invention relate to package on package (POP) structures, and more specifically to packaging arrangements incorporating a base package with a die-down flip structure.

The background description provided in this application is generally intended to provide the context of the present invention. In addition to aspects of description that may not be separately recognized as prior art at the time of filing, as a result of it being described in this background section, the work of the presently named inventors is not clearly or implicitly recognized as prior art against the present invention. Does not.

Typically, using many multi-chip packaging arrangements, the packaging arrangement is arranged in one of a package-on-package (PoP) arrangement, or a multi-chip module (MCM) arrangement. These packaging arrangements tend to be very thick (eg, approximately 1.7 millimeters to 2.0 millimeters).

PoP arrangements may include integrated circuits that combine two or more packages on top of each other. For example, a PoP arrangement can be constructed with two or more memory device packages. PoP arrangements can also consist of mixed logic memory stacks including logic in the lower package and memory in the upper package or vice versa.

Typically, the die associated with the package (referred to as "lower package" in this application) located below the PoP arrangement is the footprint of the package (referred to as "lower package" in this application) located above the lower package. Is limited to a predetermined size. Additionally, such a configuration generally limits the top package to two rows of peripheral solder balls. An example of such a packaging arrangement 1100 is illustrated in FIG. 11 and includes an upper package 1102 and a lower package 1104. As shown, the lower package 1104 includes a die 1106 that is attached to the substrate 1108 via an adhesive 1110. The die 1106 has wires 1112 and is bonded to the substrate 1108 through a wire bonding process. Solder balls 1114 are provided to couple the packaging arrangement 1100 to another substrate (not shown), such as, for example, a printed circuit board (PCB). The top package 1102 includes a die 1116 that is coupled to a substrate 1116. Solder balls 1120 are provided to couple the upper package 1102 to the lower package 1104. The top package 1102 may, if desired, include an enclosure 1122, generally in the form of a suture. As can be seen, only two rows of solder balls 1120 will be provided due to the presence of the die 1106 and the enclosure 1124 (generally in the form of encapsulant and may or may not be included) of the lower package 1104. I can. Thus, when the upper packages are attached to the lower package, the upper packages may be required to have larger sizes or footprints to avoid the die 1106 of the lower packages. Such packaging arrangements 1100 may also present problems with clearance issues for the top package 1102 with respect to the die 1106 and/or enclosure 1124.

11 illustrates another example of a packaging arrangement 1200 in which the lower package 1204 is created using a mold-array-process (MAP). The lower package 1204 is similar to the lower package 1104 of FIG. 11 and includes an encapsulant 1206. Encapsulant 1206 is generally etched to expose solder balls 1208. Alternatively, solder balls 1208 are deposited within openings 1210 after encapsulant 1206 is etched. Such packaging arrangement 1200 again allows the inclusion of only two rows of solder balls 1120 around the periphery of the top package 1102 due to the presence of the die 1106 and encapsulant 1206 again. Such packaging arrangements 1200 may also present problems with alignment issues for openings 1210, as well as clearance issues for top package 1102 for die 1106 and encapsulant 1206. have.

In various embodiments, the present invention includes a package-on-package arrangement, wherein the package-on-package arrangement is a first package, the substrate layer including (i) an upper side, and (ii) a lower side opposite to the upper side. Wherein the upper side of the substrate layer comprises the substrate layer and a first die coupled to the lower side of the substrate layer forming a generally flat surface. The package on package arrangement also includes a second package comprising a plurality of rows of solder balls and at least one or both of (i) an active component or (ii) a passive component. The second package is attached to the generally flat surface of the upper side of the substrate layer of the first package through the plurality of rows of solder balls. At least one of one or both of the (i) active component or (ii) the passive component is attached to the generally flat surface of the upper side of the substrate layer of the first package.

In various embodiments, the present invention also includes providing a first package comprising a substrate layer, wherein the substrate layer comprises (i) an upper side, and (ii) a lower side opposite the upper side, The upper side of the substrate layer forms a generally flat surface, and the first package further includes a first die coupled to the lower side of the substrate layer. The method includes providing the second package having a plurality of rows of solder balls attached to a lower surface of the second package, the second package through the plurality of rows of solder balls of the second package. Attaching to the generally flat surface of a first package, and (i) an active component or (ii) at least one or both of a passive component, the generally flat surface of the upper side of the substrate layer of the first package. It further includes attaching to the surface.

Various embodiments potentially include one or more of the following advantages. Packaging arrangements may provide a reduced pincount, according to various embodiments described herein. Further, higher speeds may be realized for electronic devices using packaging arrangements according to various embodiments described in this application.

Embodiments of the present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals indicate elements of similar structure. The embodiments of the present application are illustrated by way of example and not as limitation in the drawings of the accompanying drawings.
1A schematically illustrates exemplary packaging arrangements including an exemplary die arrangement of a die-down flip PoP structure.
1B schematically illustrates the exemplary packaging arrangement of FIG. 1A with an upper package attached to a lower package.
2 schematically illustrates another exemplary packaging arrangement including another exemplary die arrangement of a die-down flip PoP structure with exposed material to provide a path for heat dissipation.
3 schematically illustrates another exemplary packaging arrangement including another exemplary die arrangement of an exposed die-down flip PoP structure to provide a path for heat dissipation.
4 schematically illustrates another exemplary packaging arrangement including another exemplary die arrangement of a die-down flip PoP structure with through-silicon vias (TSVs).
5 schematically illustrates another exemplary packaging arrangement including another exemplary die arrangement of a die-down flip PoP structure with an embedded printed circuit board (PCB) and/or an interposer.
6 schematically illustrates another exemplary packaging arrangement including another exemplary die arrangement of a die-down flip PoP structure with a PCB/interposer.
7 is a process flow diagram of a method for fabricating PoP structures described in this application.
8 schematically illustrates an exemplary packaged device arrangement and another exemplary packaging arrangement comprising passive and/or active electronic components.
9 schematically illustrates another exemplary packaging arrangement comprising multiple dies and passive and/or active electronic components.
10 is another process flow diagram of a method for fabricating PoP structures described in this application.
11 schematically illustrates an exemplary PoP packaging arrangement.
12 schematically illustrates another exemplary PoP packaging arrangement.

1A illustrates a packaging arrangement 100 according to an embodiment in which a package on package (PoP) packaging arrangement includes an upper package 102 and a lower package 104. For illustrative purposes, packages are illustrated as individual items. The upper package 102 includes a substrate layer 106. The die arrangement in the upper package 102 may include a first die 108 and a second die 110, where each die 108, 110 is provided with a substrate layer 106 through solder balls 112. Is attached to This configuration may include an underfill material 114 in the space between the solder balls 112 and the substrate layer 106. The solder balls 112 are generally located in bond pads or contact areas (not shown). Dies 108 and 110 may be coupled to the substrate layer 106 through a flip-chip operation. Alternatively, a wire bonding process and an adhesive layer (not shown) may be used to bond the dies 108 and 110 to the substrate layer 106. Additionally, top package 102 may include two or more separate top packages 102 (not shown), each individual top package 102 comprising one or more dies.

According to various embodiments, the first die 108 and the second die 110 are memory devices, and according to an embodiment, the first die 108 and the second die 110 are mobile double data for mobile devices. Rate (mDDR) synchronous dynamic random access memory (DRAM). Mobile DDR is also known as low power DDR. However, other types of memory including, but not limited to, double data rate synchronous dynamic random access memory (DDR SDRAM), dynamic random access memory (DRAM), NOR or NAND flash memory, static random access memory (SRAM), etc. Memory devices can be used.

According to another embodiment, the top package 102 with the first die 108 and the second die 110 is for custom products, and according to an embodiment, the first die 108 and/or the second die 108 Die 110 may represent application specific integrated circuits (ASICs) for mobile devices.

The upper package 102 further includes a plurality of solder balls 115. The plurality of solder balls 115 may be attached to the lower side of the substrate layer 106 of the upper package 102. In the embodiment of FIG. 1A, the plurality of solder balls 115 form a configuration for electrically and physically attaching or stacking the upper package 102 on the lower package 104.

For clarity, the materials used within the upper package 102 and other components within the upper package 102 may not be illustrated and/or described in detail in this application. Such materials and components are generally well known in the art.

The lower package 104 includes a substrate layer 116 including an upper side 117a and a lower side 117b. 1A, the upper side 117a forms a generally flat surface of the lower package 104, ie, a generally smooth surface that is generally free of grooves, protrusions, marks, recesses, and the like. In one embodiment, the generally flat surface of the top 117a does not include any configurations, which allows the top 117a to accommodate (or support) various designs and options of the top package 102. Thus, the flat top surface of the lower package 104 provides a convenient way for the plurality of solder balls 115 of the upper package 102 to attach to the lower package 104, which is Designing the individual top packages 102 of and thereby allows greater flexibility in designing the packaging arrangement 100.

The lower package 104 includes a die 118 attached to the lower side 117b of the substrate layer 116 through an adhesive layer 120 in a die-down flip structure. In other embodiments, as will be discussed further in this application, the die 118 may be attached to the lower side 117b of the substrate layer 116 through solder balls.

In various embodiments, die 118 may be a memory device, such as a mobile double data rate (mDDR) synchronous dynamic random access memory (DRAM) for a mobile device. Other types of memory devices including, but not limited to, double data rate synchronous dynamic random access memory (DDR SDRAM), dynamic random access memory (DRAM), NOR or NAND flash memory, static random access memory (SRAM), etc. Can be used. According to another embodiment, the die 118 may be a logic device for creating a mixed logic memory stack including logic on the lower package 104 and memory on the upper package 102.

Die 118 has surfaces comprising one or more bond pads 122a, 122b. One or more of the bond pads 122a, 122b generally comprise an electrically conductive material such as, for example, aluminum or copper. Other suitable materials may be used in other embodiments. The die 118 is coupled to one or more substrate pads 124a, 124b positioned on the substrate layer 116 through bonding wires 126a, 126b coupled to the corresponding bond pads 122a, 122b. . The die 118 may be secured to the lower package 104 by a molding material. In other embodiments, die 118 may be electrically interconnected with substrate layer 116 through flip chips or conductive adhesives. The electrical signals of die 118 may include, for example, input/output (I/O) signals and/or power/ground to an integrated circuit (IC) device (not shown) formed on die 118. I can.

According to an embodiment, the lower package 104 is created through a mold-array-process (MAP). The lower package 104 further includes an enclosure 128, generally in the form of a sealant. Enclosure 128 is etched to expose solder balls 129. Alternatively, after etching the enclosure 128, solder balls 129 are added to the etched openings 131 of the enclosure 128. The solder balls 130 are added to the solder balls 129 and may be used to couple the packaging arrangement 100 to a substrate (not shown), such as, for example, a printed circuit board (PCB), another package, or the like. Alternatively, single solder balls (bonded solder balls 129 and solder balls 130) are added to the etched openings 131 after etching the enclosure 128. The solder balls 130 are generally around or on the sides of the lower package 104, thereby forming a ball grid array (BGA).

For the sake of clarity, materials used within the lower package 104 and other components within the lower package 104 are not illustrated and/or described in detail in this application. Such materials and components are generally well known in the art.

1B illustrates a packaging arrangement 100 with an upper package 102 attached to a lower package 104. In the embodiment of FIGS. 1A and 1B, a plurality of solder balls 115 form a configuration for electrically and physically attaching or stacking the upper package 102 to the lower package 104. As previously mentioned, the top package 102 may include two or more separate top packages that are attached to the bottom package 104.

Additional embodiments of the present invention generally relate to packaging arrangements having a die-down flip structure and including various embodiments of the lower package 104 illustrated in FIGS. 2-6. For the sake of brevity, the components illustrated in FIGS. 1A and 1B that are the same or similar to those of FIGS. 2 to 7 are not discussed further in this application.

2 illustrates another embodiment of a packaging arrangement 200 comprising an upper package 102 and a lower package 204. In the embodiment of FIG. 2, a thermally conductive material 206 is included on the underside of die 118. In an embodiment, the thermally conductive material 206 is attached to the underside of the die 118 through an adhesive layer 208. Thermally conductive material 206 includes, but is not limited to, metal, silicon, or any material suitable for good thermal conduction.

The lower package 204 includes thermal interface materials (TIMs) 210 that are bonded to a thermally conductive material 206. The TIM 210 includes, but is not limited to, a film, a grease composition, and an underfill material. The film can be an ultra-thin thermally conductive material, which can be prepared by depositing an amorphous material. The grease composition may include a composition with high thermal conductivity and good dispersing properties. A typical TIM is a white paste or thermal grease, typically a silicone oil filled with aluminum oxide, zinc oxide, or boron nitride. Some types of TIMs use micronized or ground silver. Another type of TIM includes phase change materials. Phase change materials are generally solid at room temperature, but at operating temperatures they liquefy and behave like grease.

The underfill material can be selected based on the desired physical properties. Thus, the thermally conductive material 206 provides a path for heat dissipation to the TIM 210. The packaging arrangement 200 may be coupled to a substrate (not shown) such as, for example, a PCB or other packaging arrangement. A hole may be provided in the substrate to accommodate the TIM 210.

3 illustrates an embodiment of a packaging arrangement 300 comprising an upper package 102 and a lower package 304. The die 118 is attached to the substrate layer 116 through solder balls 306. According to various embodiments, an underfill material 308 is provided between the die 118 and the substrate layer 116 of the solder balls 306. The underfill material 308 provides protection for the joints formed by the solder balls 306. It also prevents cracking and delamination of the inner layers of the die 118. The underfill material 308 may be a high purity, low stress liquid epoxy. In general, the larger the size of the solder balls 306, the less the need for underfill material 308 is.

The lower package 304 includes a contact thermal conductor (TIM) 310 that is coupled to the rear surface of the die 118. The TIM 310 includes, but is not limited to, a film, a grease composition, and an underfill material, as previously described. In the embodiment of Figure 3, the back side of die 118 is exposed. The exposed rear surface of die 118 provides a path for heat dissipation to TIM 310. The packaging arrangement 300 may be coupled to a substrate (not shown) such as, for example, a PCB or other packaging arrangement. A hole may be provided in the substrate to receive the TIM 310.

4 illustrates an embodiment of a packaging arrangement 400 including an upper package 102 and a lower package 404. The die 118 is attached to the substrate layer 116 through solder bumps 306. An underfill material 308 is provided in the gap positioned between the die 118 and the substrate layer 116 of the lower package 404. The underfill material 308 provides protection for the joints formed by the solder balls 306.

In the embodiment of FIG. 4, die 118 includes through-silicon vias (TSVs) 406. In embodiments, die 118 may be embedded within enclosure 128 to help expose the backside of die 118. TSVs 406 are vertical electrical connections vias (vertical interconnect access) that pass through die 118 to solder balls 306. In an embodiment, the lower package 404 includes additional solder balls 408 attached to the lower package 404. Additional solder balls 408 may be used for ground/power and input/outputs, for example.

One or more TSVs 406 are electrically coupled to bond pads (not shown) and are generally filled with an electrically conductive material, such as copper, to route electrical signals through die 118. When the density of vias is generally high and the length of the connections is shorter compared to bondwires, TSVs 406 tend to provide improved performance compared to bondwires. The exposed rear surface of the die 118 provides heat dissipation of the lower package 404. Thus, the packaging arrangement 400 can provide increased pincount and higher speeds for electronic devices using the packaging arrangement 400.

5 illustrates an embodiment of a packaging arrangement 500 including an upper package 102 and a lower package 504. Die 118 is attached to the substrate layer 510 through solder bumps 306.

In the embodiment of FIG. 5, the lower package 504 includes one or more PCBs and/or interposers 506 that are attached to the underside of the die 118. According to various embodiments, the PCB/interposer 506 is bonded to the die 118 using a thermal compression process or a solder reflow process. That is, one or more electrically conductive structures (e.g., fillers, bumps, pads, redistribution layer) are used to form a bond between the PCB/interposer 506 and the die 118. And formed on the die 118.

In some embodiments, both die 118 and PCB/interposer 506 comprise a material (eg, silicon) having the same or similar coefficient of thermal expansion (CTE). Using a material with the same or similar CTE for die 118 and PCB/interposer 506 reduces the stress associated with heating and/or cooling mismatches of the materials.

The PCB/interposer 506 provides a physical buffer, support, and reinforcement for the die 118, particularly while forming one or more layers for embedding the die 118 within the enclosure 128. That is, the die 118 coupled to the PCB/interposer 506 as described in this application is a protected integration that is more structurally resistant to the stresses associated with manufacturing the enclosure 128 than if the die 118 alone. Provides a circuit structure, resulting in an improved yield and reliable lower package 504.

In an embodiment, the lower package 504 includes additional solder balls 512. Additional solder balls 512 attached to the PCB/interposer 506 can be used for ground/power and input/outputs, for example.

6 illustrates an embodiment of a packaging arrangement 600 comprising an upper package 102 and a lower package 604. The die 118 is attached to the substrate layer 116 through an adhesive layer 120. As illustrated, die 118 is bonded to substrate layer 116 via a wire bonding process.

Solder bumps 606 are attached to the underside of die 118. The PCB or interposer 608 is attached to the solder balls 606. In embodiments, the PCB/interposer 608 may be exposed or buried. In an embodiment, the lower package 604 includes additional solder balls 610. Additional solder balls 610 may be used for ground/power and input/outputs, for example. The embodiment of FIG. 6 may allow for additional pin counts and provides a path through the PCB/interposer 608 for heat dissipation of the lower package 604.

7 illustrates an exemplary method 700, according to an embodiment of the present invention. At 702, method 700 includes providing a first package comprising a substrate layer, wherein the substrate layer comprises (i) an upper side, and (ii) a lower side opposite the upper side, and the upper side of the substrate layer. Forms a generally flat surface, and the first package further includes a die coupled to the underside of the substrate layer.

At 704, method 700 includes providing a second package having a plurality of rows of solder balls attached to a lower surface of the second package.

At 706, method 700 includes attaching the second package to the generally flat surface of the first package through the plurality of rows of solder balls of the second package.

8 illustrates a packaging arrangement 800 including a lower package 804. As can be seen, the lower package 804 is illustrated as being arranged in the same or similar to the lower package 104 illustrated in FIGS. 1A and 1B. However, the lower package 804 may be arranged in the same or similar to the lower packages 204, 304, 404, 504 and 604 as illustrated in FIGS. 2 to 6, if desired. For the sake of brevity, the components illustrated in FIGS. 1A and 1B and described for the lower package 104 are not discussed further in this application.

The packaging arrangement 800 includes one or more packaged devices 802 that can be coupled to the upper side 117a of the substrate layer 116 of the lower package 804 through solder balls 806. Packaged device 802 can be attached to various components and/or dies (not shown) with packaged device 802 thereon to create packaged device 802 through various methods. A substrate layer 808 may be optionally included. Accordingly, the packaged device 802 may include one or more dies (not shown) that are memory devices. For example, the package device may be similar to the top package 102 illustrated in FIGS. 1-6. The packaged device 802 may include one or more dies (not shown) in the form of double data rate (mDDR) synchronous dynamic random access memory (DRAM) for a mobile device. Mobile DDR is also known as low power DDR. However, other types of memory including, but not limited to, double data rate synchronous dynamic random access memory (DDR SDRAM), dynamic random access memory (DRAM), NOR or NAND flash memory, static random access memory (SRAM), etc. Memory devices can be used. Alternatively, one or more dies of packaged device 802 may represent application specific integrated circuits (ASICs) for mobile devices.

The packaging arrangement 800 further includes one or more passive and/or active electronic components 810. The passive and/or active components 810 may be attached to the top side 117a of the substrate 116 in any suitable manner. For example, the passive and/or active electronic components 810 may be attached to the upper side 117a of the substrate 116 through leads 812 and solder 814. Examples of passive components 810 include, but are not limited to, capacitors, resistors, conductors, transformers, transducers, sensors, and antennas. Other examples of passive components include, but are not limited to, networks, such as a resistor capacitor (RC) circuit and an inductor capacitor (LC) circuit. Examples of active components 810 are, but are not limited to, semiconductor dies, integrated circuits, diodes (e.g., light emitting diodes (LEDs), laser diodes, etc.), optoelectronic devices and power supplies. Include. Signals from packaged device 802 and/or passive/active electronic components 810 may be routed through substrate 116. The packaging arrangement 800 may include a plurality of lower packages 804 arranged on top of each other, if desired. The plurality of lower packages 804 may be arranged identically to each other or differently from each other.

9 illustrates another example of a packaging arrangement 900 similar to the packaging arrangement 800 of FIG. 8. Again, the packaging arrangement 900 is illustrated as including a lower package 904 arranged in the same or similar to the lower package 104 illustrated in FIGS. 1A and 1B. The packaging arrangement 904 is arranged identically or similar to the lower packages 204, 304, 404, 504 and 604 illustrated in FIGS. 2-6 if desired. For the sake of brevity, the components illustrated in FIGS. 1A and 1B and described for the lower package 104 are not discussed further in this application.

The packaging arrangement 900 includes a die 902 that is a flip chip attached to the upper side 117a of the substrate 116 of the lower package 904 with solder balls 906. One or more passive and/or active components 910 are attached to the upper side 117a of the substrate 116 of the lower package 904. Passive and/or active electronic components 910 may be attached to the upper side 117a of the substrate 116 in any suitable manner. For example, the passive and/or active components 910 may be attached to the upper side 117a of the substrate 116 through leads 912 and solder 914. Examples of passive components 910 include, but are not limited to, capacitors, resistors, conductors, transformers, transducers, sensors, and antennas. Other examples of passive components include, but are not limited to, networks, such as a resistor capacitor (RC) circuit and an inductor capacitor (LC) circuit. Examples of active components 910 are, but are not limited to, semiconductor dies, integrated circuits, diodes (e.g., light emitting diodes (LEDs), laser diodes, etc.), optoelectronic devices and power supplies. Include.

The packaging arrangement 900 also includes a die 916 that is attached to the upper side 117a of the substrate 116 of the lower package 904. The die 912 is wire bonded to the upper side 117a of the substrate 116 of the lower package 904 through wires 918. The adhesive layer 920 may be used to attach the die 916 to the upper side 117a of the substrate 116. Signals 902 from the die, passive/active electronic components 910 and/or die 916 may be routed through the substrate 116 of the lower package 904. The packaging arrangement 900 may include a plurality of lower packages 904 arranged on top of each other, if desired. The plurality of lower packages 904 may be arranged identically to each other or differently from each other.

10 illustrates an exemplary method 1000, according to an embodiment of the present invention. At 1002, method 1000 includes providing a first package comprising a substrate layer, wherein the substrate layer comprises (i) an upper side, and (ii) a lower side opposite the upper side, and the upper side of the substrate layer. Forms a generally flat surface, and the first package further includes a die coupled to the underside of the substrate layer.

At 1004, method 1000 includes providing a second package having a plurality of rows of solder balls attached to a lower surface of the second package.

At 1006, method 1000 includes attaching the second package to the generally flat surface of the first package through the plurality of rows of solder balls of the second package.

At 1008, method 1000 includes attaching at least one of (i) an active component or (ii) one or both of the passive components to a generally flat surface above the substrate layer of the first package.

This description may use perspective based descriptions such as up/down, over/under, and/or, or top/bottom, for example. Such descriptions have been used merely to facilitate discussion, and are not intended to limit the application of the embodiments described in this application in any particular direction.

For the purposes of the present invention, the phrase “A/B” means A or B. For the purposes of the present invention, the phrase “A and/or B” means “(A), (B), or (A and B)”. For the purposes of the present invention the phrase "at least one of A, B and C" means "(A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C)". For the purposes of the present invention, the phrase “(A)B” means “(B) or (AB)” ie A is an optional element.

The various operations are described as a number of separate operations in sequence, in a manner that is most helpful in understanding the claimed invention. However, the order of description should not be considered to mean that these operations are necessarily order dependent. In particular, these operations may not be performed in the order presented. The described operations may be performed in a different order than the described embodiments. Various additional operations may be performed and/or described operations may be omitted in additional embodiments.

The description uses the phrases “in an embodiment”, “in an embodiment”, or a similar expression, each of which may refer to one or more of the same or different embodiments. Additionally, as used for embodiments of the present invention, terms such as “having”, “including”, and “having” are synonymous.

Chips, integrated circuits, monolithic devices, semiconductor devices, dies, and microelectronic devices are usually used interchangeably in the field of microelectronics. The present invention is applicable to all of the above as is generally understood in the field.

Additional aspects of the invention relate to one or more of the following.

The package on package arrangement further includes a second die attached to the generally flat surface above the substrate of the first package.

The second die is wire bonded to a generally flat surface above the substrate layer of the first package.

The second die is attached to a generally flat surface above the substrate layer of the first package through a flip-chip process.

The package on package arrangement further includes an adhesive layer positioned between the first die and the substrate layer. The adhesive layer attaches the first die to the underside of the substrate layer of the second package.

The package-on-package arrangement further includes a bond pad positioned on the lower side of the first die, and a substrate pad positioned on the lower side of the substrate layer of the second package. The bond pads of the die are coupled to the substrate pads of the substrate layer to route the electrical signals of the first die through wires.

The plurality of rows of solder balls includes first solder balls, and the package-on-package arrangement includes second solder balls attached to the lower side of the substrate layer to electrically connect the first die to the substrate layer of the second package. 2 The package further includes an underfill material positioned between the substrate layer and the second solder balls.

The plurality of rows of solder balls include first solder balls, and the package-on-package arrangement further includes second solder balls attached to the lower side of the second package, and the second solder balls form a ball grid array thereby. Is located around the periphery of the second package.

The plurality of rows of solder balls includes first solder balls. The substrate layer includes a first substrate layer. The first package further includes a second die arranged next to the first die. Each of the first die and the second die is connected to a second substrate layer in the first package through second solder balls.

The package on package arrangement further includes a contact heat conduction material attached to the underside of the first die.

The package on package arrangement further comprises a thermally conductive material attached to the contact thermally conductive material.

The contact heat conductive material includes one of a film, a grease composition, or an underfill material.

Either (i) an interposer or (ii) a printed circuit board is attached to the bottom of the die.

The plurality of rows of solder balls includes a first plurality of rows of solder balls, the package-on-package arrangement includes a third package including a second plurality of rows of solder balls, and the first package includes a first plurality of The third package is attached to the generally flat surface of the second package through the rows of solder balls of the second package, and the third package is attached to the generally flat surface of the second package through the second plurality of rows of solder balls.

The plurality of rows of solder balls include first solder balls, and the package-on-package arrangement includes second solder balls attached to the lower side of the substrate layer and the upper side of the first die, and the second solder balls positioned on the first die. A plurality of through-silicon vias each extending between at least a portion, and a plurality of third solder balls attached to a lower side of the lower package are further included.

The method further includes attaching the second die to a generally flat surface above the substrate of the first package.

Attaching the first die to the underside of the substrate layer includes attaching the first die to the underside of the substrate layer through an adhesive layer.

The plurality of rows of solder balls includes first solder balls and attaching the first die to the lower side of the substrate layer includes attaching the first die to the lower side of the substrate layer through the second solder balls.

The method further includes providing an underfill material between (i) the second solder balls and (ii) a space positioned between the first die and the underside of the substrate layer of the first package.

The method includes providing on a first die a bond pad positioned on a lower side of the first die; Providing a substrate pad positioned on the substrate layer under the substrate layer of the first package; And coupling the bond pad on the first die to the substrate pad on the substrate layer to thereby route electrical signals of the first die through a wire bonding process.

The plurality of rows of solder balls include first solder balls and the method includes attaching second solder balls to a lower side of a first package, wherein the second solder balls are located on the right and left sides of the first package. do.

The method further includes attaching a contact heat conductor to the underside of the first die.

The plurality of rows of solder balls include first solder balls, and the method includes: attaching second solder balls on an underside of a substrate layer; Attaching the first die to the underside of the substrate layer through second solder balls; And providing through-silicon vias in the first die to connect the second solder balls to the third solder balls attached to the lower side of the first package.

The plurality of rows of solder balls comprises first solder balls and the method includes attaching second solder balls to the underside of the first die; And (i) bonding one of the interposer or (ii) the printed circuit board to the second solder balls.

The plurality of rows of solder balls includes a first plurality of rows of solder balls, and the method includes providing a third package having a second plurality of rows of solder balls attached to a lower surface of the third package, and 2, via the plurality of rows of solder balls, attaching the third package to the generally flat surface of the first package.

Although certain embodiments have been illustrated and described in this application, a wide variety of alternative and/or equivalent embodiments or implementations calculated to achieve the same purposes are illustrated and described without departing from the scope of the present invention. Can be replaced. The present invention is intended to cover adjustments or variations of the embodiments discussed in this application. Accordingly, it is expressly intended that the embodiments described in this application may be limited only by the claims and their equivalents.

Claims (36)

As a package on package structure,
First package; And
Includes a second package,
The first package,
a substrate layer comprising (i) a top side, and (ii) a bottom side opposite to the upper side, wherein the upper side of the substrate layer forms a flat surface;
A die coupled to the lower side of the substrate layer;
An encapsulant covering the die;
A ball grid array (BGA) of first solder balls in recesses of the encapsulant; And
A non-weld process includes second solder balls dissolved into the first solder balls in the recesses of the encapsulant, and the second solder balls are i) recesses of the encapsulant Partially embedded in, ii) partially protruding over the suture, the portion of the second solder ball protruding over the suture is spherical, smooth, and has sharp features. Not;
The second package includes a plurality of rows of third solder balls, wherein the plurality of rows of the third solder balls i) extend across the flat surface of the upper side of the substrate layer of the first package And ii) on a die coupled to the lower side of the substrate layer of the first package, and the second package is a flat surface of the upper side of the substrate layer of the first package through a plurality of rows of the third solder balls. Package on package structure, characterized in that attached to the. The method of claim 1,
And an adhesive layer disposed between the die and the substrate layer, wherein the adhesive layer attaches the die to the lower side of the substrate layer of the first package. The method of claim 1,
A bond pad located on the lower side of the die; And
A substrate pad located on the lower side of the substrate layer of the first package
It further includes,
Wherein the bond pad of the die is connected to the substrate pad of the substrate layer through a wire to route electrical signals of the die. The method of claim 1,
The substrate layer comprises a first substrate layer;
The second package includes a first die formed next to a second die; And
Each of the first die and the second die is connected to a second substrate layer in the second package through fourth solder balls. The method of claim 4,
At least some of the plurality of rows of the third solder balls are positioned between i) the first and second dies of the second package and ii) the dies coupled to the lower side of the substrate layer. Package-on-package structure. The method of claim 1,
A package-on-package structure, further comprising thermal interface materials attached to a lower side of the die. The method of claim 6,
A package-on-package structure, further comprising a thermally conductive material attached to the contact thermally conductive materials. The method of claim 7,
The package-on-package structure, wherein the thermal contact conductive materials comprise one of a film, a grease composition, or an underfill material. The method of claim 1,
Fourth solder balls attached to a lower side of the substrate layer and an upper side of the die; And
Further comprising a plurality of through-silicon vias positioned on the die,
Each of the plurality of through-silicon vias extends between i) at least a portion of the fourth solder balls and ii) a plurality of fifth solder balls attached to a lower side of the die. As a stackable semiconductor package,
First package; And
Including a second package,
The first package,
a substrate layer comprising (i) a top side, and (ii) a bottom side opposite to the upper side, wherein the upper side of the substrate layer forms a flat surface;
A die coupled to the lower side of the substrate layer;
A sealing material covering the die;
A ball grid array (BGA) of first solder balls in the recesses of the encapsulant;
The second solder balls and the second solder balls dissolved into the first solder balls in the recesses of the encapsulant are i) partially buried in the recesses of the encapsulant, and ii) the encapsulant by a first distance Partially protrudes upward; And
i) electrically connected to the lower side of the die through an interposer and ii) including third solder balls protruding above the encapsulant by a second distance equal to the first distance,
The second package includes a plurality of rows of fourth solder balls, wherein the plurality of rows of the fourth solder balls i) extend across the flat surface of the upper side of the substrate layer of the first package , ii) on a die coupled to the lower side of the substrate layer of the first package, the second package on the flat surface of the upper side of the substrate layer of the first package through a plurality of rows of the fourth solder balls A stackable semiconductor package, characterized in that attached. The method of claim 10,
And an adhesive layer positioned between the die and the substrate layer, wherein the adhesive layer attaches the die to the lower side of the substrate layer of the first package. The method of claim 10,
A bond pad located on the lower side of the die; And
A substrate pad located on the lower side of the substrate layer of the first package
It further includes,
The bond pad of the die is connected to the substrate pad of the substrate layer through a wire to route electrical signals of the die. The method of claim 10,
The substrate layer comprises a first substrate layer;
The second package includes a first die formed next to a second die; And
Each of the first die and the second die is connected to a second substrate layer in the second package through fifth solder balls. The method of claim 10,
A stackable semiconductor package, further comprising thermal interface materials attached to the lower side of the die. The method of claim 14,
A stackable semiconductor package, further comprising a thermally conductive material attached to the contact thermally conductive materials. The method of claim 15,
The stackable semiconductor package, wherein the thermal contact conductive materials comprise one of a film, a grease composition, or an underfill material. The method of claim 10,
A stackable semiconductor package, further comprising a printed circuit board attached to the lower side of the die. The method of claim 10,
Fifth solder balls attached to a lower side of the substrate layer and an upper side of the die; And
Further comprising a plurality of through-silicon vias positioned on the die,
Each of the plurality of through-silicon vias extends between at least a portion of the fifth solder balls and a plurality of third solder balls attached to the lower side of the die. The method of claim 10,
A stackable semiconductor package, further comprising fifth solder balls attached to a lower side of the substrate layer and an upper side of the die. As a method of forming a package on package structure,
Forming a first package, forming the first package,
(i) forming a substrate layer including a top side, and (ii) a bottom side opposite to the top side, wherein the top side of the substrate layer forms a flat surface;
Bonding a die to the lower side of the substrate layer;
Covering the die with an encapsulant;
Forming a ball grid array (BGA) of first solder balls in recesses of the encapsulant; And
Forming second solder balls, each of the second solder balls being dissolved into a corresponding one of the first solder balls in the recesses of the encapsulant by a non-weld process, , The second solder balls are i) partially buried in the recesses of the encapsulant, ii) partially protruding over the encapsulant, and a portion of the second solder balls protruding over the encapsulant is spherical. Is smooth, and does not have sharp features;
Forming a second package, forming the second package,
Forming a plurality of rows of third solder balls, wherein the plurality of rows of third solder balls i) extend across the flat surface of the upper side of the substrate layer of the first package, ii) over a die coupled to the underside of the substrate layer of the first package;
Attaching the second package to the upper flat surface of the substrate layer of the first package through the plurality of rows of the third solder balls;
Attaching fourth solder balls to a lower side of the substrate layer and an upper side of the die; And
Forming a plurality of through-silicon vias in the die,
Each of the plurality of through-silicon vias may extend between i) at least a portion of the fourth solder balls and ii) a plurality of fifth solder balls attached to the lower side of the die. Way. The method of claim 20,
The step of bonding the die to the lower side of the substrate layer,
The method of forming a package-on-package structure, comprising bonding the die to the lower side of the substrate layer of the first package using an adhesive layer positioned between the die and the substrate layer. The method of claim 20,
Forming a bond pad on the lower side of the die; And
Forming a substrate pad on the lower side of the substrate layer of the first package; And
And connecting the bond pad of the die to the substrate pad of the substrate layer through a wire to route electrical signals of the die. The method of claim 20,
The substrate layer includes a first substrate layer, the die includes a first die, and forming the second package includes forming a second die next to a third die in the second package. Including more,
Each of the second die and the third die is connected to a second substrate layer in the second package through sixth solder balls. The method of claim 23,
At least some of the plurality of rows of the third solder balls are positioned between i) the second and third dies of the second package and ii) the dies coupled to the lower side of the substrate layer of the first package. A method of forming a package-on-package structure, characterized in that. The method of claim 20,
And attaching thermal interface materials to the lower side of the die. The method of claim 25,
And attaching a thermally conductive material to the contact thermally conductive materials. The method of claim 25,
The method of forming a package-on-package structure, wherein the thermal contact conductive materials include one of a film, a grease composition, or an underfill material. As a method of forming a stackable semiconductor package,
Forming a first package, forming the first package,
(i) forming a substrate layer including a top side, and (ii) a bottom side opposite to the top side, wherein the top side of the substrate layer forms a flat surface;
Bonding a die to the lower side of the substrate layer;
Covering the die with an encapsulant;
Forming a ball grid array (BGA) of first solder balls in recesses of the encapsulant;
Forming second solder balls, wherein each of the second solder balls is dissolved into a corresponding one of the first solder balls in the recesses of the encapsulant, and the second solder balls are i) recesses of the encapsulant Partially embedded in, ii) partially protruding over the suture by a first distance; And
i) forming third solder balls electrically connected to the die through an interposer and ii) protruding over the encapsulant by a second distance equal to the first distance;
Forming a second package, forming the second package,
Forming a plurality of rows of fourth solder balls, wherein the plurality of rows of the fourth solder balls i) extend across the flat surface of the upper side of the substrate layer of the first package, ii) over a die coupled to the underside of the substrate layer of the first package;
Attaching the second package to the upper flat surface of the substrate layer of the first package through a plurality of rows of the fourth solder balls;
Attaching third solder balls to a lower side of the substrate layer and an upper side of the die; And
Forming a plurality of through-silicon vias in the die,
Each of the plurality of through-silicon vias extends between at least a portion of the third solder balls and a plurality of fourth solder balls attached to a lower side of the die. The method of claim 28,
And attaching the die to the lower side of the substrate layer of the first package by using an adhesive layer positioned between the die and the substrate layer. The method of claim 29,
A method of forming a stackable semiconductor package, further comprising attaching a printed circuit board to a lower side of the die. The method of claim 28,
Forming a bond pad on the lower side of the die; And
Forming a substrate pad on the lower side of the substrate layer of the first package; And
And connecting the bond pad of the die to the substrate pad of the substrate layer through a wire to route electrical signals of the die. The method of claim 28,
The substrate layer comprises a first substrate layer, and forming the second package further comprises forming a first die next to a second die in the second package,
Each of the first die and the second die is connected to a second substrate layer in the second package through fifth solder balls. The method of claim 28,
And attaching thermal interface materials to the lower side of the die. The method of claim 33,
And attaching a thermally conductive material to the contact thermally conductive materials. The method of claim 33,
The method of forming a stackable semiconductor package, wherein the thermal contact conductive materials comprise one of a film, a grease composition, or an underfill material. The method of claim 28,
And attaching fifth solder balls to a lower side of the substrate layer and an upper side of the die.

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