CN211858627U

CN211858627U - Semiconductor packaging structure

Info

Publication number: CN211858627U
Application number: CN202020763680.3U
Authority: CN
Inventors: 吴忠武; 何颖彦
Original assignee: Joulwatt Technology Hangzhou Co Ltd
Current assignee: Joulwatt Technology Co Ltd
Priority date: 2020-05-11
Filing date: 2020-05-11
Publication date: 2020-11-03
Anticipated expiration: 2030-05-11

Abstract

The utility model provides a semiconductor packaging structure, including the encapsulation main part, be located the fin of this encapsulation main part bottom, the fin by the encapsulation main part is inside to one side extend to the outside, the opposite side of encapsulation main part is equipped with a plurality of pin, the inside at least one chip unit that is equipped with of this encapsulation main part, the fin is located the inside part setting of encapsulation main part is in the below of chip unit. The utility model discloses let the fin that undertakes heat dissipation function replace the region at original partial pin place for the fin can not receive the interference of both sides pin, thereby can let the fin not receive the extension of constraining, improve packaging structure's whole heat dispersion.

Description

Semiconductor packaging structure

Technical Field

The utility model belongs to the technical field of the semiconductor technology and specifically relates to a semiconductor cooling fin device, packaging structure and packaging method are related to.

Background

In semiconductor packages, heat sinks (heat bumps), including built-in and exposed types, are widely used as package options for the following purposes: a. good thermal conductivity, and is used as an effective heat dissipation way for a semiconductor with high calorific value; b. good conductivity, can form shielding effect through grounding connection, and can effectively increase the capability of the semiconductor for resisting electromagnetic wave interference (EMI).

The traditional SOP packaging is convenient to use, not only is suitable for a red glue production process, but also is suitable for a solder paste production process, but also has poor heat dissipation condition of the packaging structure, the application power density is very limited, and the ESOP packaging structure is proposed to improve the heat dissipation condition of the packaging, but is only suitable for the solder paste process, the heat dissipation condition in the red glue process is not well solved, and the added heat dissipation welding disc is arranged at the bottom of the packaging and has pins at two sides, so that the integral heat dissipation performance is not facilitated by adding a copper-clad mode.

In order to improve the heat dissipation capability, chinese patent CN207474443U discloses a 16-pin high-density integrated circuit package structure, in which a semiconductor heat sink is disposed at the bottom of a package casing, a half of the semiconductor heat sink is disposed inside the casing, the top of the half of the semiconductor heat sink disposed inside the casing is connected to a substrate, the substrate is parallel to the bottom of the casing, two sides of the substrate are connected to enclosing plates and a sealed cavity is formed between the enclosing plates and the casing, the half of the semiconductor heat sink disposed inside the casing is located in the cavity, a heat dissipation fan is further disposed outside the package casing, and the heat dissipation performance of a chip can be improved by combining the heat dissipation fan and the heat sink.

However, the heat dissipation structure in this patent needs a very large heat dissipation space, and tends to result in the overall enlargement of the volume of the package structure, which cannot be applied to some flat package structures, and meanwhile, such package structure is complicated in internal structure, leads to a complicated package process, has a high cost, and is not favorable for marketization popularization.

Therefore, there is a need for an improved heat dissipation technology for a package structure in the prior art, so as to overcome the technical problems in the prior art.

Disclosure of Invention

In view of this, an object of the present invention is to provide a new semiconductor package structure, which designs a new heat dissipation structure at the bottom of the package body, and replaces the original region with the heat dissipation plate having heat dissipation function, so that the heat dissipation plate is not interfered by the pins on both sides, and the heat dissipation plate is not constrained to extend, thereby improving the overall heat dissipation performance of the package structure.

According to the utility model discloses a semiconductor package structure that purpose provided, including the encapsulation main part, be located the fin of this encapsulation main part bottom, the fin by the encapsulation main part is inside to one side extension to the outside, the opposite side of encapsulation main part is equipped with a plurality of pin, the inside at least one chip unit that is equipped with of this encapsulation main part, the fin is located the inside part setting of encapsulation main part is in the below of chip unit.

Preferably, the bottom surface of the heat sink is exposed outside the bottom of the package body and is flush with the bottom of the package body.

Preferably, at least one pin is further disposed on a side of the heat sink extending out of the package body.

Preferably, a high-power chip unit and a control chip unit are arranged inside the package body, wherein the heat sink is located below the high-power chip unit.

Preferably, the chip unit includes at least one chip and a lead frame for placing the chip, and the heat sink is embedded in one surface of the package body and contacts with the lead frame.

Preferably, the chip unit includes at least one chip and a lead frame for placing the chip, and a space is provided between one surface of the package body, in which the heat sink is embedded, and the lead frame.

Preferably, the plurality of pins extend inwards to the lead frame, the chip is provided with a plurality of input/output ports, and the plurality of input/output ports are connected to the corresponding pins through leads.

Preferably, the package body comprises a package casing formed by curing the package adhesive, the package casing is a flat cuboid, and the area of the heat sink is at least greater than 1/4 of the area of the bottom of the package casing.

Compared with the prior art, the technical scheme of the utility model owing to let the fin occupy an area alone to also be different from the scheme of evenly distributed in the packaging body both sides among the prior art in the design of pin, make the utility model provides a pin and fin can mutual noninterference, and this kind of design is favorable to the heat dissipation of fin itself and follow-up extension to heat radiation structure, thereby improves the holistic heat-sinking capability of packaging structure. Furthermore, because the utility model discloses a fin simple structure easily realizes, can promote the market competition ability of producing the piece.

Drawings

Fig. 1 is a bottom view of a package structure according to a first embodiment of the present invention.

Fig. 2 is a plan view of a package structure according to a first embodiment of the present invention.

Fig. 3 is a front view of a package structure according to a first embodiment of the present invention.

Fig. 4 is a schematic view of an internal structure of a package structure according to a first embodiment of the present invention.

Fig. 5 is a cross-sectional view taken along line AA of fig. 4.

Fig. 6 is an internal schematic view of a package structure according to a second embodiment of the present invention.

Fig. 7 is a bottom view of a package structure according to a third embodiment of the present invention.

Detailed Description

The present invention will be described in detail with reference to the specific embodiments shown in the drawings, but the embodiments are not limited to the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.

As described in the background art, the heat dissipation structure in the conventional semiconductor package structure is limited by the constraints of the pins on the two sides, so that the ideal heat dissipation capability cannot be achieved, or the heat dissipation capability is improved by the complex heat dissipation structure on the premise of sacrificing the volume of the package structure, which not only affects the use of the product, but also improves the production cost, and is not favorable for market competition.

Therefore, the utility model discloses a solve this problem, provided a simple structure, the heat dissipation scheme of easily realizing, can solve prior art promptly, the device pin improves the holistic heat-sinking capability of device to the restraint problem of fin, can avoid the volume increase of device again, problem that the cost rises.

The technical solution of the present invention will be described in detail through the following embodiments.

Referring to fig. 1-3, fig. 1-3 are a bottom view, a top view and a front view of a semiconductor package structure according to a first embodiment of the present invention. As shown in the figure, the semiconductor package structure includes a package body 10, the package body 10 includes a package housing 13 formed by curing a package adhesive, the package housing 13 is generally a flat rectangular parallelepiped, and in other applications, the package housing 13 may also have other geometric shapes, such as a flat cylinder, a flat triangular prism, and so on.

At the bottom of the package body 10, a heat sink 11 is provided, the heat sink 11 extends from the inside of the package body 10 to the outside to one side, and the protruding portion is smaller than the portion remaining inside the package body 10. Different from the prior art, in the utility model discloses in, the part that fin 11 stretches out has occupied the position at original a plurality of pin place for this regional pin is replaced by fin 11. Thus, even if other heat dissipation materials are coated on the heat dissipation plate 11, or other heat dissipation structures, such as heat dissipation fins, air cooling heat dissipation members, water cooling heat dissipation members, etc., are added to the heat dissipation plate 11, they are not constrained by the original two-side pins.

In the embodiment shown in fig. 1, the bottom surface of the heat sink 11 is exposed to the outside of the bottom of the package body 10 and is flush with the bottom of the package body 10. The exposed ground of the heat sink 11 is not only more beneficial to heat dissipation, but also can be added with additional heat dissipation means, such as adding air cooling or external heat dissipation structures such as heat dissipation fins, on the exposed ground, thereby improving the heat dissipation capability of the device. Of course, in other embodiments, the upper and lower surfaces of the heat sink 11 may be covered in the package body 10, and only one side of the heat sink 11 is exposed, so that the mechanical bonding strength between the heat sink 11 and the package body 10 can be improved.

The heat sink 11 may be a metal plate or a heat sink made of other materials. Preferably, the area of the heat sink 11 is at least 1/4 greater than the area of the bottom of the package housing 13, as shown in the figure. Generally, the larger the area of the heat sink is, the better the heat dissipation effect is, and certainly, the space of a part of the package and the position arrangement of the internal devices are sacrificed under the excessively large heat dissipation area, so that the actual size of the heat sink needs to be designed according to the comprehensive consideration of the device performance and the heat dissipation requirement.

Referring to fig. 1 again, in the present embodiment, the other side of the package body 10 is provided with a plurality of pins 12, and at least one pin 12 is further provided on the same side of the heat sink 11 extending out of the package body 10. The pins 12 on the same side are spaced from the heat sink 11 by a certain distance to ensure a heat dissipation space of the heat sink 11, and the number of the pins 12 on the same side is determined by the requirement of the internal device, and the length of the side of the package housing 13 is also taken into consideration.

Referring to fig. 4 and 5, fig. 4 is a schematic view of the interior of the device according to the first embodiment, and fig. 5 is a cross-sectional view taken along line AA in fig. 4. As shown in the figure, two

chip units

15 and 16 are disposed inside the package body 10, wherein the chip unit 15 is a control chip unit, and the chip unit 16 is a high-power chip unit, such as a high-power MOS transistor. In this embodiment, since the heat quantity of the chip unit 16 is large and the heat quantity of the chip unit 15 is relatively small, the portion of the heat sink 11 located inside the package body 10 is disposed below the chip unit 16, so that the heat emitted from the high-power chip unit can be dissipated by the heat sink 11. The heat sink 11 may of course also extend below the chip unit 15. In other embodiments, the number of the chip units may depend on the actual use situation, and at least one chip unit should be included.

Referring to fig. 5 again, inside the package body 10, the chip unit 16 includes at least one chip 161 and a lead frame 162 on which the chip 161 is placed, and the heat sink 11 is embedded in one surface of the package body and contacts with the lead frame 162. Generally, the lead frame 162 is made of copper material, which has a good thermal conductivity, so that the heat generated on the chip 161 can be directly conducted to the heat sink 11 through the lead frame 162. In actual manufacturing, the heat sink 11 may be fixed to the lead frame 162 by an adhesive layer.

A plurality of bonding pads for wire bonding are disposed on the inward extending portions of the plurality of leads 12 on one side of the package body 10, and a plurality of input/output ports are disposed on the chip 161 and connected to the corresponding leads through wires 163. In the illustrated embodiment, the leads 163 are led out from the lead frame 162, and in other embodiments, the leads 163 may also be led out directly from the chip 161, in which case the chip 161 is often a surface mount chip, and the input/output ports thereof face away from the lead frame 162.

Referring to fig. 6, fig. 6 is a schematic view of an interior of a package structure according to a second embodiment of the present invention. As shown in the drawing, in the second embodiment, the heat sink 21 is embedded in the package body 20 with a space between the lead frame 262 and the one surface thereof, and is not in direct contact with the lead frame 262, so that the heat sink 21 does not directly contact the lead frame 262, and therefore, the chip 261 is not affected by the electrical performance of the heat sink 21. In order to manufacture the package structure of this embodiment, the heat sink 21 needs to be inserted into a predetermined position when the package adhesive is applied, and then the package adhesive is cured to relatively fix the heat sink 21. Other parts are the same as those in the first embodiment and are not described again.

Referring to fig. 7, fig. 7 is a bottom view of a package structure according to a third embodiment of the present invention. As shown, in this third embodiment, the heat sink 31 occupies one side of the package body 30, i.e. one leg 32 is disposed entirely on the other side of the package body 30, while no pin is disposed on the side where the heat sink 31 is disposed. Thus, all chips inside the package body 30 can be within the function range of the heat sink 31, and the design of the pins 32 can be simplified only by considering one side, and certainly, the number of pins can be determined according to the overall requirement of the device. Other parts are the same as those in the first embodiment and are not described again.

To sum up, the utility model provides a new semiconductor package structure through letting the fin occupy an area alone to also be different from the scheme of evenly distributed in the packaging body both sides among the prior art in the design of pin, make the utility model provides a pin and fin can mutual noninterference, and this kind of design is favorable to the heat dissipation of fin itself and follow-up extension to heat radiation structure, thereby improves the holistic heat-sinking capability of packaging structure. Furthermore, because the utility model discloses a fin simple structure easily realizes, can promote the market competition ability of producing the piece.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

Claims

1. A semiconductor package structure, characterized in that: the packaging structure comprises a packaging body and a radiating fin positioned at the bottom of the packaging body, wherein the radiating fin extends to the outside from one side inside the packaging body, a plurality of pins are arranged on the other side of the packaging body, at least one chip unit is arranged inside the packaging body, and the radiating fin is positioned below the chip unit.

2. The semiconductor package structure of claim 1, wherein: the bottom surface of the heat sink is exposed outside the bottom of the package body and is flush with the bottom of the package body.

3. The semiconductor package structure of claim 1, wherein: at least one pin is further arranged on one side of the heat radiating fin, which extends out of the packaging main body.

4. The semiconductor package structure of claim 1, wherein: the packaging body is internally provided with a high-power chip unit and a control chip unit, wherein the heat radiating fin is positioned below the high-power chip unit.

5. The semiconductor package structure of claim 1, wherein: the chip unit comprises at least one chip and a lead frame for placing the chip, and the heat sink is embedded into one surface of the packaging body and is in contact with the lead frame.

6. The semiconductor package structure of claim 1, wherein: the chip unit comprises at least one chip and a lead frame for placing the chip, and the radiating fin is embedded into one surface of the packaging body and is spaced from the lead frame.

7. The semiconductor package structure of claim 5 or 6, wherein: the plurality of pins extend inwards to the lead frame, the chip is provided with a plurality of input/output ports, and the plurality of input/output ports are connected to the corresponding pins through leads.

8. The semiconductor package structure of claim 1, wherein: the encapsulation main part includes the encapsulation casing that is formed by the solidification of encapsulation glue, the flat cuboid of encapsulation casing, wherein the area of fin is greater than at least 1/4 of encapsulation casing bottom area.