CN217134355U - Semiconductor power device packaging structure - Google Patents
Semiconductor power device packaging structure Download PDFInfo
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- CN217134355U CN217134355U CN202221127349.8U CN202221127349U CN217134355U CN 217134355 U CN217134355 U CN 217134355U CN 202221127349 U CN202221127349 U CN 202221127349U CN 217134355 U CN217134355 U CN 217134355U
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- pin
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- packaging
- heat dissipation
- power device
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Abstract
The utility model discloses a semiconductor power device packaging structure, including chip, lead frame and packaging body, the lead frame includes base plate, first pin and second pin, the chip sets up on the base plate, first pin and base plate integrated into one piece, first pin is through base plate and chip electric connection, the second pin is through the bridging of heat dissipation copper sheet and chip electric connection inside the packaging body; the packaging body is used for plastically packaging the chip and the lead frame, the bottom surface of the substrate is exposed, and the first pin and the second pin extend to the outer side of the packaging body. The surface of the heat dissipation copper sheet of the utility model is exposed on the front side of the packaging body, the area of the heat dissipation copper sheet can be automatically adjusted according to the needs, the heat dissipation area is larger than that of the traditional packaging, and the heat dissipation effect is better; meanwhile, the packaging thermal resistance, especially Rthja, can be greatly reduced.
Description
Technical Field
The utility model relates to the field of semiconductor technology, specifically a semiconductor power device packaging structure.
Background
The packaging structure of the electronic component mainly comprises a chip, pins and the like which are arranged in a plastic package body, wherein the pins are used for leading out the leading-out ends of an internal circuit of the chip so as to connect the chip with an external circuit or an external device through the pins.
The traditional packaging form has low packaging efficiency through a wire bonding process, the area ratio of the chip to the packaging body is far smaller than 1:1, so that the final overall dimension of an electronic product is influenced, and the traditional packaging form cannot meet the requirement of miniaturization development of the electronic product.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a semiconductor power device packaging structure to solve the above-mentioned problem that proposes.
In order to achieve the above object, the present invention provides a semiconductor power device package structure, which includes a chip, a lead frame and a package body, wherein the lead frame includes a substrate, a first pin and a second pin, the chip is disposed on the substrate, the first pin and the substrate are integrally formed, the first pin is electrically connected to the chip through the substrate, and the second pin is electrically connected to the chip through a heat dissipation copper sheet bridge inside the package body;
the packaging body is used for plastically packaging the chip and the lead frame, the bottom surface of the substrate is exposed, and the first pin and the second pin extend to the outer side of the packaging body.
Preferably, the surface of the heat dissipation copper sheet is exposed on the front surface of the packaging body.
Preferably, the first pin and the second pin are respectively disposed at two opposite sides of the package body.
Preferably, tin-climbing recessed areas are formed in the outer sides of the first pin and/or the second pin.
Preferably, the first pin and/or the second pin is a gull pin.
Compared with the prior art, the utility model discloses following beneficial effect has:
(1) the utility model discloses a second pin is through the bridging of heat dissipation copper sheet and chip electric connection, and the heat dissipation copper sheet can also play the radiating action as electric connector's while, and bigger packaging body can be adopted in this kind of pin design to can set up bigger semiconductor power device, improve the encapsulation utilization ratio.
(2) The surface of the heat dissipation copper sheet of the utility model is exposed on the front side of the packaging body, the area of the heat dissipation copper sheet can be automatically adjusted according to the needs, the heat dissipation area is larger than that of the traditional packaging, and the heat dissipation effect is better; meanwhile, the packaging thermal resistance, especially Rthja, can be greatly reduced.
(3) The utility model discloses a tin depressed area has been seted up in the outside of first pin and/or second pin and has climbed the tin effect better.
Drawings
Fig. 1 is a front view of a semiconductor power device package structure according to an embodiment of the present invention;
fig. 2 is a side cross-sectional view of a semiconductor power device package structure according to an embodiment of the present invention;
fig. 3 is a rear view of a semiconductor power device package structure according to an embodiment of the present invention.
In the figure: the package comprises a package body 1, a substrate 2, a first pin 3, a second pin 4, a heat dissipation copper sheet 5 and a tin-climbing recessed area 6.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Fig. 1 shows a front view of a semiconductor power device package structure of this embodiment, which includes a chip, a lead frame and a package 1, wherein the lead frame includes a substrate 2, a first pin 3 and a second pin 4, the chip is disposed on the substrate 2 (not shown in the figure), the first pin 3 and the substrate 2 are integrally formed, the first pin 3 is electrically connected to the chip through the substrate 2, and the second pin 4 is bridged inside the package 1 through a heat dissipation copper sheet 5 and electrically connected to the chip.
As shown in fig. 1 and 2, the surface of the heat-dissipating copper sheet 5 is exposed on the front surface of the package body 1, the area of the heat-dissipating copper sheet 5 can be automatically adjusted according to needs, and the heat-dissipating area is larger than that of the conventional package, so that the heat-dissipating effect is better; meanwhile, the packaging thermal resistance, especially Rthja, can be greatly reduced. The radiating copper sheet 5 can also play a role in heat dissipation while being used as an electric connector, and the pin design can adopt a larger packaging body 1, so that a larger semiconductor power device can be arranged, and the packaging utilization rate is improved.
It should be noted that, the surface of the heat dissipation copper sheet 5 exposed on the front surface of the package body 1 is only a preferred embodiment, not the whole of the present invention, the heat dissipation copper sheet 5 is completely sealed in the package body 1, and the heat dissipation copper sheet 5 only plays a role of bridging at this moment, and does not have a heat dissipation function any more.
As shown in fig. 2, the package 1 encapsulates the chip, the substrate 2, a portion of the first pins 3, a portion of the second pins 4, and the heat sink copper sheet 5, as shown in fig. 3, the bottom surface of the substrate 2 is exposed, the first pins 3 and the second pins 4 extend to the outer side of the package 1, and the positions of the first pins 3 and the second pins 4 are respectively located at two opposite sides of the package 1. Those skilled in the art can understand how to bridge the second leads 4 inside the package 1 through the heat sink copper sheet 5 to electrically connect with the chip, which is a common technical means in the art and will not be described herein again.
In a preferred embodiment, the outer sides of the first leads 3 and/or the second leads 4 are provided with solder-climbing recessed regions 6, so as to achieve a better solder-climbing effect.
In other embodiments, the first pin 3 and/or the second pin 4 are gull legs.
It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (5)
1. A semiconductor power device packaging structure is characterized by comprising a chip, a lead frame and a packaging body, wherein the lead frame comprises a substrate, a first pin and a second pin, the chip is arranged on the substrate, the first pin and the substrate are integrally formed, the first pin is electrically connected with the chip through the substrate, and the second pin is electrically connected with the chip through a radiating copper sheet bridge inside the packaging body;
the packaging body is used for plastically packaging the chip and the lead frame, the bottom surface of the substrate is exposed, and the first pin and the second pin extend to the outer side of the packaging body.
2. The semiconductor power device package structure of claim 1, wherein a surface of the heat sink copper sheet is exposed at a front surface of the package body.
3. The semiconductor power device package structure of claim 1, wherein the first lead and the second lead are disposed at opposite sides of the package body.
4. The semiconductor power device package structure of claim 1, wherein a solder-climbing recessed region is formed on an outer side of the first lead and/or the second lead.
5. The semiconductor power device package of claim 1, wherein the first pin and/or the second pin is a gull pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221127349.8U CN217134355U (en) | 2022-05-12 | 2022-05-12 | Semiconductor power device packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221127349.8U CN217134355U (en) | 2022-05-12 | 2022-05-12 | Semiconductor power device packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217134355U true CN217134355U (en) | 2022-08-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202221127349.8U Active CN217134355U (en) | 2022-05-12 | 2022-05-12 | Semiconductor power device packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217134355U (en) |
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2022
- 2022-05-12 CN CN202221127349.8U patent/CN217134355U/en active Active
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