CN210535651U

CN210535651U - Heat abstractor based on DFN encapsulation

Info

Publication number: CN210535651U
Application number: CN201921191424.5U
Authority: CN
Inventors: 杨国江; 陈益忠; 夏昊天; 陈炜; 徐成; 于世珩; 毛嘉云; 刘健; 汤振凯; 徐伟
Original assignee: Jiangsu Changjing Technology Co Ltd
Current assignee: Jiangsu Changjing Technology Co.,Ltd.
Priority date: 2019-07-26
Filing date: 2019-07-26
Publication date: 2020-05-15
Anticipated expiration: 2029-07-26

Abstract

The utility model relates to a heat abstractor based on DFN encapsulation, including the MOSFET chip, electrically conductive base plate and epoxy layer, the upper surface of MOSFET chip is equipped with source electrode and grid, the lower surface is equipped with the drain electrode, electrically conductive base plate comprises radiating area and lead frame, the central authorities' base island of lead frame and the lower surface of MOSFET chip combine, the radiating area is located the MOSFET chip under and is connected through soft solder layer electricity between the lower surface of MOSFET chip, the epoxy layer wraps up whole MOSFET chip and fixes mutually with the top of lead frame, the top of MOSFET chip is equipped with the fin, the bottom both sides of fin are equipped with the projection, the top both sides of MOSFET chip be equipped with projection assorted slot, the drain electrode department of MOSFET chip bottom is provided with the heat dissipation alloy. The utility model discloses a top at the MOSFET chip is equipped with the heat dissipation copper sheet, and it can be with the heat direction fin that the chip during operation produced, reinforcing heat dispersion.

Description

Heat abstractor based on DFN encapsulation

Technical Field

The utility model relates to an electronic packaging technical field especially relates to a heat abstractor based on DFN encapsulation.

Background

With the development of electronic products, consumer electronic products such as notebook computers, mobile phones, mini CDs, palm computers, CPUs, digital cameras, etc. are increasingly developing toward miniaturization. As products are made smaller and thinner, how heat generated by millions of transistors dissipates becomes ー issues that have to be considered. In the prior art, the trend of increasing the heating density still cannot be avoided. The problem of heat dissipation is not solved, so that the reliability of the product is affected due to overheating of the power device, the service life of the product is seriously shortened, and even the product is damaged .

At the present stage, the MOS tube has relatively high packaging internal resistance and poor heat dissipation. Utilize neotype ultra-thin DFN packaging structure can the greatly reduced internal resistance, heat dispersion obtains promoting by a wide margin, and the application is more extensive. At present, chinese patent application No. CN102842550A discloses a DFN package structure of a power MOSFET chip, which conducts heat on the chip away by providing a heat dissipation region and then providing a soft solder layer connection between the heat dissipation region and the chip.

This prior art mainly dispels the heat through the environment contact with the external world, but this prior art's heat radiation structure is limited with the area of external contact, therefore heat dispersion is comparatively general.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a heat abstractor based on DFN encapsulation to solve the problem that meets in the above-mentioned background art.

In order to achieve the above purpose, the technical scheme of the utility model is as follows:

the utility model provides a heat abstractor based on DFN encapsulation, includes MOSFET chip, electrically conductive base plate and epoxy layer, the upper surface of MOSFET chip is equipped with source electrode and grid, and the lower surface is equipped with the drain electrode, electrically conductive base plate comprises radiating area and lead frame, the central authorities' base island of lead frame combines with the lower surface of MOSFET chip, the radiating area is located the MOSFET chip under and is connected through soft solder layer electricity between the lower surface of MOSFET chip, the epoxy layer wraps up whole MOSFET chip and is fixed mutually with the top of lead frame, the top of MOSFET chip is equipped with the fin, the bottom both sides of fin are equipped with the projection, the top both sides of MOSFET chip be equipped with projection assorted slot, the drain electrode department of MOSFET chip bottom is provided with the heat dissipation alloy.

In the above scheme, the heat sink is a copper sheet.

In the scheme, the top of the radiating fin is uniformly provided with a plurality of grooves.

In the above scheme, the groove is an inwards concave rectangular groove.

In the scheme, the top of the epoxy resin layer is uniformly provided with semicircular transverse grooves.

In the scheme, the radiating fin is attached to the MOSFET chip through the heat conducting material.

Compared with the prior art, the beneficial effects of the utility model are that: through being equipped with the fin at the top of MOSFET chip, the fin is close to this side laminating of this side of chip with the good heat conduction material of heat conductivity together of one side of chip, because the copper sheet has better heat dispersion, consequently it can be with the heat direction fin that the chip during operation produced to with the heat more efficient conduction to the fin on the chip, reinforcing heat dispersion. Meanwhile, the copper sheet is good in conductivity, and when the copper sheet is connected with the electrode of a chip, the copper sheet is good in conductivity, so that the overcurrent capacity of components can be increased, and the effect of reducing the internal resistance value is achieved.

Drawings

FIG. 1 is a schematic view of the overall structure of the present invention;

FIG. 2 is a schematic view of the connection structure of the MOSFET chip and the lead frame of the present invention;

reference numbers in the figures: 1-MOSFET chip; 11-a slot; 12-a heat-dissipating alloy; 2-a lead frame; 21-central base island; 3-a heat sink; 31-a convex column; 32-grooves; 4-epoxy resin layer.

Detailed Description

The technical solution of the present invention will be further described in detail with reference to the accompanying drawings and embodiments.

As shown in fig. 1 and 2, a DFN package-based heat dissipation device includes a MOSFET chip 1, a conductive substrate and an epoxy layer 4, wherein a source and a gate are disposed on an upper surface of the MOSFET chip 1, a drain is disposed on a lower surface of the MOSFET chip 1, the conductive substrate is composed of a heat dissipation area and a lead frame 2, the central substrate 21 of the lead frame 2 is combined with the lower surface of the MOSFET chip 1, the heat dissipation area is located right below the MOSFET chip 1 and is electrically connected with the lower surface of the MOSFET chip through a soft solder layer, and the epoxy layer 4 surrounds the whole MOSFET chip 1 and is fixed to the top of the lead frame 2. The above is the prior art and will not be repeated here.

Different from the prior art, the top of the MOSFET chip 1 is provided with a heat sink 3, and the heat sink 3 is a copper sheet, but an aluminum sheet can also be adopted. One side of the radiating fin 3 is in contact with the external environment, and one surface, close to the MOSFET chip 1, of the radiating fin 3 is attached to the side of the MOSFET chip 1 through a heat conduction material with good heat conductivity, so that the radiating area is greatly increased. The heat conduction material with good heat conductivity is silver-doped solder, and has high combination degree and good heat dissipation. And (3) coating solder paste on the upper surface of the MOSFET chip 1, and welding the solder paste with the radiating fin 3 (copper sheet) after reflow soldering to complete the packaging structure.

Because the copper sheet has better heat dispersion, consequently it can lead the heat that the chip during operation produced to fin 3 to with the heat conduction of the on-chip high efficiency to fin 3, reinforcing heat dispersion. Meanwhile, the copper sheet is good in conductivity, and when the copper sheet is connected with the electrode of a chip, the copper sheet is good in conductivity, so that the overcurrent capacity of components can be increased, and the effect of reducing the internal resistance value is achieved.

Be equipped with projection 31 in the bottom both sides of fin 3, be equipped with in MOSFET chip 1's top both sides with projection 31 assorted slot 11, projection 31 and slot 11's cooperation, be convenient for with MOSFET chip 1 and fin 3 more firm connection, make both be difficult to separate, projection 31 is made by heat sink material, it can be with MOSFET chip 1 during operation produced heat direction fin 3, thereby with the heat more efficient conduction to fin 3 on the MOSFET chip 1, strengthen heat dispersion.

As a preferable scheme, a plurality of grooves 32 are uniformly formed on the top of the heat sink 3 to increase the heat dissipation area. For ease of manufacture, the groove 32 is configured as a concave rectangular groove. The groove 32 can increase the contact area between the heat sink 3 and the epoxy layer 4, so that the heat sink and the epoxy layer are connected more firmly and are less prone to being separated, and heat on the MOSFET chip 1 is more uniformly dispersed into the epoxy layer 4.

As a preferable scheme, semicircular transverse grooves 41 are uniformly formed at the top of the epoxy resin layer 4, and the transverse grooves 41 have the function of increasing the contact area between the epoxy resin layer 4 and the outside air, so as to improve the heat dissipation efficiency of the integrated circuit package.

The heat dissipation alloy 12 is arranged at the drain electrode at the bottom of the MOSFET chip 1, the heat dissipation alloy 12 is silver-lead-tin alloy with good heat dissipation performance and also has good electrical conductivity, and the components of the heat dissipation alloy in percentage by mass are 4.5-11% of tin, 0.8-2.215% of silver and the balance of lead. The heat dissipating alloy 12 can thus form an electrical connection with the MOSFET chip 1 and the lead frame 2, and can replace the soft solder layer.

In the implementation, the metal wire is connected with the bottom bonding pad in a bridging mode on the grid of the MOSFET chip 1, and the large-area bonding pad is plated at the bottom of the central base island 21 of the lead frame 2, so that the heat dissipation performance and the electric conductivity are improved. The source electrode of the MOSFET chip 1 can be electrically connected with the radiating fin 3 (copper sheet) on the upper surface of the chip through a soft solder layer, the radiating fin 3 is connected with the source electrode on the bottom bonding pad, the wire bonding process before change is adopted, the electric contact area is increased, and meanwhile, the radiating performance is greatly increased.

The above-mentioned embodiments further explain in detail the objects, technical solutions and advantages of the present invention, and it should be understood that the above-mentioned embodiments are only the embodiments of the present invention, and are not intended to limit the scope of the present invention, any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention should be included within the scope of the present invention.

Claims

1. The utility model provides a heat abstractor based on DFN encapsulation, includes MOSFET chip (1), electrically conductive base plate and epoxy layer (4), the upper surface of MOSFET chip (1) is equipped with source electrode and grid, and the lower surface is equipped with the drain electrode, electrically conductive base plate comprises heat dissipation area and lead frame (2), central island (21) of lead frame (2) combine with the lower surface of MOSFET chip (1), the heat dissipation area be located MOSFET chip (1) under and with MOSFET chip lower surface between be connected through soft solder layer electricity, epoxy layer (4) wrap whole MOSFET chip (1) and are fixed mutually with the top of lead frame (2), its characterized in that: the top of MOSFET chip (1) is equipped with fin (3), the bottom both sides of fin (3) are equipped with projection (31), the top both sides of MOSFET chip (1) are equipped with projection (31) assorted slot (11), the drain electrode department of MOSFET chip (1) bottom is provided with heat dissipation alloy (12).

2. The DFN package based heat dissipation device of claim 1, wherein: the radiating fin (3) is a copper sheet.

3. The DFN package based heat dissipation device of claim 2, wherein: the top of the radiating fin (3) is uniformly provided with a plurality of grooves (32).

4. The DFN package based heat dissipation device of claim 3, wherein: the groove (32) is an inwards concave rectangular groove.

5. The DFN package based heat dissipation device of claim 1, wherein: and semicircular transverse grooves (41) are uniformly formed in the top of the epoxy resin layer (4).

6. The DFN package based heat dissipation device of claim 1, wherein: the radiating fin (3) is attached to the MOSFET chip (1) through a heat conducting material.