CN212570968U - Heat dissipation embedding packaging structure - Google Patents
Heat dissipation embedding packaging structure Download PDFInfo
- Publication number
- CN212570968U CN212570968U CN202021171406.3U CN202021171406U CN212570968U CN 212570968 U CN212570968 U CN 212570968U CN 202021171406 U CN202021171406 U CN 202021171406U CN 212570968 U CN212570968 U CN 212570968U
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- Prior art keywords
- circuit layer
- layer
- hole
- copper
- heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The utility model discloses a heat dissipation inlays and buries packaging structure, include: the frame is provided with at least one through hole and a plurality of vertically arranged first copper columns, devices are arranged in the through hole, and photosensitive insulating materials are filled at the lower part of the through hole; the device is electrically connected with the first circuit layer; and part of the second circuit layer fills the upper part of the through hole and wraps the upper surface and at least part of the side surface of the device, and the first copper cylinder is electrically connected with the first circuit layer and the second circuit layer. The upper surface and at least part of part side of second circuit layer parcel device compare in original single face heat dissipation packaging structure, the utility model discloses increased the heat radiating area of device for the device can carry out diversified heat dissipation, thereby makes the radiating efficiency improve.
Description
Technical Field
The utility model relates to a semiconductor package field, in particular to packaging structure.
Background
With the rapid development of the electronic industry, the conventional electronic products are becoming thinner and lighter, and the integration level and functionality are increasing, so that the circuit boards for carrying electronic devices such as resistors, capacitors or chips are inevitably developed toward the direction of thinning, and thus the circuit board packaging technology is derived. Among them, the embedded package technology has been widely applied to power management products such as filters, power amplifiers, etc., and is more and more favored by people. The embedded packaging technology is a high-density packaging technology for embedding electronic devices into an embedded packaging substrate, can shorten the length of a circuit, improve the electrical characteristics and reduce welding points on the surface of a circuit board, thereby improving the reliability of packaging and reducing the cost. However, as electronic devices become more integrated, heat dissipation becomes one of the primary considerations in embedded package design.
The embedded packaging technology in the prior art adopts a single-side heat dissipation packaging mode, namely, through holes are formed on the back surface of an embedded packaging substrate in a laser drilling or plasma etching mode, and then the through holes are metalized to form heat-conducting copper columns, or large-area copper sheets are directly arranged on the back surface of the embedded packaging substrate.
SUMMERY OF THE UTILITY MODEL
The utility model discloses aim at solving one of the technical problem that exists among the prior art at least. Therefore, the utility model provides a heat dissipation inlays and buries packaging structure can improve the heat radiating area of device, reduction in production cost, shorten preparation cycle.
According to the utility model discloses heat dissipation buries packaging structure, include: the frame is provided with at least one through hole and a plurality of vertically arranged first copper columns, devices are arranged in the through hole, photosensitive insulating materials are filled at the lower part of the through hole, the lower surface of the frame is a first surface, and the upper surface of the frame is a second surface; the first circuit layer is arranged on the first surface, and the device is electrically connected with the first circuit layer; and part of the second circuit layer is filled in the upper part of the through hole and wraps the upper surface and at least part of the side surface of the device, the other part of the second circuit layer covers the upper end of the first copper column, and the first copper column is electrically connected with the first circuit layer and the second circuit layer.
The method has the following beneficial effects: the upper surface and at least part of part side of second circuit layer parcel device compare in original single face heat dissipation packaging structure, the utility model discloses increased the heat radiating area of device for the device can carry out diversified heat dissipation, thereby makes the radiating efficiency improve.
According to some embodiments of the present invention, further comprising: the third circuit layer is arranged below the first circuit layer, a first filling and sealing layer and a plurality of second copper columns are arranged between the first circuit layer and the third circuit layer, and the second copper columns penetrate through the first filling and sealing layer and are electrically connected with the first circuit layer and the third circuit layer; the fourth circuit layer, set up in second circuit layer top, the second circuit layer with be provided with the second between the fourth circuit layer and fill out sealing layer and a plurality of the second copper post, the second copper post runs through sealing layer and electric connection are filled out to the second circuit layer with the fourth circuit layer.
According to some embodiments of the invention, the first and second sealing layers are made of resin.
According to some embodiments of the present invention, the second circuit layer and the second surface are further filled with the photosensitive insulating material.
According to some embodiments of the utility model, the upper surface on first circuit layer is provided with first seed layer, the lower surface on second circuit layer is provided with the second seed layer.
According to some embodiments of the invention, the frame is made of resin.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic longitudinal cross-sectional view of one embodiment of the present invention;
fig. 2 is a schematic longitudinal cross-sectional view of another embodiment of the present invention.
Reference numerals: the semiconductor device comprises a frame 1, a first surface 11, a first seed layer 111, a second surface 12, a second seed layer 121, a through hole 13, a first copper pillar 14, a first circuit layer 15, a second circuit layer 16, a first sealing layer 17, a third circuit layer 171, a second sealing layer 18, a fourth circuit layer 181, a device 2 and a second copper pillar 3.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present invention, and should not be construed as limiting the present invention.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as the upper and lower directions, is the orientation or positional relationship shown on the drawings, and is only for convenience of description and simplification of description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore should not be construed as limiting the present invention.
In the description of the present invention, a plurality of means are one or more, and a plurality of means are two or more. If there is a description of the first, second, third and fourth only for the purpose of distinguishing between technical features, this is not to be understood as indicating or implying a relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present invention, unless there is an explicit limitation, words such as setting, connection, and fitting should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meaning of the above words in combination with the specific content of the technical solution.
Referring to fig. 1, the utility model discloses a heat dissipation embedding packaging structure, including frame 1, first circuit layer 15 and second circuit layer 16.
Wherein, frame 1 is provided with at least one through-hole 13 and a plurality of vertical first copper post 14 that sets up, be provided with device 2 in the through-hole 13, the lower part packing of through-hole 13 has photosensitive insulating material, the lower surface of frame 1 is first surface 11, the upper surface of frame 1 is second surface 12, first circuit layer 15 sets up in first surface 11, device 2 and first circuit layer 15 electric connection, part second circuit layer 16 fills the upper portion of through-hole 13 and wraps up device 2's upper surface and at least part side, another part second circuit layer 16 covers the upper end of first copper post 14, first copper post 14 electric connection first circuit layer 15 and second circuit layer 16.
It can be understood that the upper surface and at least part of the side of second circuit layer 16 parcel device 2 compare in original single face heat dissipation packaging structure, the utility model discloses increased device 2's heat radiating area for device 2 can carry out diversified heat dissipation, thereby makes the radiating efficiency improve.
Specifically, there may be one or more through holes 13 and first copper pillars 14, the through holes 13 are distributed on the frame 1, and the first copper pillars 14 are distributed on the frame 1. The device 2 may be a passive device such as a resistor, a capacitor, an inductor, or the like, or an active device such as a chip, and the device 2 may be a single device 2, or a combination of a plurality of devices 2 stacked back to back.
Referring to fig. 2, in some embodiments of the present invention, further comprising: a third circuit layer 171 and a fourth circuit layer 181.
The third circuit layer 171 is disposed below the first circuit layer 15, a first sealing layer 17 and a plurality of second copper pillars 3 are disposed between the first circuit layer 15 and the third circuit layer 171, the second copper pillars 3 penetrate through the first sealing layer 17 and are electrically connected to the first circuit layer 15 and the third circuit layer 171, the fourth circuit layer 181 is disposed above the second circuit layer 16, a second sealing layer 18 and a plurality of second copper pillars 3 are disposed between the second circuit layer 16 and the fourth circuit layer 181, and the second copper pillars 3 penetrate through the second sealing layer 18 and are electrically connected to the second circuit layer 16 and the fourth circuit layer 181. The first and second potting layers 17 and 18 are made of resin.
In some embodiments of the present invention, a photosensitive insulating material is further filled between the second circuit layer 16 and the second surface 12. The photosensitive insulating material is a substance which can be converted into a solid organic polymer product under the action of light or high-energy rays. The photosensitive insulating material is a stable solid organic polymer product which can be formed by crosslinking and polymerizing a small molecular unsaturated organic oligomer along with the effect of a specific catalyst under the action of light (ultraviolet light or visible light) or high-energy rays (mainly electron beams), and the product has good dielectric property (electric insulating property), a dielectric constant of 2.5-3.4, dielectric loss of 0.001-0.01, dielectric strength of 100 KV-400 KV, and surface resistance and bulk resistance of 10e17 omega. m, for example: PI polyimide, PPO polyoxyxylene, and the like.
Referring to fig. 1, in some embodiments of the present invention, the upper surface of the first circuit layer 15 is provided with a first seed layer 111, and the lower surface of the second circuit layer 16 is provided with a second seed layer 121. The first seed layer 111 and the second seed layer 121 may be made of metal, including but not limited to metal titanium, copper, titanium-tungsten alloy, and the like. The presence of the first seed layer 111 and the second seed layer 121 may enable the subsequent first metal layer and the second metal layer to better adhere to the respective areas when electroplating is performed.
In some embodiments of the present invention, the frame 1 is made of resin.
The utility model provides a heat dissipation embedding packaging structure preparation flow as follows: manufacturing a frame 1 with at least one through hole 13, wherein the frame 1 is also vertically provided with a plurality of first copper columns 14, and the lower surface of the frame 1 is a first surface 11; adhering an adhesive tape on the first surface 11, so that the adhesive surface of the adhesive tape is attached to the first surface 11, placing the device 2 in the through hole 13, and attaching the contact of the device 2 to the adhesive tape; curing the photosensitive insulating material in a part of the space of the through hole 13 to expose the upper surface of the device 2 and at least part of the side surface of the device 2; removing the adhesive tape, electroplating on the first surface 11 to form a first metal layer, electroplating on the upper surface and the side surface of the device 2, the upper surface of the photosensitive insulating material and the upper end surface of the first copper pillar 14 to form a second metal layer, and covering the upper end surface of the first copper pillar 14 and the upper surface and at least part of the side surface of the device 2 with the second metal layer; the first metal layer and the second metal layer are etched to obtain a first circuit layer 15 and a second circuit layer 16 respectively, the contact of the device 2 is electrically connected with the first circuit layer 15, and the upper end and the lower end of the first copper pillar 14 are electrically connected with the second circuit layer 16 and the first circuit layer 15 respectively.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.
Claims (6)
1. A heat dissipation embedded package structure, comprising:
the device comprises a frame (1) and a plurality of first copper columns (14) which are vertically arranged, wherein at least one through hole (13) and a plurality of first copper columns (14) are arranged in the frame (1), a device (2) is arranged in the through hole (13), a photosensitive insulating material is filled at the lower part of the through hole (13), the lower surface of the frame (1) is a first surface (11), and the upper surface of the frame (1) is a second surface (12);
a first circuit layer (15) arranged on the first surface (11), wherein the device (2) is electrically connected with the first circuit layer (15);
and a second circuit layer (16), wherein a part of the second circuit layer (16) fills the upper part of the through hole (13) and wraps the upper surface and at least a part of the side surface of the device (2), the other part of the second circuit layer (16) covers the upper end of the first copper pillar (14), and the first copper pillar (14) is electrically connected with the first circuit layer (15) and the second circuit layer (16).
2. The heat sink embedded package structure of claim 1, further comprising:
the third circuit layer (171) is arranged below the first circuit layer (15), a first filling and sealing layer (17) and a plurality of second copper columns (3) are arranged between the first circuit layer (15) and the third circuit layer (171), and the second copper columns (3) penetrate through the first filling and sealing layer (17) and are electrically connected with the first circuit layer (15) and the third circuit layer (171);
fourth circuit layer (181), set up in second circuit layer (16) top, second circuit layer (16) with be provided with second packing layer (18) and a plurality of between fourth circuit layer (181) second copper post (3), second copper post (3) run through second packing layer (18) and electric connection second circuit layer (16) with fourth circuit layer (181).
3. The heat sink embedded package structure according to claim 2, wherein the first sealing layer (17) and the second sealing layer (18) are made of resin.
4. The heat sink embedded package structure as claimed in claim 1, wherein the second circuit layer (16) and the second surface (12) are further filled with the photosensitive insulating material.
5. The heat dissipation embedded package structure as claimed in claim 1, wherein a first seed layer (111) is disposed on an upper surface of the first circuit layer (15), and a second seed layer (121) is disposed on a lower surface of the second circuit layer (16).
6. The heat dissipating embedded package structure according to claim 1, wherein the frame (1) is made of resin.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021171406.3U CN212570968U (en) | 2020-06-22 | 2020-06-22 | Heat dissipation embedding packaging structure |
| TW109211179U TWM608326U (en) | 2020-06-22 | 2020-08-27 | Heat-dissipation embedded packaging structure |
| JP2020003910U JP3229456U (en) | 2020-06-22 | 2020-09-11 | Heat dissipation embedded package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021171406.3U CN212570968U (en) | 2020-06-22 | 2020-06-22 | Heat dissipation embedding packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212570968U true CN212570968U (en) | 2021-02-19 |
Family
ID=73646642
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021171406.3U Active CN212570968U (en) | 2020-06-22 | 2020-06-22 | Heat dissipation embedding packaging structure |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP3229456U (en) |
| CN (1) | CN212570968U (en) |
| TW (1) | TWM608326U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113451259A (en) * | 2021-05-14 | 2021-09-28 | 珠海越亚半导体股份有限公司 | Multi-device multi-time embedded packaging substrate and manufacturing method thereof |
-
2020
- 2020-06-22 CN CN202021171406.3U patent/CN212570968U/en active Active
- 2020-08-27 TW TW109211179U patent/TWM608326U/en unknown
- 2020-09-11 JP JP2020003910U patent/JP3229456U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113451259A (en) * | 2021-05-14 | 2021-09-28 | 珠海越亚半导体股份有限公司 | Multi-device multi-time embedded packaging substrate and manufacturing method thereof |
| CN113451259B (en) * | 2021-05-14 | 2023-04-25 | 珠海越亚半导体股份有限公司 | Multi-device fractional embedded packaging substrate and manufacturing method thereof |
| TWI823387B (en) * | 2021-05-14 | 2023-11-21 | 大陸商珠海越亞半導體股份有限公司 | A multi-device graded embedded packaging substrate and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| TWM608326U (en) | 2021-03-01 |
| JP3229456U (en) | 2020-12-10 |
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