KR20070087765A - Stack type package and manufacture method thereof - Google Patents

Stack type package and manufacture method thereof Download PDF

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Publication number
KR20070087765A
KR20070087765A KR1020050105452A KR20050105452A KR20070087765A KR 20070087765 A KR20070087765 A KR 20070087765A KR 1020050105452 A KR1020050105452 A KR 1020050105452A KR 20050105452 A KR20050105452 A KR 20050105452A KR 20070087765 A KR20070087765 A KR 20070087765A
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South Korea
Prior art keywords
package
chip
substrate
wire
solder
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KR1020050105452A
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Korean (ko)
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KR100772103B1 (en
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서민석
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주식회사 하이닉스반도체
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Priority to KR1020050105452A priority Critical patent/KR100772103B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A stacked package and its manufacture method are provided to install easily a new chip and to enhance a yield by removing only a bad chip from a plurality of chips. A substrate(110) includes a bonding pad(111) positioned on both ends of one side thereof. A chip(120) is mounted on one side of the substrate and is electrically connected with the bonding pad by using a wire(130). A metal post(113) is formed on both ends of the other side of the substrate. A solder cap(114) is coated on an end of the metal post. An EMC is used for sealing up the chip and the wire. An upper package has the same structure as a structure of a lower package. The upper package is formed by soldering and stacking the solder cap on the bonding pad of the lower package.

Description

적층형 패키지 및 그 제조 방법{Stack type package and manufacture method thereof}Stacked package and method for manufacturing same

도 1a 및 도 1b는 종래의 적층형 패키지를 나타낸 단면도,1a and 1b is a cross-sectional view showing a conventional stacked package,

도 2는 본 발명이 일 실시에에 따른 적층형 패키지를 나타낸 단면도,2 is a cross-sectional view showing a stacked package according to an embodiment of the present invention;

도 3a 내지 도 3f는 도 2의 적층형 패키지 제조방법을 순차적으로 나타낸 단면도.3A to 3F are cross-sectional views sequentially illustrating the method of manufacturing the stacked package of FIG. 2.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

110... 기판 111... 본딩 패드110 ... substrate 111 ... bonding pad

113... 메탈 포스트 114... 솔더 캡113 ... metal post 114 ... solder cap

120... 칩 130... 와이어120 ... chip 130 ... wire

본 발명은 적층형 패키지 및 그 제조방법에 관한 것으로서, 특히 다수의 패키지를 적층하여 높은 공정 수율과 실장 밀도 및 고속 동작이 가능한 적층형 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated package and a method of manufacturing the same, and more particularly, to a laminated package and a method of manufacturing the same, which can produce a high process yield, mounting density, and high-speed operation by stacking a plurality of packages.

최근 모바일 제품 및 고성능 전자 기기에서는 실장 효율이 높고, 고성능의 디바이스가 요구된다.Recently, mobile products and high-performance electronic devices require high mounting efficiency and high-performance devices.

그러나, 칩의 성능 및 밀도 개선은 팹 공정 및 소자 설계의 난이도 때문에 시장의 요구에 효과적으로 대응하기 어렵다.However, chip performance and density improvements are difficult to respond effectively to market demands due to the difficulty of fab processes and device design.

이를 해결하기 위해 대두되는 것 중 하나가 SIP(system in package)로써, 하나의 패키지 내에 다수의 칩을 적층하는 칩 적층 패키지와 단품의 패키지를 다수개 적층함으로써 높은 실장 밀도를 구현하는 패키지 적층이 있다.In order to solve this problem, a system in package (SIP) is a chip stack package for stacking a plurality of chips in one package and a package stack for implementing a high mounting density by stacking a plurality of single packages. .

그런데, 도 1a와 같은 칩 적층 패키지(10)의 경우에는 내부에 적층된 다수의 칩(11) 중 어느 하나라도 불량이 발생하면 패키지 전체를 사용하지 못하게 되어, 전체적인 공정 수율이 낮아지게 되며, 따라서 제작 단가가 높아지는 문제점이 있다.However, in the case of the chip stack package 10 as shown in FIG. 1A, when any one of the plurality of chips 11 stacked therein is defective, the entire package cannot be used, thereby lowering the overall process yield. There is a problem that the production cost increases.

그리고 도 1b와 같은 패키지 적층(20)의 경우에는 핀(21)에 의한 기판(22)과 별도의 수직 연결이 필요하여 공정이 복잡해지는 문제점이 있다.In addition, in the case of the package stack 20 as illustrated in FIG. 1B, a separate vertical connection with the substrate 22 by the pins 21 is required, which causes a complicated process.

본 발명은 상기의 문제점을 해결하기 위하여 창출된 것으로서, 공정 수율을 향상시키고, 공정을 단순화시킬 수 있도록 적층형 패키지 및 그 제조방법을 제공하는 것을 그 목적으로 한다.The present invention has been made to solve the above problems, and an object thereof is to provide a laminated package and a method of manufacturing the same so as to improve process yield and simplify the process.

상기의 목적을 달성하기 위한 본 발명의 적층형 패키지는, 일면 양측단부에 본딩 패드가 마련된 기판과, 상기 기판 일면에 실장되며, 와이어에 의하여 상기 본딩 패드와 전기적으로 연결된 칩과, 상기 기판 타면 양측단부에 마련된 메탈 포스 트와, 상기 메탈 포스트 단부에 도포된 솔더 캡 및 상기 칩과 상기 와이어를 밀봉하는 EMC를 포함한 하부 패키지; 및 상기 하부 패키지와 동일한 구조로, 상기 하부 패키지의 본딩 패드에 솔더 캡이 솔더링 적층된 상부 패키지를 포함한 것이 바람직하다.The laminated package of the present invention for achieving the above object is a substrate provided with bonding pads at both ends of one surface, a chip mounted on one surface of the substrate and electrically connected to the bonding pads by a wire, and both ends of the other surface of the substrate. A lower package including a metal post provided in the lower portion, a solder cap applied to the metal post end, and an EMC sealing the chip and the wire; And the upper package having the same structure as the lower package, in which a solder cap is soldered and laminated on the bonding pad of the lower package.

그리고 본 발명의 적층형 패키지 제조 방법은, 일면 양측단부에 본딩 패드가 마련되고, 타면에 배선이 배치된 기판을 마련하는 단계; 상기 기판 양측단부의 배선 상에 다수의 메탈 포스트를 마련하는 단계; 상기 메탈 포스트의 단부에 솔더 캡을 마련하는 단계; 상기 배선을 덮도록 상기 배선 상에 솔더 레지스트를 도포하는 단계; 상기 기판 일면에 칩을 실장하고, 와이어에 의하여 상기 본딩 패드와 상기 칩을 전기적으로 연결하고, 상기 칩과 상기 와이어를 밀봉하여 단품 패키지를 마련하는 단계; 상기의 단계를 반복하여 다수의 단품 패키지를 마련한 후, 상기 단품 패키지의 본딩 패드 상에 상기 다른 단품 패키지의 솔더 캡이 접촉되도록 적층하는 단계; 및 상기 솔더 캡과 상기 본딩 패드 사이에 솔더링 되도록 리플로우하는 단계를 포함한 것이 바람직하다.In addition, the method of manufacturing a stacked package of the present invention may include: providing a substrate on which bonding pads are provided at both ends of one surface and wires are disposed on the other surface; Providing a plurality of metal posts on wirings at both ends of the substrate; Providing a solder cap at an end of the metal post; Applying a solder resist on the wiring to cover the wiring; Mounting a chip on one surface of the substrate, electrically connecting the bonding pad and the chip by a wire, and sealing the chip and the wire to prepare a single package; Repeating the above steps to prepare a plurality of unit packages, and stacking the solder caps of the other unit packages on the bonding pads of the unit packages; And reflowing to be soldered between the solder cap and the bonding pad.

여기서, 상기 메탈 포스트는 도금 및 스터드 방식 중 어느 한 방식에 의하여 마련된것이 바람직하다.Here, the metal post is preferably provided by any one of the plating and stud method.

이하 첨부된 도면을 참조하면서 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명의 일 실시예에 따른 적층형 패키지를 나타낸 단면도이다.2 is a cross-sectional view showing a stacked package according to an embodiment of the present invention.

도면을 참조하면, 적층형 패키지(100)는 동일한 형태의 패키지 다수가 적층 된 패키지로써, 본 발명에서는 하부 패키지(100a) 상에 상부 패키지(100b)가 적층된 형태에 대하여 설명하기로 한다.Referring to the drawings, the stacked package 100 is a package in which a plurality of packages of the same type are stacked. In the present invention, a form in which the upper package 100b is stacked on the lower package 100a will be described.

하부 패키지(100a)는 기판(110)과, 이 기판(110) 일면에 실장되는 칩(120)과, 기판(110)과 칩(120)을 전기적으로 연결하는 와이어(130) 및 칩(120)과 와이어(130)를 밀봉하는 EMC(140)를 포함한다.The lower package 100a includes a substrate 110, a chip 120 mounted on one surface of the substrate 110, a wire 130 and a chip 120 electrically connecting the substrate 110 and the chip 120. And EMC 140 for sealing wire 130.

기판(110) 일면 양측단부에는 다수의 본딩 패드(111)가 마련되며, 이 본딩 패드(111) 중 어느 하나에 와이어(130)가 연결되어 칩(120)과 기판(110) 간을 전기적으로 연결되도록 한다.A plurality of bonding pads 111 are provided at both ends of one surface of the substrate 110, and a wire 130 is connected to any one of the bonding pads 111 to electrically connect the chip 120 and the substrate 110. Be sure to

그리고 기판(110) 타면 양측단부에는 다수의 메탈 포스트(113)가 마련되며, 이 메탈 포스트(113)의 단부에는 솔더 캡(113)이 마련된다.A plurality of metal posts 113 are provided at opposite ends of the other surface of the substrate 110, and solder caps 113 are provided at the ends of the metal posts 113.

이 하부 패키지(100a) 상에, 이 하부 패키지(100a)와 동일한 구조의 상부 패키지(100b)가 적층되어 본 발명의 적층형 패키지(100)를 만드는데, 그 적층 구조를 설명하면 다음과 같다.On the lower package 100a, the upper package 100b having the same structure as the lower package 100a is stacked to form the stacked package 100 of the present invention. The lamination structure will be described below.

즉, 상부 패키지(100b)의 메탈 포스트(113')가 하부 패키지(100a)의 본딩 패드(111) 상에 올려져, 상부 패키지(100b)의 메탈 포스트(113') 단부에 마련된 솔더 캡(114')과 하부 패키지(100a)의 본딩 패드(111)가 솔더링되어 수직 신호 전달 경로를 형성하게 된다.That is, the metal post 113 'of the upper package 100b is mounted on the bonding pad 111 of the lower package 100a, and the solder cap 114 provided at the end of the metal post 113' of the upper package 100b. ') And the bonding pads 111 of the lower package 100a are soldered to form a vertical signal transmission path.

이와 같은 적층형 패키지는 도 3a 내지 도 3f와 같이 순차적으로 제조된다.Such stacked packages are sequentially manufactured as shown in FIGS. 3A to 3F.

도면을 참조하면, 적층형 패키지 제조 방법은, 먼저 일면 양측단부에 다수의 본딩 패드(111)가 마련되고, 타면에 배선(112)이 배치된 기판(110)을 마련한다.Referring to the drawings, in the method of manufacturing a stacked package, first, a plurality of bonding pads 111 are provided at both ends of one surface, and a substrate 110 having wiring 112 disposed on the other surface thereof.

그리고 기판(110) 양측단부의 배선(112) 상에 금 등의 전기전도성 물질로 된 다수의 메탈 포스트(113)를 마련한다. 여기서, 메탈 포스트(113)는 도금 방식이나 스터드 방식에 의하여 마련할 수 있다.A plurality of metal posts 113 made of an electrically conductive material such as gold is provided on the wiring 112 at both ends of the substrate 110. Here, the metal post 113 can be provided by a plating method or a stud method.

다음으로, 메탈 포스트(113) 단부에 솔더 캡(114)을 마련하고, 배선(112)을 덮도록 배선(112) 상에 솔더 레지스트(115)를 도포한다.Next, a solder cap 114 is provided at an end portion of the metal post 113, and a solder resist 115 is coated on the wiring 112 to cover the wiring 112.

그리고 기판(110) 일면에 칩(120)을 실장하고, 와이어(130)에 의하여 다수의 본딩 패드(111) 중 어느 하나와 전기적으로 연결하고, 칩(120)과 와이어(130) 등을 외부로부터 보호하기 위하여 EMC(140)로 밀봉함으로써 단품 패키지(100a)를 마련한다.The chip 120 is mounted on one surface of the substrate 110, electrically connected to any one of the plurality of bonding pads 111 by the wire 130, and the chip 120 and the wire 130 are connected from the outside. In order to protect, the one piece package 100a is prepared by sealing with EMC 140.

이와 같은 과정을 반복하여 다수의 단품 패키지를 마련한 후, 적층형 패키지(100)를 제조하기 위하여, 단품 패키지(100a)의 본딩 패드(111) 상에, 또 다른 단품 패키지(100b)의 메탈 포스트(113')를 올려 본딩 패드(111)와 메탈 포스트(113') 단부에 마련된 솔더 캡(114')이 접촉하도록 한 후, 리플로우에 의하여 본딩 패드(111)와 솔더 캡(114')을 솔더링함으로써, 적층형 패키지(100)를 완성한다.After repeating the above process to prepare a plurality of single-piece package, in order to manufacture the stacked package 100, on the bonding pad 111 of the single-piece package 100a, the metal post 113 of another single-package 100b. ') To raise the bonding pads 111 and the solder caps 114' provided at the ends of the metal posts 113 ', and then solder the bonding pads 111 and the solder caps 114' by reflow. The stacked package 100 is completed.

이와 같은 구조 및 방법에 의하면, 다수의 칩 중 불량이 발생한 칩이 있을 경우, 그 칩만을 제거하고, 다시 새로운 칩으로 재작업을 용이하게 할 수 있고, 또한 미세한 피치의 컬럼 형태의 메탈 포스트를 통해 적층된 패키지 간 수직 연결을 하기 때문에 패키지의 크기를 더 줄일 수 있어 실장 효율이 더욱 향상된다.According to such a structure and method, when there is a chip having a defect among a plurality of chips, only the chip can be removed, and reworking with a new chip can be easily performed, and through a fine pitch column type metal post The vertical connection between stacked packages further reduces the package size, further improving mounting efficiency.

미설명 부호 121은 칩 패드이다.Reference numeral 121 is a chip pad.

상술한 바와 같이 본 발명의 적층형 패키지 및 그 제조방법에 의하면, 다수의 칩 중 불량이 발생한 칩이 있을 경우, 그 칩만을 제거하고, 다시 새로운 칩으로 재작업을 용이하게 할 수 있고, 또한 미세한 피치의 컬럼 형태의 메탈 포스트를 통해 적층된 패키지 간 수직 연결을 하기 때문에 패키지의 크기를 더 줄일 수 있어 실장 효율을 향상시키는 효과를 제공한다.As described above, according to the stacked package of the present invention and a manufacturing method thereof, when there is a chip having a defect among a plurality of chips, only the chip can be removed, and reworking with a new chip can be easily performed, and a fine pitch can be obtained. The vertical connection between the stacked packages through column-shaped metal posts reduces the size of the package, thereby improving the mounting efficiency.

본 발명은 상기에 설명되고 도면에 예시된 것에 의해 한정되는 것은 아니며, 다음에 기재되는 청구의 범위 내에서 더 많은 변형 및 변용예가 가능한 것임은 물론이다.It is to be understood that the invention is not limited to that described above and illustrated in the drawings, and that more modifications and variations are possible within the scope of the following claims.

Claims (3)

일면 양측단부에 본딩 패드가 마련된 기판과, 상기 기판 일면에 실장되며, 와이어에 의하여 상기 본딩 패드와 전기적으로 연결된 칩과, 상기 기판 타면 양측단부에 마련된 메탈 포스트와, 상기 메탈 포스트 단부에 도포된 솔더 캡 및 상기 칩과 상기 와이어를 밀봉하는 EMC를 포함한 하부 패키지; 및A substrate provided with bonding pads at both ends of one surface, a chip mounted on one surface of the substrate and electrically connected to the bonding pads by a wire, metal posts provided at both ends of the other surface of the substrate, and solder applied to the metal post ends A bottom package including a cap and an EMC sealing said chip and said wire; And 상기 하부 패키지와 동일한 구조로, 상기 하부 패키지의 본딩 패드에 솔더 캡이 솔더링 적층된 상부 패키지를 포함한 것을 특징으로 하는 적층형 패키지.Stacked package, characterized in that the same as the lower package, the upper package having a solder cap soldered on the bonding pad of the lower package. 일면 양측단부에 본딩 패드가 마련되고, 타면에 배선이 배치된 기판을 마련하는 단계;Providing a substrate on which bonding pads are provided at both ends of one surface and wires are disposed on the other surface; 상기 기판 양측단부의 배선 상에 다수의 메탈 포스트를 마련하는 단계;Providing a plurality of metal posts on wirings at both ends of the substrate; 상기 메탈 포스트의 단부에 솔더 캡을 마련하는 단계;Providing a solder cap at an end of the metal post; 상기 배선을 덮도록 상기 배선 상에 솔더 레지스트를 도포하는 단계;Applying a solder resist on the wiring to cover the wiring; 상기 기판 일면에 칩을 실장하고, 와이어에 의하여 상기 본딩 패드와 상기 칩을 전기적으로 연결하고, 상기 칩과 상기 와이어를 밀봉하여 단품 패키지를 마련하는 단계;Mounting a chip on one surface of the substrate, electrically connecting the bonding pad and the chip by a wire, and sealing the chip and the wire to prepare a single package; 상기의 단계를 반복하여 다수의 단품 패키지를 마련한 후, 상기 단품 패키지의 본딩 패드 상에 상기 다른 단품 패키지의 솔더 캡이 접촉되도록 적층하는 단계; 및 Repeating the above steps to prepare a plurality of unit packages, and stacking the solder caps of the other unit packages on the bonding pads of the unit packages; And 상기 솔더 캡과 상기 본딩 패드 사이에 솔더링 되도록 리플로우하는 단계를 포함한 것을 특징으로 하는 적층형 패키지 제조 방법.And reflowing the solder cap between the solder cap and the bonding pad. 제2항에 있어서,The method of claim 2, 상기 메탈 포스트는 도금 및 스터드 방식 중 어느 한 방식에 의하여 마련된것을 특징으로 하는 적층형 패키지 제조 방법.The metal post is a laminated package manufacturing method, characterized in that provided by any one of the plating and stud method.
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