TW201633494A - Package on package and manufacturing method thereof - Google Patents
Package on package and manufacturing method thereof Download PDFInfo
- Publication number
- TW201633494A TW201633494A TW104106831A TW104106831A TW201633494A TW 201633494 A TW201633494 A TW 201633494A TW 104106831 A TW104106831 A TW 104106831A TW 104106831 A TW104106831 A TW 104106831A TW 201633494 A TW201633494 A TW 201633494A
- Authority
- TW
- Taiwan
- Prior art keywords
- substrate
- wafer
- disposed
- semiconductor component
- encapsulant
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Wire Bonding (AREA)
Abstract
Description
本發明是有關於一種半導體封裝及其製造方法，且特別是有關於一種堆疊式半導體封裝及其製造方法。 The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a stacked semiconductor package and a method of fabricating the same.
隨著電子裝置的尺寸減小，近來，已發展堆疊型半導體封裝(Package on Package，POP)的技術，藉由堆疊多個晶片或在單個半導體封裝中堆疊個別半導體封裝而實現高積集密度。 As the size of electronic devices has decreased, recently, a technology of stacked-on-package (POP) has been developed to achieve high accumulation density by stacking a plurality of wafers or stacking individual semiconductor packages in a single semiconductor package.
圖1至圖3是習知的一種堆疊式封裝的製造流程的示意圖。請先參閱圖1，首先提供一第一半導體元件11。如圖1所示，第一半導體元件11包括一第一基底12、一第一晶片13、多個焊球14及一第一封裝膠體15。第一晶片13與這些焊球14(圖1上示意性地繪示出兩個)配置在第一基底12上，且焊球14環繞著第一晶片13。第一封裝膠體15配置於第一基底12上且包封第一晶片13與這些焊球14。 1 to 3 are schematic views of a manufacturing process of a conventional stacked package. Referring first to FIG. 1, a first semiconductor component 11 is first provided. As shown in FIG. 1 , the first semiconductor device 11 includes a first substrate 12 , a first wafer 13 , a plurality of solder balls 14 , and a first encapsulant 15 . The first wafer 13 and the solder balls 14 (two are schematically shown on FIG. 1) are disposed on the first substrate 12, and the solder balls 14 surround the first wafer 13. The first encapsulant 15 is disposed on the first substrate 12 and encloses the first wafer 13 and the solder balls 14.
接著，如圖2所示，移除部分的第一封裝膠體15，而製造出開孔15a，以使這些焊球14外露，其中移除第一封裝膠體15 的方式例如是透過雷射鑽孔等方式。 Next, as shown in FIG. 2, a portion of the first encapsulant 15 is removed, and an opening 15a is formed to expose the solder balls 14, wherein the first encapsulant 15 is removed. The way is, for example, by laser drilling or the like.
再來，如圖3所示，將一第二半導體元件16配置在第一半導體元件11上。詳細地說，第二半導體元件16包括一第二基底17、一第二晶片18、一第二封裝膠體19及用以連接第一半導體元件11的多個焊球20。為了避免多餘的線條，圖式上特意省略第一基底12與第二基底17的線路層。 Further, as shown in FIG. 3, a second semiconductor element 16 is disposed on the first semiconductor element 11. In detail, the second semiconductor component 16 includes a second substrate 17 , a second wafer 18 , a second encapsulant 19 , and a plurality of solder balls 20 for connecting the first semiconductor component 11 . In order to avoid unnecessary lines, the wiring layers of the first substrate 12 and the second substrate 17 are intentionally omitted in the drawing.
第二晶片18與第二封裝膠體19配置在第二基底17的其中一面(圖面上的上表面)上，且這些焊球20配置於第二基底17的另一面(圖面上的下表面)上。第二半導體元件16疊置於第一半導體元件11上，且第二半導體元件16的焊球20伸入第一半導體元件11的開孔15a，以連接到第一半導體元件11的焊球14，而完成了堆疊式封裝10。然而，上述的堆疊式封裝10在製造的步驟上仍較為繁瑣。 The second wafer 18 and the second encapsulant 19 are disposed on one surface (upper surface on the surface) of the second substrate 17, and the solder balls 20 are disposed on the other surface of the second substrate 17 (the lower surface on the surface) )on. The second semiconductor component 16 is stacked on the first semiconductor component 11, and the solder ball 20 of the second semiconductor component 16 extends into the opening 15a of the first semiconductor component 11 to be connected to the solder ball 14 of the first semiconductor component 11, The stacked package 10 is completed. However, the stacked package 10 described above is still cumbersome in the manufacturing steps.
本發明提供一種堆疊式封裝，其呈現一種新的堆疊式封裝結構。 The present invention provides a stacked package that presents a new stacked package structure.
本發明提供一種堆疊式封裝的製造方法，其具有較簡化的步驟。 The present invention provides a method of fabricating a stacked package having relatively simplified steps.
本發明的一種堆疊式封裝，包括一第一半導體元件及疊置於第一半導體元件的一第二半導體元件。第一半導體元件包括一第一基底、一第一晶片、多個導電柱及一第一封裝膠體。第一 基底包括相對的一第一表面與一第二表面。第一晶片配置於第一基底的第一表面。導電柱配置於第一基底的第一表面。第一封裝膠體配置於第一基底的第一表面上以覆蓋第一晶片與各導電柱的一第一部分。各導電柱的一第二部分凸出或齊平於第一封裝膠體。第二半導體元件包括一第二基底、一第二晶片、一第二封裝膠體及多個第二焊球。第二基底包括相對的一第三表面與一第四表面。第二晶片配置於第二基底的第三表面。第二封裝膠體配置於第二基底的第三表面上以覆蓋第二晶片。第二焊球配置於第二基底的第四表面，其中第二半導體元件的第二焊球連接至第一半導體元件的導電柱的第二部分。 A stacked package of the present invention includes a first semiconductor component and a second semiconductor component stacked on the first semiconductor component. The first semiconductor component includes a first substrate, a first wafer, a plurality of conductive pillars, and a first encapsulant. the first The substrate includes a first surface and a second surface opposite to each other. The first wafer is disposed on the first surface of the first substrate. The conductive pillar is disposed on the first surface of the first substrate. The first encapsulant is disposed on the first surface of the first substrate to cover the first wafer and a first portion of each of the conductive pillars. A second portion of each of the conductive posts is convex or flush with the first encapsulant. The second semiconductor component includes a second substrate, a second wafer, a second encapsulant, and a plurality of second solder balls. The second substrate includes an opposite third surface and a fourth surface. The second wafer is disposed on the third surface of the second substrate. The second encapsulant is disposed on the third surface of the second substrate to cover the second wafer. The second solder ball is disposed on the fourth surface of the second substrate, wherein the second solder ball of the second semiconductor component is coupled to the second portion of the conductive pillar of the first semiconductor component.
在本發明的一實施例中，上述的第一半導體元件更包括多個第一焊球，配置於第一基底的第二表面。 In an embodiment of the invention, the first semiconductor component further includes a plurality of first solder balls disposed on the second surface of the first substrate.
在本發明的一實施例中，上述的第一晶片與第二晶片分別以打線或是球柵陣列的方式電性連接至第一基底與第二基底。 In an embodiment of the invention, the first wafer and the second wafer are electrically connected to the first substrate and the second substrate by wire bonding or a ball grid array, respectively.
在本發明的一實施例中，上述的這些導電柱在第一表面上以環繞第一晶片的方式配置。 In an embodiment of the invention, the conductive pillars are disposed on the first surface in a manner surrounding the first wafer.
在本發明的一實施例中，上述的各導電柱為一銅柱。 In an embodiment of the invention, each of the conductive pillars is a copper pillar.
一種堆疊式封裝的製造方法，包括下列步驟：首先，提供一第一半導體元件，其中第一半導體元件包括一第一基底與一第一晶片，第一基底包括相對的一第一表面與一第二表面，且第一晶片配置於第一基底的第一表面。接著，配置多個導電柱於第一基底的第一表面上。再來，形成一第一封裝膠體於第一基底的 第一表面上以覆蓋第一晶片與各導電柱的一第一部分，其中各導電柱的一第二部分凸出或齊平於第一封裝膠體。最後，連接一第二半導體元件至第一半導體元件，其中第二半導體元件包括一第二基底、一第二晶片、一第二封裝膠體及多個第二焊球。第二基底包括相對的一第三表面與一第四表面，第二晶片配置於第二基底的第三表面，第二封裝膠體配置於第二基底的第三表面上以覆蓋第二晶片，這些第二焊球配置於第二基底的第四表面，其中第二半導體元件的第二焊球連接至第一半導體元件的導電柱的第二部分。 A method of manufacturing a stacked package, comprising the steps of: firstly providing a first semiconductor component, wherein the first semiconductor component comprises a first substrate and a first wafer, the first substrate comprises an opposite first surface and a first Two surfaces, and the first wafer is disposed on the first surface of the first substrate. Next, a plurality of conductive pillars are disposed on the first surface of the first substrate. Then, forming a first encapsulant on the first substrate The first surface covers a first portion of the first wafer and each of the conductive pillars, wherein a second portion of each of the conductive pillars is convex or flush with the first encapsulant. Finally, a second semiconductor component is connected to the first semiconductor component, wherein the second semiconductor component comprises a second substrate, a second wafer, a second encapsulant and a plurality of second solder balls. The second substrate includes an opposite third surface and a fourth surface, the second wafer is disposed on the third surface of the second substrate, and the second encapsulant is disposed on the third surface of the second substrate to cover the second wafer. The second solder ball is disposed on the fourth surface of the second substrate, wherein the second solder ball of the second semiconductor component is coupled to the second portion of the conductive pillar of the first semiconductor component.
在本發明的一實施例中，上述的第一半導體元件更包括多個第一焊球，配置於第一基底的第二表面。 In an embodiment of the invention, the first semiconductor component further includes a plurality of first solder balls disposed on the second surface of the first substrate.
在本發明的一實施例中，上述的第一晶片與第二晶片分別以打線或是球柵陣列的方式電性連接至第一基底與第二基底。 In an embodiment of the invention, the first wafer and the second wafer are electrically connected to the first substrate and the second substrate by wire bonding or a ball grid array, respectively.
在本發明的一實施例中，上述的這些導電柱在第一表面上以環繞第一晶片的方式配置。 In an embodiment of the invention, the conductive pillars are disposed on the first surface in a manner surrounding the first wafer.
在本發明的一實施例中，上述的各導電柱為一銅柱。 In an embodiment of the invention, each of the conductive pillars is a copper pillar.
基於上述，相較於習知的堆疊式封裝需要透過在第一半導體元件的第一基底上預先配置用以連接第二半導體元件的焊球，並且還需透過雷射鑽孔等方式移除局部的第一封裝膠體而使焊球外露。本發明的堆疊式封裝的製造方法透過在第一基底上配置多個導電柱，且各導電柱的第二部分凸出或齊平於第一封裝膠體，以使第二半導體元件的第二焊球能夠直接與第一半導體元件 的導電柱連接而完成堆疊式封裝的結構。因此，本發明的堆疊式封裝的製造方法能夠省去在第一基底上配置用以連接第二半導體元件的焊球，以及移除局部的第一封裝膠體的步驟。並且，本發明也提供了一種新結構的堆疊式封裝。 Based on the above, compared to the conventional stacked package, it is necessary to pre-configure the solder ball for connecting the second semiconductor element on the first substrate of the first semiconductor element, and also to remove the local portion by laser drilling or the like. The first encapsulant colloids to expose the solder balls. The method for manufacturing a stacked package of the present invention is characterized in that a plurality of conductive pillars are disposed on a first substrate, and a second portion of each conductive pillar is convex or flush with the first encapsulant to enable second soldering of the second semiconductor component. The ball can be directly connected to the first semiconductor component The conductive pillars are connected to complete the structure of the stacked package. Therefore, the manufacturing method of the stacked package of the present invention can omit the step of disposing a solder ball for connecting the second semiconductor element on the first substrate, and removing the partial first encapsulant. Moreover, the present invention also provides a stacked package of a new structure.
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 The above described features and advantages of the invention will be apparent from the following description.
10‧‧‧習知的堆疊式封裝 10‧‧‧Scheduled stacked packages
11‧‧‧第一半導體元件 11‧‧‧First semiconductor component
12‧‧‧第一基底 12‧‧‧First substrate
13‧‧‧第一晶片 13‧‧‧First chip
14‧‧‧焊球 14‧‧‧ solder balls
15‧‧‧第一封裝膠體 15‧‧‧First encapsulant
15a‧‧‧開孔 15a‧‧‧Opening
16‧‧‧第二半導體元件 16‧‧‧Second semiconductor component
17‧‧‧第二基底 17‧‧‧Second substrate
18‧‧‧第二晶片 18‧‧‧second chip
19‧‧‧第二封裝膠體 19‧‧‧Second encapsulant
20‧‧‧焊球 20‧‧‧ solder balls
100‧‧‧堆疊式封裝 100‧‧‧Stacked package
110‧‧‧第一半導體元件 110‧‧‧First semiconductor component
112‧‧‧第一基底 112‧‧‧First base
112a‧‧‧第一表面 112a‧‧‧ first surface
112b‧‧‧第二表面 112b‧‧‧ second surface
114‧‧‧第一晶片 114‧‧‧First chip
116‧‧‧導電柱 116‧‧‧conductive column
116a‧‧‧第一部分 116a‧‧‧Part 1
116b‧‧‧第二部分 116b‧‧‧Part II
118‧‧‧第一封裝膠體 118‧‧‧First encapsulant
119‧‧‧第一焊球 119‧‧‧First solder ball
120‧‧‧第二半導體元件 120‧‧‧Second semiconductor component
122‧‧‧第二基底 122‧‧‧Second substrate
122a‧‧‧第三表面 122a‧‧‧ third surface
122b‧‧‧第四表面 122b‧‧‧Fourth surface
124‧‧‧第二晶片 124‧‧‧second chip
126‧‧‧第二封裝膠體 126‧‧‧Second encapsulant
128‧‧‧第二焊球 128‧‧‧second solder ball
200‧‧‧堆疊式封裝的製造方法 200‧‧‧Manufacturing method of stacked package
210~240‧‧‧步驟 210~240‧‧‧Steps
圖1至圖3是習知的一種堆疊式封裝的製造流程的示意圖。 1 to 3 are schematic views of a manufacturing process of a conventional stacked package.
圖4至圖6是製造依照本發明的一實施例的一種堆疊式封裝的示意圖。 4 through 6 are schematic views of fabricating a stacked package in accordance with an embodiment of the present invention.
圖7是依照本發明的一實施例的一種堆疊式封裝的製造方法的流程圖。 7 is a flow chart of a method of fabricating a stacked package in accordance with an embodiment of the present invention.
圖4至圖6是製造依照本發明的一實施例的一種堆疊式封裝的示意圖。圖7是依照本發明的一實施例的一種堆疊式封裝的製造方法的流程圖。 4 through 6 are schematic views of fabricating a stacked package in accordance with an embodiment of the present invention. 7 is a flow chart of a method of fabricating a stacked package in accordance with an embodiment of the present invention.
請先參考圖4與圖7，本實施例的堆疊式封裝的製造方法200，包括下列步驟：首先，提供一第一半導體元件110，其中第一半導體元件110包括一第一基底112與一第一晶片114，第一基 底112包括相對的一第一表面112a與一第二表面112b，且第一晶片114配置於第一基底112的第一表面112a(步驟210)。並且，配置多個導電柱116於第一基底112的第一表面112a上(步驟220)。 Referring to FIG. 4 and FIG. 7 , the manufacturing method 200 of the stacked package of the present embodiment includes the following steps: First, a first semiconductor component 110 is provided, wherein the first semiconductor component 110 includes a first substrate 112 and a first a wafer 114, a first base The bottom 112 includes an opposite first surface 112a and a second surface 112b, and the first wafer 114 is disposed on the first surface 112a of the first substrate 112 (step 210). Also, a plurality of conductive pillars 116 are disposed on the first surface 112a of the first substrate 112 (step 220).
需說明的是，在本實施例中，第一半導體元件110是先配置第一晶片114之後再配置導電柱116，但在其他實施例中，第一晶片114與導電柱116設置在第一基底112上的順序並不以此為限制。 It should be noted that, in this embodiment, the first semiconductor device 110 is configured with the first wafer 114 and then the conductive pillars 116 are disposed. However, in other embodiments, the first wafer 114 and the conductive pillars 116 are disposed on the first substrate. The order on 112 is not limited by this.
再來，請參閱圖5與圖7，形成一第一封裝膠體118於第一基底112的第一表面112a上以覆蓋第一晶片114與各導電柱116的一第一部分116a，其中各導電柱116的一第二部分116b凸出或齊平於第一封裝膠體118(步驟230)。在本實施例中，導電柱116的第二部分116b是齊平且外露於第一封裝膠體118。在其他實施例中，導電柱116的第二部分116b也可以是略高於第一封裝膠體118。 Referring to FIG. 5 and FIG. 7 , a first encapsulant 118 is formed on the first surface 112 a of the first substrate 112 to cover the first wafer 114 and a first portion 116 a of each of the conductive pillars 116 , wherein each conductive pillar A second portion 116b of the protrusion 116b is convex or flush with the first encapsulant 118 (step 230). In the present embodiment, the second portion 116b of the conductive post 116 is flush and exposed to the first encapsulant 118. In other embodiments, the second portion 116b of the conductive post 116 can also be slightly higher than the first encapsulant 118.
最後，請參閱圖6與圖7，連接一第二半導體元件120至第一半導體元件110。詳細地說，第二半導體元件120包括一第二基底122、一第二晶片124、一第二封裝膠體126及多個第二焊球128。第二基底122包括相對的一第三表面122a與一第四表面122b。第二晶片124配置於第二基底122的第三表面122a，第二封裝膠體126配置於第二基底122的第三表面122a上以覆蓋第二晶片124，且這些第二焊球128配置於第二基底122的第四表面122b。第二半導體元件120的第二焊球128連接至第一半導體元 件110的導電柱116的第二部分116b(步驟240)。需說明的是，為了避免多餘的線條，圖式上特意省略第一基底112與第二基底122的線路層。 Finally, referring to FIG. 6 and FIG. 7, a second semiconductor component 120 is connected to the first semiconductor component 110. In detail, the second semiconductor device 120 includes a second substrate 122 , a second wafer 124 , a second encapsulant 126 , and a plurality of second solder balls 128 . The second substrate 122 includes a third surface 122a and a fourth surface 122b opposite to each other. The second wafer 124 is disposed on the third surface 122a of the second substrate 122, the second encapsulant 126 is disposed on the third surface 122a of the second substrate 122 to cover the second wafer 124, and the second solder balls 128 are disposed on the second surface The fourth surface 122b of the second substrate 122. The second solder ball 128 of the second semiconductor component 120 is connected to the first semiconductor element The second portion 116b of the conductive post 116 of the piece 110 (step 240). It should be noted that, in order to avoid unnecessary lines, the circuit layers of the first substrate 112 and the second substrate 122 are intentionally omitted in the drawing.
在本實施例中，導電柱116的第二部分116b是齊平於第一封裝膠體118，因此，導電柱116的第二部分116b是導電柱116外露於第一封裝膠體118的一上表面。第二半導體元件120透過位於第四表面122b的第二焊球128連接至第一半導體元件110的導電柱116的第二部分116b，以完成堆疊式封裝100。相較於習知，本實施例的堆疊式封裝的製造方法200能夠省去習知在第一基底12上配置用以連接第二半導體元件16的焊球14，以及移除局部的第一封裝膠體15的步驟，而簡化整體的製造程序。 In the present embodiment, the second portion 116b of the conductive post 116 is flush with the first encapsulant 118. Therefore, the second portion 116b of the conductive post 116 is a conductive post 116 exposed on an upper surface of the first encapsulant 118. The second semiconductor component 120 is connected to the second portion 116b of the conductive pillar 116 of the first semiconductor component 110 through the second solder ball 128 on the fourth surface 122b to complete the stacked package 100. Compared with the prior art, the manufacturing method 200 of the stacked package of the present embodiment can eliminate the conventional solder ball 14 disposed on the first substrate 12 for connecting the second semiconductor component 16, and remove the partial first package. The step of colloid 15 simplifies the overall manufacturing process.
本實施例也提供了一種新的堆疊式封裝100。請再參閱圖6，本實施例的堆疊式封裝100包括第一半導體元件110及疊置於第一半導體元件110的第二半導體元件120。 This embodiment also provides a new stacked package 100. Referring to FIG. 6 again, the stacked package 100 of the present embodiment includes a first semiconductor component 110 and a second semiconductor component 120 stacked on the first semiconductor component 110.
第一半導體元件110包括第一基底112、第一晶片114、多個導電柱116、第一封裝膠體118及多個第一焊球119。第一基底112包括相對的第一表面112a與第二表面112b。第一晶片114配置於第一基底112的第一表面112a。在本實施例中，第一晶片114是以球柵陣列的方式連接至第一基底112，但第一晶片114連接至第一基底112的方式並不以此為限制。導電柱116配置於第一基底112的第一表面112a且環繞第一晶片114。在本實施例中，導電柱116為一銅柱。第一封裝膠體118配置於第一基底112的 第一表面112a上以覆蓋第一晶片114與各導電柱116的第一部分116a。導電柱116的第二部分116b(也就是上表面)齊平且外露於第一封裝膠體118。第一焊球119配置於第一基底112的第二表面112b。 The first semiconductor component 110 includes a first substrate 112, a first wafer 114, a plurality of conductive pillars 116, a first encapsulant 118, and a plurality of first solder balls 119. The first substrate 112 includes opposing first and second surfaces 112a, 112b. The first wafer 114 is disposed on the first surface 112a of the first substrate 112. In the present embodiment, the first wafer 114 is connected to the first substrate 112 in a ball grid array manner, but the manner in which the first wafer 114 is connected to the first substrate 112 is not limited thereto. The conductive pillars 116 are disposed on the first surface 112a of the first substrate 112 and surround the first wafer 114. In this embodiment, the conductive post 116 is a copper post. The first encapsulant 118 is disposed on the first substrate 112 The first surface 112a covers the first wafer 114 and the first portion 116a of each of the conductive pillars 116. The second portion 116b (ie, the upper surface) of the conductive post 116 is flush and exposed to the first encapsulant 118. The first solder ball 119 is disposed on the second surface 112b of the first substrate 112.
第二半導體元件120包括第二基底122、第二晶片124、第二封裝膠體126及多個第二焊球128。第二基底122包括相對的第三表面122a與第四表面122b。第二晶片124配置於第二基底122的第三表面122a。在本實施例中，第二晶片124是以打線的方式電性連接至第二基底122，但第二晶片124連接至第二基底122的方式並不以此為限制。第二封裝膠體126配置於第二基底122的第三表面122a上以覆蓋第二晶片124。第二焊球128配置於第二基底122的第四表面122b。本實施例的堆疊式封裝100的第二半導體元件120透過第二焊球128直接連接至第一半導體元件110的導電柱116的第二部分116b，以使第一半導體元件110與第二半導體元件120之間電性連接。 The second semiconductor component 120 includes a second substrate 122, a second wafer 124, a second encapsulant 126, and a plurality of second solder balls 128. The second substrate 122 includes opposing third and second surfaces 122a, 122b. The second wafer 124 is disposed on the third surface 122a of the second substrate 122. In this embodiment, the second wafer 124 is electrically connected to the second substrate 122 in a wire bonding manner, but the manner in which the second wafer 124 is connected to the second substrate 122 is not limited thereto. The second encapsulant 126 is disposed on the third surface 122 a of the second substrate 122 to cover the second wafer 124 . The second solder ball 128 is disposed on the fourth surface 122b of the second substrate 122. The second semiconductor component 120 of the stacked package 100 of the present embodiment is directly connected to the second portion 116b of the conductive pillar 116 of the first semiconductor component 110 through the second solder ball 128 to make the first semiconductor component 110 and the second semiconductor component Electrical connection between 120.
綜上所述，相較於習知的堆疊式封裝需要透過在第一半導體元件的第一基底上預先配置用以連接第二半導體元件的焊球，並且還需透過雷射鑽孔等方式移除局部的第一封裝膠體而使焊球外露。本發明的堆疊式封裝的製造方法透過在第一基底上配置多個導電柱，且各導電柱的第二部分凸出或齊平於第一封裝膠體，以使第二半導體元件的第二焊球能夠直接與第一半導體元件的導電柱連接而完成堆疊式封裝的結構。因此，本發明的堆疊式 封裝的製造方法能夠省去在第一基底上配置用以連接第二半導體元件的焊球，以及移除局部的第一封裝膠體的步驟。並且，本發明也提供了一種新結構的堆疊式封裝。 In summary, compared with the conventional stacked package, it is required to pre-configure the solder ball for connecting the second semiconductor element on the first substrate of the first semiconductor element, and also needs to be moved by laser drilling or the like. The solder balls are exposed except for the partial first encapsulant. The method for manufacturing a stacked package of the present invention is characterized in that a plurality of conductive pillars are disposed on a first substrate, and a second portion of each conductive pillar is convex or flush with the first encapsulant to enable second soldering of the second semiconductor component. The ball can be directly connected to the conductive pillars of the first semiconductor element to complete the structure of the stacked package. Therefore, the stacked type of the present invention The manufacturing method of the package can omit the step of disposing a solder ball on the first substrate for connecting the second semiconductor element, and removing the partial first encapsulant. Moreover, the present invention also provides a stacked package of a new structure.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100‧‧‧堆疊式封裝 100‧‧‧Stacked package
110‧‧‧第一半導體元件 110‧‧‧First semiconductor component
112‧‧‧第一基底 112‧‧‧First base
112a‧‧‧第一表面 112a‧‧‧ first surface
112b‧‧‧第二表面 112b‧‧‧ second surface
114‧‧‧第一晶片 114‧‧‧First chip
116‧‧‧導電柱 116‧‧‧conductive column
116a‧‧‧第一部分 116a‧‧‧Part 1
116b‧‧‧第二部分 116b‧‧‧Part II
118‧‧‧第一封裝膠體 118‧‧‧First encapsulant
119‧‧‧第一焊球 119‧‧‧First solder ball
120‧‧‧第二半導體元件 120‧‧‧Second semiconductor component
122‧‧‧第二基底 122‧‧‧Second substrate
122a‧‧‧第三表面 122a‧‧‧ third surface
122b‧‧‧第四表面 122b‧‧‧Fourth surface
124‧‧‧第二晶片 124‧‧‧second chip
126‧‧‧第二封裝膠體 126‧‧‧Second encapsulant
128‧‧‧第二焊球 128‧‧‧second solder ball
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104106831A TW201633494A (en) | 2015-03-04 | 2015-03-04 | Package on package and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW104106831A TW201633494A (en) | 2015-03-04 | 2015-03-04 | Package on package and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201633494A true TW201633494A (en) | 2016-09-16 |
Family
ID=57443292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW104106831A TW201633494A (en) | 2015-03-04 | 2015-03-04 | Package on package and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TW201633494A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107919333A (en) * | 2017-12-28 | 2018-04-17 | 江阴长电先进封装有限公司 | A kind of three-dimensional POP encapsulating structures and its method for packing |
-
2015
- 2015-03-04 TW TW104106831A patent/TW201633494A/en unknown
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107919333A (en) * | 2017-12-28 | 2018-04-17 | 江阴长电先进封装有限公司 | A kind of three-dimensional POP encapsulating structures and its method for packing |
| CN107919333B (en) * | 2017-12-28 | 2023-08-29 | 江阴长电先进封装有限公司 | Three-dimensional POP packaging structure and packaging method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI656613B (en) | Chip package structure and method of manufacturing same | |
| TWI557868B (en) | Semiconductor device and manufacturing method thereof | |
| US20090127682A1 (en) | Chip package structure and method of fabricating the same | |
| TW201644024A (en) | Chip packaging structure and manufacture method thereof | |
| KR101605600B1 (en) | Manufacturing method of semiconductor device and semiconductor device thereof | |
| KR20150091932A (en) | Manufacturing method of semiconductor device and semiconductor device thereof | |
| US9324633B2 (en) | Multi-level package assembly having conductive vias coupled to chip carrier for each level and method for manufacturing the same | |
| US20150014848A1 (en) | Semiconductor device and fabrication method thereof | |
| US10943842B2 (en) | Semiconductor device with a protection mechanism and associated systems, devices, and methods | |
| JP2013211407A (en) | Semiconductor module | |
| US20160233205A1 (en) | Method for fabricating semiconductor package | |
| JP5358089B2 (en) | Semiconductor device | |
| TW201528453A (en) | Semiconductor package and manufacturing method thereof | |
| JP2008103685A (en) | Semiconductor device and method of manufacturing same | |
| US20160126176A1 (en) | Package substrate, package structure and fabrication method thereof | |
| US20150054150A1 (en) | Semiconductor package and fabrication method thereof | |
| TW201633494A (en) | Package on package and manufacturing method thereof | |
| KR100772103B1 (en) | Stack type package and manufacture method thereof | |
| US11417581B2 (en) | Package structure | |
| US8603911B2 (en) | Semiconductor device and fabrication method thereof | |
| TWI559470B (en) | Non-substrate semiconductor package structure and manufacturing method thereof | |
| TWI473242B (en) | Chip package structure | |
| US20160163629A1 (en) | Semiconductor package and method of fabricating the same | |
| TWI588940B (en) | Package on package and manufacturing method thereof | |
| KR20120030769A (en) | Semiconductor device and fabricating method thereof |