CN103400767B - First sealing chip flipchip bump three-dimensional systematic metal circuit board and process after erosion - Google Patents
First sealing chip flipchip bump three-dimensional systematic metal circuit board and process after erosion Download PDFInfo
- Publication number
- CN103400767B CN103400767B CN201310339207.7A CN201310339207A CN103400767B CN 103400767 B CN103400767 B CN 103400767B CN 201310339207 A CN201310339207 A CN 201310339207A CN 103400767 B CN103400767 B CN 103400767B
- Authority
- CN
- China
- Prior art keywords
- photoresistance film
- basal board
- metal
- metal basal
- board front
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
The present invention relates to sealing chip flipchip bump three-dimensional systematic metal circuit board and process thereof after one is first lost, described structure includes Metal Substrate sheet frame, it is provided with Ji Dao and pin in described Metal Substrate sheet frame, front upside-down mounting at described Ji Dao and pin has chip, described pin front is provided with conductive posts, the region that described base island is peripheral, region between Ji Dao and pin, region between pin and pin, Ji Dao and the region on pin top, plastic packaging material all it is encapsulated with outside Ji Dao and the region of pin bottom and chip and conductive posts, at described Metal Substrate sheet frame, pin and conductive posts are exposed the surface of plastic packaging material and are coated with anti oxidation layer, described conductive posts top is provided with metal ball.The present invention can solve the problem that conventional metals lead frame cannot be imbedded object and limit the functional of die-attach area and application performance.
Description
Technical field
The present invention relates to sealing chip flipchip bump three-dimensional systematic metal circuit board and process after one is first lost.Belong to
Technical field of semiconductor encapsulation.
Background technology
The basic process for making of conventional metals lead frame has an in the following manner:
1) take the technology that a sheet metal utilizes mechanically bottom tool die-cut make the most from top to bottom or by under
It is punched out on and, promotes lead frame to draw in being formed with the carrying Ji Dao of chip and signal transmission in sheet metal
The outer pin that foot is connected with extraneous PCB, carry out the most again interior pin and (or) some region of Ji Dao carries out electrodeposition of metals quilt
Cover and form the lead frame (seeing Figure 72 ~ Figure 74) that really can use.
2) take a sheet metal utilize the technology of chemical etching to be exposed, develop, window, chemical etching, promote lead frame
What frame can be formed with in sheet metal that the interior pin of the carrying Ji Dao of chip and signal transmission is connected with external world PCB outer draws
Foot, carry out the most again interior pin and (or) to carry out electrodeposition of metals coating and formed and really can use for some region of Ji Dao
Lead frame (sees Figure 75 ~ Figure 76).
3) another way is exactly based on method one or method two, is having the Ji Dao of chip bearing, letter
Outer pin that the interior pin of number transmission is connected with extraneous PCB and interior pin and (or) some region of Ji Dao carries out metal
Electrodeposited coating is coated to the lead frame back side of formation and pastes the high temperature glued membrane that last layer can resist 260 degrees Celsius again, becomes and can use four
Face leadless packages and reduce the lead frame (seeing Figure 77) of encapsulation of plastic packaging volume.
4.) another way is exactly with method one or method two, is transmitted by Ji Dao, the signal with chip bearing
Outer pin that interior pin is connected with extraneous PCB and interior pin and (or) some region of Ji Dao carries out electrodeposition of metals quilt
Cover formed lead frame and carry out pre-packaged, or the area filling heat cured epoxy tree that be chemically etched punched at sheet metal
Fat fill so that it is become can use four sides leadless packages, reduce plastic packaging volume and copper wire bonding ability encapsulation
Pre-packing type lead frame (seeing Figure 78).
Two, the shortcoming of Conventional processing methods:
1.) machinery punching-type lead frame:
A.) machinery is die-cut is to utilize upper bottom tool from top to bottom or to be from bottom to top punched out forming vertical cross section, institute
With cannot carry out again inside lead frame completely other function or object embedment utilization such as system object be integrated in metal lead wire
Frame itself
B.) mechanical stamping be utilize upper bottom tool mutually to be extruded by sheet metal edge and along stretching out metallic region, and
The metallic region length stretched out along being extruded can only be at most the 80% of lead frame thickness.If it exceeds lead frame thickness 80% with
Time upper, its be extruded extended metallic region be easy to occur warpage, hidden split, rupture, irregularly shaped and surface holes
The problems such as hole, and ultra-thin lead frame the most easily produces problem above (seeing Figure 79 ~ Figure 80).
C.) if the metallic region length stretched out along mechanical stamping than lead frame thickness less than less than 80% or just
80% can cause again because cannot place into related object (especially in the metallic region extended along the curtailment stretched
It is that thickness needs ultra-thin lead frame cannot accomplish especially) (seeing Figure 81 ~ Figure 82).
2.) chemical etch technique mode lead frame:
A.) subtractive lithography can use half-etching technology to imbed the spatial etch of object out by needing, but maximum
Shortcoming is exactly the more difficult control of flatness of etch depth size and etching back plane.
B.), after metallic plate completes the half-etched regions much needing to imbed object, the structural strength of lead frame can become phase
When soft, can directly influence follow-up imbed object again required for working condition (such as pick and place, transport, high temperature, high pressure and heat should
Power shrink) difficulty.
C.) lead frame of chemical etch technique mode can only present at most lead frame front and the back side outer foot or
Interior foot type state, cannot hold the system-level die-attach area revealing multi-layer three-dimension metallic circuit completely.
Summary of the invention
It is an object of the invention to overcome above-mentioned deficiency, it is provided that after one is first lost, sealing chip flipchip bump three-dimensional systematic is golden
Belonging to wiring board and process, it can solve the problem that conventional metals lead frame cannot be imbedded object and limit the function of die-attach area
Property and application performance.
The object of the present invention is achieved like this: one first lose after sealing chip flipchip bump three-dimensional systematic metal circuit board
Process, described method comprises the steps:
Step one, take metal basal board
Step 2, the micro-layers of copper of metallic substrate surfaces preplating
Step 3, patch photoresistance film operation
The photoresistance film that can be exposed development is sticked respectively in the metal basal board front and the back side completing the micro-layers of copper of preplating；
Part photoresistance film is removed at step 4, the metal basal board back side
The metal basal board back side utilizing exposure imaging equipment that step 3 completes to paste photoresistance film operation carries out graph exposure, shows
Shadow and removal partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in the metal basal board back side carry out electroplating；
Step 5, plated metal line layer
Metallic circuit layer is electroplated in the region of metal basal board back side removal part photoresistance film in step 4；
Step 6, patch photoresistance film operation
In step 5, the photoresistance film that can be exposed development is sticked at the metal basal board back side；
Part photoresistance film is removed at step 7, the metal basal board back side
The metal basal board back side utilizing exposure imaging equipment that step 6 completes to paste photoresistance film operation carries out graph exposure, shows
Shadow and removal partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in the metal basal board back side carry out electroplating；
Step 8, plating high-conductive metal line layer
High-conductive metal line layer is electroplated in the region of metal basal board back side removal part photoresistance film in step 7；
Step 9, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces；
Step 10, epoxy resin plastic packaging
Epoxide resin material is utilized to carry out plastic packaging protection on the metallic circuit layer surface at the metal basal board back side；
Step 11, epoxy resin surface grind
Epoxy resin surface grinding is carried out after completing epoxy resin plastic packaging；
Step 12, patch photoresistance film operation
The photoresistance film that can be exposed development is sticked at the metal basal board front and back completing step 11；
Part photoresistance film is removed in step 13, metal basal board front
Utilize exposure imaging equipment step 12 is completed paste photoresistance film operation metal basal board front carry out graph exposure,
Development and removal partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in metal basal board front are etched；
Step 14, chemical etching
The region that metal basal board front in step 13 completes exposure imaging is carried out chemical etching；
Step 15, patch photoresistance film operation
The photoresistance film that can be exposed development is sticked at the metal basal board front and back completing step 14；
Part photoresistance film is removed in step 10 six, metal basal board front
Utilize exposure imaging equipment step 15 is completed paste photoresistance film operation metal basal board front carry out graph exposure,
Development and removal partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in metal basal board front carry out electroplating；
Step 10 seven, plated metal pillar
Metal pillar is electroplated in the region of metal basal board front removal part photoresistance film in step 10 six；
Step 10 eight, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces；
Step 10 nine, load
Complete step 10 eight Hou Ji island and pin top by underfill flip-chip；
Step 2 ten, encapsulating
Plastic packaging material is used to carry out plastic packaging in the metal basal board front in step 10 nine；
Step 2 11, epoxy resin surface grind
Epoxy resin surface grinding is carried out after completing the epoxy resin plastic packaging of step 2 ten；
Step 2 12, plating anti-oxidant metal layer or batch cover antioxidant (OSP)
The exposed metal of metallic substrate surfaces after completing step 2 11 carry out electroplate anti-oxidant metal layer or
Criticize and cover antioxidant (OSP)
Step 2 13, plant ball
Complete the metal pillar top implanted metal ball of step 2 12.
Described step 15 moves and carries out between step 4 and step 5.
One first lose after sealing chip flipchip bump three-dimensional systematic metal circuit board, it includes Metal Substrate sheet frame, described
It is provided with Ji Dao and pin in Metal Substrate sheet frame, has chip in the front of described Ji Dao and pin by underfill upside-down mounting,
Conductive posts it is provided with, region between region, Ji Dao and pin that described base island is peripheral, pin and draw in described pin front
Outside region, Ji Dao and the region on pin top, Ji Dao and the region of pin bottom between foot and chip and conductive posts all
Being encapsulated with plastic packaging material, described plastic packaging material flushes with the top of conductive posts, reveals in described Metal Substrate sheet frame, pin and conductive posts
The surface going out plastic packaging material is coated with anti oxidation layer or coating antioxidant, and described conductive posts top is provided with metal ball.
One first lose after sealing chip flipchip bump three-dimensional systematic metal circuit board, it includes Metal Substrate sheet frame and chip,
Be provided with pin in arranging in described Metal Substrate sheet frame, described chip by underfill upside-down mounting in pin front, in institute
State pin front and be provided with conductive posts, the region between described pin and pin, the region on pin top, the district of pin bottom
All being encapsulated with plastic packaging material outside territory and chip and conductive posts, described plastic packaging material flushes with the top of conductive posts, at described gold
Belong to substrate, pin and conductive posts are exposed the surface of plastic packaging material and are coated with anti oxidation layer or batch cover antioxidant (OSP), lead described
Electricity pillar top is provided with metal ball.
Bridging passive device by conductive bond material between described pin and pin, described passive device can be connected across
Between pin front and pin front, or it is connected across between pin front and the front of static release ring, or is connected across electrostatic and releases
Putting between the front of circle and the front of Ji Dao, be provided with static release ring between described Ji Dao and pin, described chip is just
It is connected by metal wire between face with static release ring front.
Described conductive posts has multi-turn.
In described chip front side, conduction or non-conductive bonding material are provided with the second chip, described second chip front side
It is connected by metal wire with between pin.
Described pin front is provided with the second conductive posts, in described second conductive posts by upside-down mounting on conductive materials
The second chip, described second conductive posts and the second chip is had to be in the inside of plastic packaging material.
Described pin front is provided with the second conductive posts, equipped with passive device in described second conductive posts, institute
State the second conductive posts and passive device is in the inside of plastic packaging material.
The process of sealing chip flipchip bump three-dimensional systematic metal circuit board after a kind of first erosion, described method include as
Lower step:
Step one, take metal basal board
Step 2, the micro-layers of copper of metallic substrate surfaces preplating
Step 3, patch photoresistance film operation
The photoresistance film that can be exposed development is sticked respectively in the metal basal board front and the back side completing the micro-layers of copper of preplating；
Part photoresistance film is removed in step 4, metal basal board front
The metal basal board front utilizing exposure imaging equipment that step 3 completes to paste photoresistance film operation carries out graph exposure, shows
Shadow and removal partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in metal basal board front carry out electroplating；
Step 5, electroplate the first metallic circuit layer
The first metallic circuit layer is electroplated in the region of metal basal board front removal part photoresistance film in step 4；
Step 6, patch photoresistance film operation
In step 5, the photoresistance film that can be exposed development is sticked in metal basal board front；
Part photoresistance film is removed in step 7, metal basal board front
The metal basal board front utilizing exposure imaging equipment that step 6 completes to paste photoresistance film operation carries out graph exposure, shows
Shadow and removal partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in metal basal board front carry out electroplating；
Step 8, electroplate the second metallic circuit layer
The second metallic circuit layer conduct in plating in the region of metal basal board front removal part photoresistance film in step 7
In order to connect the first metallic circuit layer and the conductive posts of the 3rd metallic circuit layer；
Step 9, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces；
Step 10, pressing non-conductive glued membrane operation
At one layer of non-conductive glued membrane of metal basal board front pressing；
Step 11, grind non-conductive film surface
Surface grinding is carried out after completing non-conductive glued membrane pressing；
The metallization pretreatment of step 12, non-conductive film surface
Non-conductive film surface is carried out pretreatment of metallizing；
Step 13, patch photoresistance film operation
In step 12, metal basal board front and back sticks the photoresistance film that can be exposed development；
Part photoresistance film is removed in step 14, metal basal board front
Utilize exposure imaging equipment step 13 is completed paste photoresistance film operation metal basal board front carry out graph exposure,
Development and removal partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in metal basal board front are etched；Step 10
Five, etching operation
Complete the region after photoresistance film is windowed in step 14 and be etched operation；
Photoresistance film is removed in step 10 six, metal basal board front
Remove the photoresistance film in metal basal board front, the metallic region figure being plated to expose follow-up needs to carry out；
Step 10 seven, plating the 3rd metallic circuit layer
The plating work of the 3rd metallic circuit layer is carried out in the metal basal board front of step 10 six；
Step 10 eight, patch photoresistance film operation
The photoresistance film that can be exposed development is sticked in the metal basal board front of step 10 seven；
Part photoresistance film is removed in step 10 nine, metal basal board front
Utilize exposure imaging equipment step 10 eight is completed paste photoresistance film operation metal basal board front carry out graph exposure,
Development and removal partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in metal basal board front carry out electroplating；
Step 2 ten, plating the 4th metallic circuit layer
In step 10 nine, in the region of metal basal board front removal part photoresistance film, in plating, the 4th metallic circuit layer is made
For the conductive posts in order to connect the 3rd metallic circuit layer and fifth metal line layer；
Step 2 11, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces；
Step 2 12, pressing non-conductive glued membrane operation
At one layer of non-conductive glued membrane of metal basal board front pressing；
Step 2 13, grind non-conductive film surface
Surface grinding is carried out after completing non-conductive glued membrane pressing；
The metallization pretreatment of step 2 14, non-conductive film surface
Non-conductive film surface is carried out pretreatment of metallizing；
Step 2 15, patch photoresistance film operation
In step 2 14, metal basal board front and back sticks the photoresistance film that can be exposed development；
Part photoresistance film is removed in step 2 16, metal basal board front
The metal basal board front utilizing exposure imaging equipment that step 2 15 completes to paste photoresistance film operation carries out figure exposure
Light, develop with remove partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in metal basal board front are etched；Step
27, etching operation
Complete the region after photoresistance film is windowed in step 2 16 and be etched operation；
Photoresistance film is removed in step 2 18, metal basal board front
Remove the photoresistance film in metal basal board front；
Step 2 19, plating fifth metal line layer
The plating work of fifth metal line layer, fifth metal line layer is carried out in the metal basal board front of step 2 18
Corresponding Ji Dao and pin is formed the most on metallic substrates after having electroplated；
Step 3 ten, patch photoresistance film operation
In step 2 19, the photoresistance film that can be exposed development is sticked in metal basal board front；
Part photoresistance film is removed at step 3 11, the metal basal board back side
Utilize exposure imaging equipment step 3 ten is completed paste photoresistance film operation the metal basal board back side carry out graph exposure,
Development and removal partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in the metal basal board back side are etched；
Step 3 12, chemical etching
The region that the metal basal board back side in step 3 11 completes exposure imaging is carried out chemical etching, chemical etching until
Till metallic circuit layer；
Step 3 13, patch photoresistance film operation
The photoresistance film that can be exposed development is sticked at the metal basal board back side completing chemical etching in step 3 12；
Part photoresistance film is removed at step 3 14, the metal basal board back side
The metal basal board back side utilizing exposure imaging equipment that step 3 13 completes to paste photoresistance film operation carries out figure exposure
Light, develop with remove partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in the metal basal board back side carry out electroplating；
Step 3 15, plated metal pillar
Metal pillar is electroplated in the region of metal basal board back side removal part photoresistance film in step 3 14；
Step 3 16, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces；
Step 3 17, load
By underfill flip-chip on the Ji Dao completing step 3 16 and pin；
Step 3 18, encapsulating
Epoxy resin (being commonly called as plastic packaging material) is used to carry out plastic packaging at the metal basal board back side in step 3 17；
Step 3 19, epoxy resin surface grind
Epoxy resin surface grinding is carried out after completing the epoxy resin plastic packaging of step 3 18；
Step 4 ten, plating anti-oxidant metal layer or batch cover antioxidant (OSP)
The exposed metal of metallic substrate surfaces after completing step 3 19 carry out electroplate anti-oxidant metal layer or
Criticize and cover antioxidant (OSP)；
Step 4 11, plant ball
Metal pillar top implanted metal ball after completing step 4 ten.
Described step 6, to the repeatable operation of step 10 seven, forms the metallic circuit layer of more layers.
Compared with prior art, the method have the advantages that
1) metal current lead frame all uses the die-cut or chemical etching mode of machinery, it is impossible to make multiple layer metal circuit
Layer, and the interlayer in the middle of punching-type die-attach area cannot be imbedded any object, and the 3-dimensional metal circuit of the present invention is multiple
Box-like substrate can in a substrate between interlayer in imbed object.
2) interlayer in 3-dimensional metal circuit composite substrate can be because heat conduction or heat radiation need in the position needed
Put or imbed in region heat conduction or heat radiation object, become a system-level die-attach area of hot property.(seeing Figure 83)
3) interlayer in 3-dimensional metal circuit composite substrate can be because of system and the needs of function in the position needed
Put or in region, imbed active member or assembly or passive assembly, becoming a system-level die-attach area.
4) outward appearance from 3-dimensional metal circuit composite substrate finished product be can't see internal interlayer completely and imbedded because being
The object that system or function need, the especially chip buried X-ray of silicon material all cannot be inspected, and sufficiently achieves system and function
Confidentiality and protectiveness.
5) 3-dimensional metal circuit composite substrate finished product is inherently rich in various assemblies, if no longer carrying out follow-up
Under its condition of secondary encapsulation, as long as 3-dimensional metal circuit composite substrate is cut according to each lattice unit, inherently can become
One ultra-thin packaging body.
6) 3-dimensional metal circuit composite substrate can also carry out secondary in addition to the embedment function itself including object
Encapsulation, sufficiently reaches the integration of systemic-function.
7) 3-dimensional metal circuit composite substrate can also be at packaging body in addition to the embedment function itself including object
The peripheral unit that superposition is different again encapsulation or system in package, sufficiently achieve the encapsulation technology energy of dual system or polyphyly irrespective of size
Power.
8) 3-dimensional metal circuit base plate can apply to multi-chip modules (MCM) encapsulation (seeing Figure 84 and Figure 85), and three
It is bigger than conventional MCM substrate ground low cost, toughness that Vygen belongs to circuit base plate.
Accompanying drawing explanation
Fig. 1 ~ Figure 23 is each operation of sealing chip upside-down mounting three-dimensional systematic metal circuit board process after the present invention first loses
Schematic diagram.
Figure 24 is the schematic diagram of sealing chip flipchip bump three-dimensional systematic metal circuit board embodiment 1 after the present invention first loses.
Figure 25 is the schematic diagram of sealing chip flipchip bump three-dimensional systematic metal circuit board embodiment 2 after the present invention first loses.
Figure 26 is the schematic diagram of sealing chip flipchip bump three-dimensional systematic metal circuit board embodiment 3 after the present invention first loses.
Figure 27 is the schematic diagram of sealing chip flipchip bump three-dimensional systematic metal circuit board embodiment 4 after the present invention first loses.
Figure 28 is the schematic diagram of sealing chip flipchip bump three-dimensional systematic metal circuit board embodiment 5 after the present invention first loses.
Figure 29 is the schematic diagram of sealing chip flipchip bump three-dimensional systematic metal circuit board embodiment 6 after the present invention first loses.
Figure 30 ~ Figure 70 is the work of sealing chip flipchip bump three-dimensional systematic metal circuit board embodiment 7 after the present invention first loses
Process flow figure.
Figure 71 is the schematic diagram of sealing chip flipchip bump three-dimensional systematic metal circuit board embodiment 7 after the present invention first loses.
Figure 72 is the die-cut schematic diagram in the basic process for making of conventional metals lead frame.
Figure 73 be conventional metals lead frame basic process for making in the schematic diagram of strip shaped metals sheet.
Figure 74 be conventional metals lead frame basic process for making in the schematic diagram of front lead frame.
Figure 75 is conventional metals lead frame through overexposure, develops, windows, cuts open in the basic process for making of etching etc.
The schematic diagram in face.
Figure 76 be conventional metals lead frame basic process for making in the schematic diagram of front lead frame.
Figure 77 be conventional metals lead frame basic process for making in the cross-sectional view of QFN.
Figure 78 be conventional metals lead frame basic process for making in the schematic diagram of pre-packing type lead frame.
Figure 79 be conventional metals lead frame basic process for making in upper bottom tool extruding formed and extend metal area
The schematic diagram in territory.
Figure 80 be conventional metals lead frame basic process for making in upper bottom tool extruding formed and extend metal area
Hidden produced by territory split, rupture, the schematic diagram of warpage.
Figure 81 be conventional metals lead frame basic process for making in upper bottom tool extruding formed along stretching metal area
The schematic diagram of length of field deficiency lead frame thickness 80%.
Figure 82 be conventional metals lead frame basic process for making in upper bottom tool extruding formed along stretching metal area
The 80% of length of field deficiency lead frame thickness is produced the schematic diagram of embedment object difficulty.
Figure 83 is that the interlayer in 3-dimensional metal circuit composite substrate can be because heat conduction or heat radiation need at needs
Position or region in imbed heat conduction or heat radiation object schematic diagram.
Figure 84 is the schematic diagram that 3-dimensional metal circuit base plate is applied to that multi-chip modules (MCM) encapsulates.
Figure 85 is the top view of Figure 84.
Wherein:
Metal Substrate sheet frame 1
Base island 2
Pin 3
Underfill 4
Chip 5
Metal wire 6
Conductive posts 7
Plastic packaging material 8
Anti oxidation layer or batch cover antioxidant 9
Passive device 10
Static release ring 11
Second chip 12
Second conductive posts 13
Conductive materials 14
Conduction or non-conductive bonding material 15
Metal ball 16.
Detailed description of the invention
One of the present invention first lose after sealing chip flipchip bump three-dimensional systematic metal circuit board and process as follows:
Embodiment 1, monolayer circuit single-chip upside-down mounting individual pen pin
See Figure 24, the knot of sealing chip flipchip bump three-dimensional systematic metal circuit board embodiment 1 after first losing for the present invention
Structure schematic diagram, it includes Metal Substrate sheet frame 1, is provided with base island 2 and pin 3, described base island 2 He in described Metal Substrate sheet frame 1
There is chip 5 in pin 3 front by underfill 4 upside-down mounting, and described pin 3 front is provided with conductive posts 7, described base island 2
Peripheral region, base island 2 and the district on pin 3 top between region, pin 3 and pin 3 between region, base island 2 and pin 3
Territory, base island 2 and the region of pin 3 bottom and chip 5 and the outer plastic packaging material 8 that is all encapsulated with of conductive posts 7, described plastic packaging material 8 with
The top of conductive posts 7 flushes, and exposes the plated surface of plastic packaging material 8 in described metal basal board 1, base island 2, pin 3 and conductive posts 7
There is anti oxidation layer or batch cover antioxidant (OSP) 9, described conductive posts 7 top is provided with metal ball 16.
Its process is as follows:
Step one, take metal basal board
Seeing Fig. 1, take the suitable metal basal board of a piece of thickness, the purpose that this sheet material uses simply makes with follow-up for circuit
Encapsulation supports the transitional material that line layer structure is used, and the material of this sheet material is mainly based on metal material, and metal
The material of material can be copper material iron material zinc-plated material stainless steel aluminium maybe can reach conducting function metallics or
Non-all-metal material etc..
Step 2, the micro-layers of copper of metallic substrate surfaces preplating
Seeing Fig. 2, in the micro-layers of copper of metallic substrate surfaces preplating, micro-copper layer thickness, at 2 ~ 10 microns, needs also according to function
Can be thinning or thicken, primarily to enable line layer and metal basal board fluid-tight engagement, plating when follow-up circuit makes
Mode can use chemical deposition or electrolysis plating.
Step 3, patch photoresistance film operation
See Fig. 3, stick respectively in the metal basal board front and the back side completing the micro-layers of copper of preplating and can be exposed development
Photoresistance film, to protect follow-up electroplated metal layer process operation, photoresistance film can be dry type photoresistance film can also be wet type photoresistance
Film.
Part photoresistance film is removed at step 4, the metal basal board back side
Seeing Fig. 4, the metal basal board back side utilizing exposure imaging equipment that step 3 completes to paste photoresistance film operation carries out figure
Shape exposes, develops and remove partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in the metal basal board back side carry out electroplating.
Step 5, plated metal line layer
See Fig. 5, in step 4, electroplate metallic circuit layer in the region of metal basal board back side removal part photoresistance film,
Metallic circuit layer material can be copper, aluminum, nickel, silver, gold, copper silver, nickel gold, NiPdAu (usual 5 ~ 20 microns, can be according to difference
Characteristic conversion plating thickness) etc. material, other electrically conductive metallics can use certainly, do not limit to copper, aluminum,
The metal material such as nickel, silver, gold, copper silver, nickel gold, NiPdAu, plating mode can be chemical deposition or electrolysis plating mode.
Step 6, patch photoresistance film operation
Seeing Fig. 6, in step 5, the photoresistance film that can be exposed development is sticked at the metal basal board back side, and photoresistance film can be
Dry type photoresistance film can also be wet type photoresistance film.
Part photoresistance film is removed at step 7, the metal basal board back side
Seeing Fig. 7, the metal basal board back side utilizing exposure imaging equipment that step 6 completes to paste photoresistance film operation carries out figure
Shape exposes, develops and remove partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in the metal basal board back side carry out electroplating.
Step 8, plating high-conductive metal line layer
See Fig. 8, in step 7, electroplate high-conductive metal line in the region of metal basal board back side removal part photoresistance film
Road floor, the material of high-conductive metal line layer can be the materials such as copper, aluminum, nickel, silver, gold, copper silver, nickel gold, NiPdAu, certainly its
Its electrically conductive metallics can use, and does not limit to the metals such as copper, aluminum, nickel, silver, gold, copper silver, nickel gold, NiPdAu
Material, plating mode can make chemical deposition or electrolysis plating mode.
Step 9, removal photoresistance film
Seeing Fig. 9, remove the photoresistance film of metallic substrate surfaces, the method removing photoresistance film can use chemical medicinal liquid to soften also
The mode using high pressure water washing removes photoresistance film.
Step 10, epoxy resin plastic packaging
Seeing Figure 10, metallic circuit layer and high-conductive metal line layer surface at the metal basal board back side utilize epoxy resin
Material carries out plastic packaging protection, and epoxide resin material can select according to product attribute to be had filler or do not have the kind of filler, moulds
Envelope mode can be to use mould encapsulating mode, spraying equipment spraying method, pad pasting mode or the mode of brush coating.
Step 11, epoxy resin surface grind
See Figure 11, after completing epoxy resin plastic packaging, carry out epoxy resin surface grinding, it is therefore an objective to make outer foot function
High-conductive metal line layer expose plastic-sealed body surface and control epoxy resin thickness.
Step 12, patch photoresistance film operation
See Figure 12, stick the photoresistance that can be exposed development at the metal basal board front and back completing step 11
Film, photoresistance film can be dry type photoresistance film can also be wet type photoresistance film.
Part photoresistance film is removed in step 13, metal basal board front
Seeing Figure 13, the metal basal board front utilizing exposure imaging equipment that step 12 completes to paste photoresistance film operation is carried out
Graph exposure, develop with remove partial graphical photoresistance film, to expose the administrative division map that the follow-up needs in metal basal board front are etched
Shape.
Step 14, chemical etching
Seeing Figure 14, the region that metal basal board front in step 13 completes exposure imaging carries out chemical etching, chemistry
Till being etched through metallic circuit layer, etching solution can use copper chloride or iron chloride or can carry out chemical etching
Liquid medicine.
Step 15, patch photoresistance film operation
See Figure 15, stick the photoresistance that can be exposed development at the metal basal board front and back completing step 14
Film, photoresistance film can be dry type photoresistance film can also be wet type photoresistance film.
Part photoresistance film is removed in step 10 six, metal basal board front
Seeing Figure 16, the metal basal board front utilizing exposure imaging equipment that step 15 completes to paste photoresistance film operation is carried out
Graph exposure, develop with remove partial graphical photoresistance film, to expose the administrative division map that the follow-up needs in metal basal board front carry out electroplating
Shape.
Step 10 seven, plated metal pillar
See Figure 17, in step 10 six, electroplate metal column in the region of metal basal board front removal part photoresistance film
Son, the material of metal pillar can be the materials such as copper, aluminum, nickel, silver, gold, copper silver, nickel gold, NiPdAu, and other is electrically conductive certainly
Metallics can use, do not limit to the metal materials such as copper, aluminum, nickel, silver, gold, copper silver, nickel gold, NiPdAu, plating side
Formula can make chemical deposition or electrolysis plating mode.
Step 10 eight, removal photoresistance film
Seeing Figure 18, remove the photoresistance film of metallic substrate surfaces, the method removing photoresistance film can use chemical medicinal liquid to soften
And use the mode of high pressure water washing to remove photoresistance film.
Step 10 nine, load
Seeing Figure 19, by underfill flip-chip on the Ji Dao and pin of step 10 eight, the mode of upside-down mounting can
To fall after underfill being coated on Ji Dao and pin in upside-down mounting again chip or underfill being coated in chip front side
It is loaded on Ji Dao and pin front.
Step 2 ten, encapsulating
Seeing Figure 20, use plastic packaging material to carry out plastic packaging in the metal basal board front in step 10 nine, plastic packaging mode can be adopted
With mould encapsulating mode, spraying equipment spraying method or use pad pasting mode, described plastic packaging material can use packing material or
It is the epoxy resin of no-arbitrary pricing material.
Step 2 11, epoxy resin surface grind
See Figure 21, after completing the epoxy resin plastic packaging of step 2 ten, carry out epoxy resin surface grinding, it is therefore an objective to
Metal pillar is made to expose plastic-sealed body surface and control the thickness of epoxy resin.
Step 2 12, plating anti-oxidant metal layer or coating antioxidant (OSP)
Seeing Figure 22, the exposed metal of metallic substrate surfaces after completing step 2 11 carries out electroplating antioxidation
Metal level, prevents burning, such as gold, nickel gold, NiPdAu, stannum or coating antioxidant (OSP).
Step 2 13, plant ball
See Figure 23, metal pillar top implanted metal ball after completing step 2 12.
Embodiment 2, multi-turn single-chip upside-down mounting+passive device+static release ring
See Figure 25, the knot of sealing chip flipchip bump three-dimensional systematic metal circuit board embodiment 2 after first losing for the present invention
Structure schematic diagram, embodiment 2 is with the difference of embodiment 1: described pin 3 has multi-turn, between described pin 3 and pin 3
Bridge passive device 10 by conductive bond material, between described base island 2 and pin 3, be provided with static release ring 11, described
Passive device 10 can be connected across between pin 3 front and pin 3 front.
Embodiment 3, individual pen Duo Ji island tiling multi-chip inversion
See Figure 26, the knot of sealing chip flipchip bump three-dimensional systematic metal circuit board embodiment 3 after first losing for the present invention
Structure schematic diagram, embodiment 3 is with the difference of embodiment 1: pass through underfill 4 on described base island 2 and pin 3 front
Upside-down mounting has multiple chip 5.
Embodiment 4, individual pen stacked multichip fall formal dress
See Figure 27, the knot of sealing chip flipchip bump three-dimensional systematic metal circuit board embodiment 4 after first losing for the present invention
Structure schematic diagram, embodiment 4 is with the difference of embodiment 1: at described chip 5 back side by conduction or non-conductive adhesive
Matter 15 is provided with the second chip 12, is connected by metal wire 6 between described second chip 12 front and pin 3.
Embodiment 5, individual pen stacked multichip upside-down mounting
See Figure 28, the knot of sealing chip flipchip bump three-dimensional systematic metal circuit board embodiment 5 after first losing for the present invention
Structure schematic diagram, embodiment 5 is with the difference of embodiment 1: described pin 3 front is provided with the second conductive posts 13,
Described second conductive posts 13 there are the second chip 12, described second conductive posts 13 and second by conductive materials 14 upside-down mounting
Chip 12 is in the inside of plastic packaging material 8.
Embodiment 6, island-free single-chip upside-down mounting
See Figure 29, the knot of sealing chip flipchip bump three-dimensional systematic metal circuit board embodiment 6 after first losing for the present invention
Structure schematic diagram, embodiment 6 is with the difference of embodiment 1: described metallic circuit plate structure does not has base island 2, described chip 5
By underfill 4 upside-down mounting between pin 3 front and pin 3 front.
Embodiment 7, multilayer line single-chip upside-down mounting individual pen pin
See Figure 71, the knot of sealing chip flipchip bump three-dimensional systematic metal circuit board embodiment 7 after first losing for the present invention
Structure schematic diagram, embodiment 7 is with the difference of embodiment 1: described base island 2 or pin 3 include multiple layer metal line layer, phase
Being connected by conductive posts between adjacent double layer of metal line layer, described base island 2 and pin 3 back side are fallen by underfill 4
Equipped with chip 5, described pin 3 back side is provided with conductive posts 7, described conductive posts 7 top is provided with metal ball 16.
Its process is as follows:
Step one, take metal basal board
See Figure 30, take the suitable metal basal board of a piece of thickness, the purpose that this sheet material uses simply make for circuit and after
Continuous encapsulation supports the transitional material that line layer structure is used, and the material of this sheet material is mainly based on metal material, and golden
The material belonging to material can be the metallics that copper material iron material zinc-plated material stainless steel aluminium maybe can reach conducting function
Or nonmetallic substance etc..
Step 2, the micro-layers of copper of metallic substrate surfaces preplating
Seeing Figure 31, in the micro-layers of copper of metallic substrate surfaces preplating, micro-copper layer thickness, at 2 ~ 10 microns, needs according to function
Can also be thinning or thicken, primarily to enable line layer and metal basal board fluid-tight engagement, electricity when follow-up circuit makes
The mode of plating can use chemical deposition or electrolysis plating.
Step 3, patch photoresistance film operation
See Figure 32, stick respectively in the metal basal board front and the back side completing the micro-layers of copper of preplating and can be exposed development
Photoresistance film, to protect follow-up electroplated metal layer process operation, photoresistance film can be dry type photoresistance film can also be wet type photoresistance
Film.
Part photoresistance film is removed in step 4, metal basal board front
Seeing Figure 33, the metal basal board front utilizing exposure imaging equipment that step 3 completes to paste photoresistance film operation carries out figure
Shape exposes, develops and remove partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in metal basal board front carry out electroplating.
Step 5, electroplate the first metallic circuit layer
See Figure 34, in step 4, electroplate the first metal wire in the region of metal basal board front removal part photoresistance film
Road floor, the first metallic circuit layer material can be copper, aluminum, nickel, silver, gold, copper silver, nickel gold, NiPdAu (usual 5 ~ 20 microns, can
With according to different qualities conversion plating thickness) etc. material, other electrically conductive metallics can use certainly, not
The metal materials such as limitation copper, aluminum, nickel, silver, gold, copper silver, nickel gold, NiPdAu, plating mode can be chemical deposition or electrolysis
Plating mode.
Step 6, patch photoresistance film operation
Seeing Figure 35, in step 5, the photoresistance film that can be exposed development is sticked in metal basal board front, and photoresistance film is permissible
Be dry type photoresistance film can also be wet type photoresistance film.
Part photoresistance film is removed in step 7, metal basal board front
Seeing Figure 36, the metal basal board front utilizing exposure imaging equipment that step 6 completes to paste photoresistance film operation carries out figure
Shape exposes, develops and remove partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in metal basal board front carry out electroplating.
Step 8, electroplate the second metallic circuit layer
See Figure 37, in step 7, electroplate the second metal wire in the region of metal basal board front removal part photoresistance film
Road floor is as in order to connect the first metallic circuit floor and the conductive posts of the 3rd metallic circuit floor, and the material of metallic circuit layer can be adopted
By copper, nickel gold, NiPdAu, silver, gold or tin metal, plating mode can make chemical deposition or electrolysis plating mode.
Step 9, removal photoresistance film
See Figure 38, remove the photoresistance film of metallic substrate surfaces, it is therefore an objective to carry out non-conductive glued membrane operation for follow-up, remove
The method of photoresistance film can use chemical medicinal liquid to soften and use the mode of high pressure water washing to remove photoresistance film.
Step 10, pressing non-conductive glued membrane operation
See Figure 39, at one layer of non-conductive glued membrane of metal basal board front (having the region of line layer) pressing, it is therefore an objective to be
First metallic circuit layer and the 3rd metallic circuit layer insulate, and the mode of the non-conductive glued membrane of pressing can use the rolling of routine
Equipment, or in the environment of vacuum, carry out pressing, to prevent pressing process from producing the residual of air, non-conductive glued membrane is mainly
Thermosetting epoxy resin, and epoxy resin can could be used without filler according to product attribute or have the non-conductive glued membrane of filler,
The color of epoxy resin can carry out dyeing process according to product attribute.
Step 11, grind non-conductive film surface
See Figure 40, after completing non-conductive glued membrane pressing, carry out surface grinding, it is therefore an objective to the second metallic circuit will be exposed
Layer, maintains non-conductive glued membrane and the flatness of the second metallic circuit layer and controls the thickness of non-conductive glued membrane.
The metallization pretreatment of step 12, non-conductive film surface
See Figure 41, non-conductive film surface is carried out pretreatment of metallizing so that it is surface attachment last layer metallization height
Molecular material, it is therefore an objective to the catalyst conversion that can plate as subsequent metal material, adhesion metal macromolecular material is permissible
The row again such as spraying, plasma concussion, surface coarsening is used to dry；
Step 13, patch photoresistance film operation
Seeing Figure 42, in step 12, metal basal board front and back sticks the photoresistance film that can be exposed development, with
Protect the electroplating technology operation of the 3rd follow-up metallic circuit layer, photoresistance film can be dry type photoresistance film can also be wet type photoresistance
Film.
Part photoresistance film is removed in step 14, metal basal board front
Seeing Figure 43, the metal basal board front utilizing exposure imaging equipment that step 13 completes to paste photoresistance film operation is carried out
Graph exposure, develop with remove partial graphical photoresistance film, to expose the administrative division map that the follow-up needs in metal basal board front are etched
Shape.
Step 15, etching operation
See Figure 44, complete the region after photoresistance film is windowed in step 14 and be etched operation, its objective is to protect
Metallic region corrosion beyond the metallic circuit stayed is clean, and the method being etched can be copper chloride or iron chloride or can
To carry out the technology mode of the liquid medicine of chemical etching.
Photoresistance film is removed in step 10 six, metal basal board front
See Figure 45, remove the photoresistance film in metal basal board front, the metallic region being plated to expose follow-up needs to carry out
Figure.
Step 10 seven, plating the 3rd metallic circuit layer
See Figure 46, carry out the plating work of the 3rd metallic circuit layer, the 3rd gold medal in the metal basal board front of step 10 six
The material belonging to line layer can be copper, nickel gold, NiPdAu, silver, gold or tin metal, and plating mode can be that chemical deposition powers up
Electrolytic plating or whole thickness using chemical deposition mode to plate out needs.
Step 10 eight, patch photoresistance film operation
See Figure 47, stick the photoresistance film that can be exposed development in the metal basal board front of step 10 seven, it is therefore an objective to for
The making of subsequent metal line layer, photoresistance film can be dry type photoresistance film can also be wet type photoresistance film.
Part photoresistance film is removed in step 10 nine, metal basal board front
Seeing Figure 48, the metal basal board front utilizing exposure imaging equipment that step 10 eight completes to paste photoresistance film operation is carried out
Graph exposure, develop with remove partial graphical photoresistance film, to expose the administrative division map that the follow-up needs in metal basal board front carry out electroplating
Shape.
Step 2 ten, plating the 4th metallic circuit layer
See Figure 49, in step 10 nine, electroplate the 4th metal in the region of metal basal board front removal part photoresistance film
Line layer is as the conductive posts in order to connect the 3rd metallic circuit layer and fifth metal line layer, and the material of metallic circuit layer can
Using copper, nickel gold, NiPdAu, silver, gold or tin metal, plating mode can make chemical deposition or electrolysis plating mode.
Step 2 11, removal photoresistance film
See Figure 50, remove the photoresistance film of metallic substrate surfaces, it is therefore an objective to carry out non-conductive glued membrane operation for follow-up, remove
The method of photoresistance film can use chemical medicinal liquid to soften and use the mode of high pressure water washing to remove photoresistance film.
Step 2 12, pressing non-conductive glued membrane operation
See Figure 51, at one layer of non-conductive glued membrane of metal basal board front (having the region of line layer) pressing, it is therefore an objective to be
3rd metallic circuit layer insulate with fifth metal line layer, and the mode of the non-conductive glued membrane of pressing can use the rolling of routine
Equipment, or in the environment of vacuum, carry out pressing, to prevent pressing process from producing the residual of air, non-conductive glued membrane is mainly
Thermosetting epoxy resin, and epoxy resin can could be used without filler according to product attribute or have the non-conductive glued membrane of filler,
The color of epoxy resin can carry out dyeing process according to product attribute.
Step 2 13, grind non-conductive film surface
See Figure 52, after completing non-conductive glued membrane pressing, carry out surface grinding, it is therefore an objective to the 4th metallic circuit will be exposed
Layer, maintains non-conductive glued membrane and the flatness of the 4th metallic circuit layer and controls the thickness of non-conductive glued membrane.
The metallization pretreatment of step 2 14, non-conductive film surface
See Figure 53, non-conductive film surface is carried out pretreatment of metallizing so that it is surface attachment last layer metallization height
Molecular material, it is therefore an objective to the catalyst conversion that can plate as subsequent metal material, adhesion metal macromolecular material is permissible
The row again such as spraying, plasma concussion, surface coarsening is used to dry；
Step 2 15, patch photoresistance film operation
Seeing Figure 54, in step 2 14, metal basal board front and back sticks the photoresistance film that can be exposed development,
With the electroplating technology operation of the follow-up fifth metal line layer of protection, photoresistance film can be dry type photoresistance film can also be wet type light
Resistance film.
Part photoresistance film is removed in step 2 16, metal basal board front
Seeing Figure 55, the metal basal board front utilizing exposure imaging equipment that step 2 15 completes to paste photoresistance film operation is entered
Row graph exposure, develop with remove partial graphical photoresistance film, to expose the region that the follow-up needs in metal basal board front are etched
Figure.
Step 2 17, etching operation
Seeing Figure 56, complete the region after photoresistance film is windowed in step 2 16 and be etched operation, its objective is will
Metallic region corrosion beyond the metallic circuit retained is clean, the method being etched can be copper chloride or iron chloride or
The technology mode of the liquid medicine of chemical etching can be carried out.
Photoresistance film is removed in step 2 18, metal basal board front
See Figure 57, remove the photoresistance film in metal basal board front, the metallic region being plated to expose follow-up needs to carry out
Figure.
Step 2 19, plating fifth metal line layer
See Figure 58, carry out the plating work of fifth metal line layer in the metal basal board front of step 2 18, the 5th
Metallic circuit layer forms corresponding Ji Dao and pin after having electroplated the most on metallic substrates, and the material of fifth metal line layer can
To be copper, nickel gold, NiPdAu, silver, gold or tin metal, plating mode can be that chemical deposition powers up electrolytic plating or all makes
The thickness of needs is plated out by chemical deposition mode.
Step 3 ten, patch photoresistance film operation
Seeing Figure 59, in step 2 19, the photoresistance film that can be exposed development, photoresistance film are sticked in metal basal board front
Can be dry type photoresistance film can also be wet type photoresistance film.
Part photoresistance film is removed at step 3 11, the metal basal board back side
Seeing Figure 60, the metal basal board back side utilizing exposure imaging equipment that step 3 ten completes to paste photoresistance film operation is carried out
Graph exposure, develop with remove partial graphical photoresistance film, to expose the administrative division map that the follow-up needs in the metal basal board back side are etched
Shape.
Step 3 12, chemical etching
Seeing Figure 61, the region that the metal basal board back side in step 3 11 completes exposure imaging carries out chemical etching, changes
Till be etched through metallic circuit layer, etching solution can use copper chloride or iron chloride or can carry out chemical etching
Liquid medicine.
Step 3 13, patch photoresistance film operation
See Figure 62, step 3 12 completes the metal basal board back side of chemical etching and sticks and can be exposed development
Photoresistance film, photoresistance film can be dry type photoresistance film can also be wet type photoresistance film.
Part photoresistance film is removed at step 3 14, the metal basal board back side
Seeing Figure 63, the metal basal board back side utilizing exposure imaging equipment that step 3 13 completes to paste photoresistance film operation is entered
Row graph exposure, develop with remove partial graphical photoresistance film, to expose the region that the follow-up needs in the metal basal board back side carry out electroplating
Figure.
Step 3 15, plated metal pillar
See Figure 64, in step 3 14, electroplate metal column in the region of metal basal board back side removal part photoresistance film
Son, the material of metal pillar can be the materials such as copper, aluminum, nickel, silver, gold, copper silver, nickel gold, NiPdAu, and other is electrically conductive certainly
Metallics can use, do not limit to the metal materials such as copper, aluminum, nickel, silver, gold, copper silver, nickel gold, NiPdAu, plating side
Formula can make chemical deposition or electrolysis plating mode.
Step 3 16, removal photoresistance film
See Figure 65, remove the photoresistance film of metallic substrate surfaces, chemical medicinal liquid can be used to soften and use high pressure water jets to remove
Mode remove photoresistance film.
Step 3 17, load
See Figure 66, pass through underfill flip-chip at Ji Dao and the pin back side of step 3 16.
Step 3 18, encapsulating
Seeing Figure 67, use plastic packaging material to carry out plastic packaging at the metal basal board back side in step 3 17, plastic packaging mode is permissible
Using mould encapsulating mode, spraying equipment spraying method, use pad pasting mode or the mode of brush coating, described plastic packaging material can use
There are packing material or the epoxy resin of no-arbitrary pricing material.
Step 3 19, epoxy resin surface grind
See Figure 68, after completing the epoxy resin plastic packaging of step 4 ten, carry out epoxy resin surface grinding, it is therefore an objective to make
Metal pillar exposes plastic-sealed body surface and controls the thickness of epoxy resin.
Step 4 ten, plating anti-oxidant metal layer or coating antioxidant (OSP)
Seeing Figure 69, the exposed metal of metallic substrate surfaces after completing step 4 11 carries out electroplating antioxidation
Metal level, prevents burning, such as gold, nickel gold, NiPdAu, stannum or coating antioxidant (OSP).
Step 4 11, plant ball
See Figure 70, the metal pillar top implanted metal ball after completing step 4 ten.
Claims (3)
1. a process for sealing chip flipchip bump three-dimensional systematic metal circuit board after first erosion, described method includes as follows
Step:
Step one, take metal basal board
Step 2, the micro-layers of copper of metallic substrate surfaces preplating
Step 3, patch photoresistance film operation
The photoresistance film that can be exposed development is sticked respectively in the metal basal board front and the back side completing the micro-layers of copper of preplating；
Part photoresistance film is removed at step 4, the metal basal board back side
Utilize exposure imaging equipment step 3 is completed paste photoresistance film operation the metal basal board back side carry out graph exposure, development with
Remove partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in the metal basal board back side carry out electroplating；
Step 5, plated metal line layer
Metallic circuit layer is electroplated in the region of metal basal board back side removal part photoresistance film in step 4；
Step 6, patch photoresistance film operation
In step 5, the photoresistance film that can be exposed development is sticked at the metal basal board back side；
Part photoresistance film is removed at step 7, the metal basal board back side
Utilize exposure imaging equipment step 6 is completed paste photoresistance film operation the metal basal board back side carry out graph exposure, development with
Remove partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in the metal basal board back side carry out electroplating；
Step 8, electroplated conductive metal line layer
Conductive metal lines layer is electroplated in the region of metal basal board back side removal part photoresistance film in step 7；
Step 9, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces；
Step 10, epoxy resin plastic packaging
Epoxide resin material is utilized to carry out plastic packaging protection on the metallic circuit layer surface at the metal basal board back side；
Step 11, epoxy resin surface grind
Epoxy resin surface grinding is carried out after completing epoxy resin plastic packaging；
Step 12, patch photoresistance film operation
The photoresistance film that can be exposed development is sticked at the metal basal board front and back completing step 11；
Part photoresistance film is removed in step 13, metal basal board front
The metal basal board front utilizing exposure imaging equipment that step 12 completes to paste photoresistance film operation carries out graph exposure, development
With remove partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in metal basal board front are etched；
Step 14, chemical etching
The region that metal basal board front in step 13 completes exposure imaging is carried out chemical etching；
Step 15, patch photoresistance film operation
The photoresistance film that can be exposed development is sticked at the metal basal board front and back completing step 14；
Part photoresistance film is removed in step 10 six, metal basal board front
The metal basal board front utilizing exposure imaging equipment that step 15 completes to paste photoresistance film operation carries out graph exposure, development
With remove partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in metal basal board front carry out electroplating；
Step 10 seven, plated metal pillar
Metal pillar is electroplated in the region of metal basal board front removal part photoresistance film in step 10 six；
Step 10 eight, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces；
Step 10 nine, load
By underfill flip-chip on the Ji Dao completing step 10 eight and pin；
Step 2 ten, encapsulating
Plastic packaging material is used to carry out plastic packaging in the metal basal board front in step 10 nine；
Step 2 11, epoxy resin surface grind
Epoxy resin surface grinding is carried out after completing the epoxy resin plastic packaging of step 2 ten；
Step 2 12, coating antioxidant
The exposed metal of metallic substrate surfaces after completing step 2 11 carries out coating antioxidant；
Step 2 13, plant ball
Metal pillar top implanted metal ball after completing step 2 12.
2. the process of sealing chip flipchip bump three-dimensional systematic metal circuit board after a first erosion, it is characterised in that described side
Method comprises the steps:
Step one, take metal basal board
Step 2, the micro-layers of copper of metallic substrate surfaces preplating
Step 3, patch photoresistance film operation
The photoresistance film that can be exposed development is sticked respectively in the metal basal board front and the back side completing the micro-layers of copper of preplating；
Part photoresistance film is removed in step 4, metal basal board front
Utilize exposure imaging equipment step 3 is completed paste photoresistance film operation metal basal board front carry out graph exposure, development with
Remove partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in metal basal board front carry out electroplating；
Step 5, electroplate the first metallic circuit layer
The first metallic circuit layer is electroplated in the region of metal basal board front removal part photoresistance film in step 4；
Step 6, patch photoresistance film operation
In step 5, the photoresistance film that can be exposed development is sticked in metal basal board front；
Part photoresistance film is removed in step 7, metal basal board front
Utilize exposure imaging equipment step 6 is completed paste photoresistance film operation metal basal board front carry out graph exposure, development with
Remove partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in metal basal board front carry out electroplating；
Step 8, electroplate the second metallic circuit layer
In step 7 metal basal board front remove part photoresistance film region in plating on the second metallic circuit layer as in order to
Connect the first metallic circuit layer and the conductive posts of the 3rd metallic circuit layer；
Step 9, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces；
Step 10, pressing non-conductive glued membrane operation
At one layer of non-conductive glued membrane of metal basal board front pressing；
Step 11, grind non-conductive film surface
Surface grinding is carried out after completing non-conductive glued membrane pressing；
The metallization pretreatment of step 12, non-conductive film surface
Non-conductive film surface is carried out pretreatment of metallizing；
Step 13, patch photoresistance film operation
In step 12, metal basal board front and back sticks the photoresistance film that can be exposed development；
Part photoresistance film is removed in step 14, metal basal board front
The metal basal board front utilizing exposure imaging equipment that step 13 completes to paste photoresistance film operation carries out graph exposure, development
With remove partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in metal basal board front are etched；
Step 15, etching operation
Complete the region after photoresistance film is windowed in step 14 and be etched operation；
Photoresistance film is removed in step 10 six, metal basal board front
Remove the photoresistance film in metal basal board front, the metallic region figure being plated to expose follow-up needs to carry out；
Step 10 seven, plating the 3rd metallic circuit layer
The plating work of the 3rd metallic circuit layer is carried out in the metal basal board front of step 10 six；
Step 10 eight, patch photoresistance film operation
The photoresistance film that can be exposed development is sticked in the metal basal board front of step 10 seven；
Part photoresistance film is removed in step 10 nine, metal basal board front
The metal basal board front utilizing exposure imaging equipment that step 10 eight completes to paste photoresistance film operation carries out graph exposure, development
With remove partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in metal basal board front carry out electroplating；
Step 2 ten, plating the 4th metallic circuit layer
The 4th metallic circuit layer is electroplated as use in the region of metal basal board front removal part photoresistance film in step 10 nine
To connect the conductive posts of the 3rd metallic circuit layer and fifth metal line layer；
Step 2 11, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces；
Step 2 12, pressing non-conductive glued membrane operation
At one layer of non-conductive glued membrane of metal basal board front pressing；
Step 2 13, grind non-conductive film surface
Surface grinding is carried out after completing non-conductive glued membrane pressing；
The metallization pretreatment of step 2 14, non-conductive film surface
Non-conductive film surface is carried out pretreatment of metallizing；
Step 2 15, patch photoresistance film operation
In step 2 14, metal basal board front and back sticks the photoresistance film that can be exposed development；
Part photoresistance film is removed in step 2 16, metal basal board front
The metal basal board front utilizing exposure imaging equipment that step 2 15 completes to paste photoresistance film operation carries out graph exposure, shows
Shadow and removal partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in metal basal board front are etched；
Step 2 17, etching operation
Complete the region after photoresistance film is windowed in step 2 16 and be etched operation；
Photoresistance film is removed in step 2 18, metal basal board front
Remove the photoresistance film in metal basal board front；
Step 2 19, plating fifth metal line layer
Carry out the plating work of fifth metal line layer in the metal basal board front of step 2 18, fifth metal line layer is electroplated
Corresponding Ji Dao and pin is formed the most on metallic substrates after completing；
Step 3 ten, patch photoresistance film operation
In step 2 19, the photoresistance film that can be exposed development is sticked in metal basal board front；
Part photoresistance film is removed at step 3 11, the metal basal board back side
The metal basal board back side utilizing exposure imaging equipment that step 3 ten completes to paste photoresistance film operation carries out graph exposure, development
With remove partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in the metal basal board back side are etched；
Step 3 12, chemical etching
The region that the metal basal board back side in step 3 11 completes exposure imaging is carried out chemical etching, and chemical etching is until metal
Till line layer；
Step 3 13, patch photoresistance film operation
The photoresistance film that can be exposed development is sticked at the metal basal board back side completing chemical etching in step 3 12；
Part photoresistance film is removed at step 3 14, the metal basal board back side
The metal basal board back side utilizing exposure imaging equipment that step 3 13 completes to paste photoresistance film operation carries out graph exposure, shows
Shadow and removal partial graphical photoresistance film, to expose the regional graphics that the follow-up needs in the metal basal board back side carry out electroplating；
Step 3 15, plated metal pillar
Metal pillar is electroplated in the region of metal basal board back side removal part photoresistance film in step 3 14；
Step 3 16, removal photoresistance film
Remove the photoresistance film of metallic substrate surfaces；
Step 3 17, load
Complete Ji Dao and the pin back side flip-chip of step 3 16；
Step 3 18, encapsulating
Plastic packaging material is used to carry out plastic packaging at the metal basal board back side in step 3 17；
Step 3 19, epoxy resin surface grind
Epoxy resin surface grinding is carried out after completing the epoxy resin plastic packaging of step 3 18；
Step 4 ten, coating antioxidant
The exposed metal of metallic substrate surfaces after completing step 3 19 carries out coating antioxidant；
Step 4 11, plant ball
Metal pillar top implanted metal ball after completing step 4 ten.
The technique side of sealing chip flipchip bump three-dimensional systematic metal circuit board after a kind of first erosion the most according to claim 2
Method, it is characterised in that described step 6 to the repeatable operation of step 10 seven, forms the metallic circuit layer of more layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310339207.7A CN103400767B (en) | 2013-08-06 | 2013-08-06 | First sealing chip flipchip bump three-dimensional systematic metal circuit board and process after erosion |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310339207.7A CN103400767B (en) | 2013-08-06 | 2013-08-06 | First sealing chip flipchip bump three-dimensional systematic metal circuit board and process after erosion |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103400767A CN103400767A (en) | 2013-11-20 |
| CN103400767B true CN103400767B (en) | 2016-08-17 |
Family
ID=49564367
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310339207.7A Active CN103400767B (en) | 2013-08-06 | 2013-08-06 | First sealing chip flipchip bump three-dimensional systematic metal circuit board and process after erosion |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103400767B (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681581B (en) * | 2013-12-05 | 2016-04-27 | 江苏长电科技股份有限公司 | Once after first erosion, plating frame subtraction buries the flat leg structure of flip-chip and process |
| CN103646936B (en) * | 2013-12-05 | 2016-06-01 | 江苏长电科技股份有限公司 | First plate for two times and lose metal frame subtraction afterwards and bury the flat leg structure of flip-chip and processing method |
| CN103646935B (en) * | 2013-12-05 | 2016-06-01 | 江苏长电科技股份有限公司 | First plate for two times and lose metal frame subtraction afterwards and bury flip-chip bump structure and processing method |
| CN103681580B (en) * | 2013-12-05 | 2016-07-06 | 江苏长电科技股份有限公司 | Etching-prior-to-plametal metal frame subtraction imbedded chip flipchip bump structure and process |
| CN103646933B (en) * | 2013-12-05 | 2016-03-30 | 江苏长电科技股份有限公司 | Secondary etching-prior-to-plametal metal frame subtraction buries chip formal dress bump structure and process |
| CN103681583B (en) * | 2013-12-05 | 2016-04-27 | 江苏长电科技股份有限公司 | Once after first erosion, plating frame subtraction buries the flat leg structure of chip formal dress and process |
| CN103646929B (en) * | 2013-12-05 | 2016-06-01 | 江苏长电科技股份有限公司 | Once first plate and lose metal frame subtraction afterwards and bury chip and just filling flat leg structure and processing method |
| CN104465586B (en) * | 2014-12-26 | 2018-07-10 | 江苏长电科技股份有限公司 | A kind of wafer-level package structure and its process |
| CN105848416B (en) * | 2016-03-31 | 2019-04-26 | 华为技术有限公司 | A kind of substrate and mobile terminal |
| CN107919333B (en) * | 2017-12-28 | 2023-08-29 | 江阴长电先进封装有限公司 | Three-dimensional POP packaging structure and packaging method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101958301A (en) * | 2010-09-04 | 2011-01-26 | 江苏长电科技股份有限公司 | Double-side graph chip direct-put single package structure and package method thereof |
| CN102456677A (en) * | 2010-10-27 | 2012-05-16 | 三星半导体(中国)研究开发有限公司 | Packaging structure for ball grid array and manufacturing method for same |
| CN102723293A (en) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | Etching-first and packaging-later manufacturing method for chip inversion single-surface three-dimensional circuit and packaging structure of chip formal double-surface three-dimensional circuit |
| CN102723282A (en) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | Etching-first and packaging-later manufacturing method for chip formal double-surface three-dimensional circuit and packaging structure of chip formal double-surface three-dimensional circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101346420B1 (en) * | 2011-12-29 | 2014-01-10 | 주식회사 네패스 | Stacked semiconductor package and method of manufacturing the same |
-
2013
- 2013-08-06 CN CN201310339207.7A patent/CN103400767B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101958301A (en) * | 2010-09-04 | 2011-01-26 | 江苏长电科技股份有限公司 | Double-side graph chip direct-put single package structure and package method thereof |
| CN102456677A (en) * | 2010-10-27 | 2012-05-16 | 三星半导体(中国)研究开发有限公司 | Packaging structure for ball grid array and manufacturing method for same |
| CN102723293A (en) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | Etching-first and packaging-later manufacturing method for chip inversion single-surface three-dimensional circuit and packaging structure of chip formal double-surface three-dimensional circuit |
| CN102723282A (en) * | 2012-06-09 | 2012-10-10 | 江苏长电科技股份有限公司 | Etching-first and packaging-later manufacturing method for chip formal double-surface three-dimensional circuit and packaging structure of chip formal double-surface three-dimensional circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103400767A (en) | 2013-11-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103413766B (en) | First sealing chip formal dress three-dimensional systematic metallic circuit plate structure and process after erosion | |
| CN103400767B (en) | First sealing chip flipchip bump three-dimensional systematic metal circuit board and process after erosion | |
| CN103400771B (en) | First sealing chip upside-down mounting three-dimensional systematic metal circuit board structure and process after erosion | |
| CN103390563B (en) | Erosion flip-chip of being first honored as a queen three-dimensional systematic metal circuit board structure &processes method | |
| CN103400772B (en) | First it is honored as a queen and loses chip formal dress three-dimensional systematic metallic circuit plate structure and process | |
| CN103400773B (en) | First it is honored as a queen and loses passive device three-dimensional systematic metal circuit board structure and process | |
| CN103400778B (en) | First lose and seal passive device three-dimensional systematic metal circuit board structure &processes method afterwards | |
| CN103400770B (en) | First be honored as a queen and lose flip-chip salient point three-dimensional systematic metal circuit board and process | |
| CN103400777B (en) | First sealing chip formal dress salient point three-dimensional systematic metal circuit board and process after erosion | |
| CN103400775B (en) | First it is honored as a queen and loses three-dimensional systematic flip-chip bump packaging structure and process | |
| CN103400769B (en) | First lose and seal three-dimensional systematic flip-chip bump packaging structure and process afterwards | |
| CN103400774B (en) | First be honored as a queen and lose chip formal dress salient point three-dimensional systematic metal circuit board and process | |
| CN103400776B (en) | First lose and seal three-dimensional systematic flip chip encapsulation structure and process afterwards | |
| CN102856291B (en) | First etched and then packaged packaging structure with multiple chips normally installed and without base islands as well as preparation method thereof | |
| CN102723292B (en) | Flip chip double-faced three-dimensional circuit manufacture method by encapsulation prior to etching and flip chip double-faced three-dimensional circuit encapsulation structure | |
| CN102867791A (en) | Multi-chip reversely-arranged etched-encapsulated base island-buried encapsulating structure and manufacturing method thereof | |
| CN102856290A (en) | First etched and then packaged packaging structure with single chip reversedly installed and base islands buried as well as preparation method thereof | |
| CN102856293B (en) | First etched and then packaged packaging structure with single chip normally installed and without base islands as well as preparation method thereof | |
| CN102856286B (en) | First packaged and then etched packaging structure with single chip normally installed and without base islands and preparation method of structure | |
| CN102881671B (en) | Single-chip front-mounted etching-first package-followed island-exposed package structure and manufacturing method thereof | |
| CN103390567B (en) | First lose and seal three-dimensional systematic chip formal dress bump packaging structure and process afterwards | |
| CN102867802A (en) | Multi-chip reversely-arranged etched-encapsulated base island-exposed encapsulating structure and manufacturing method thereof | |
| CN102856271B (en) | Multi-chip flip, packaging-after-etching and non-pad packaging structure and manufacturing method thereof | |
| CN102856269B (en) | Single-chip flip, etching-after-packaging and pad exposed packaging structure and manufacturing method thereof | |
| CN102856284A (en) | Multi-chip flip, etching-after-packaging and pad exposed packaging structure and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20160429 Address after: 214434 Jiangyin, Jiangsu, Chengjiang city street, Long Hill Road, No. 78 Applicant after: Jiangsu Changjiang Electronics Technology Co., Ltd. Address before: 214434 Jiangyin, Jiangsu Province, the development of mountain road, No. 78, No. Applicant before: Jiangsu Changjiang Electronics Technology Co., Ltd. |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |