CN105514099A - Multiple-layer stacked fan-out type packaging structure and preparation method thereof - Google Patents
Multiple-layer stacked fan-out type packaging structure and preparation method thereof Download PDFInfo
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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Abstract
The invention relates to a multiple-layer stacked fan-out type packaging structure and a preparation method thereof. The preparation method includes the following steps of: (1) preparing a first seed layer on a bearing sheet through a temporary bonding film, and forming metal columns; (2) pasting a chip on the first seed layer, and covering the chip with a first insulation resin; (3) thinning and grinding the first insulation resin, exposing the metal columns and metal embosses; (4) preparing a second insulation resin on the surface of the first insulation resin and exposing the metal columns and the metal embosses; preparing a second seed layer on the surface of the second insulation resin surface, and forming a conducting circuit; (5) removing photoresist and the exposed second seed layer, coating the surface of the second insulation resin with a third insulation resin, and forming opening patterns of solder balls; (6) removing the bearing sheet, the temporary bonding film, and the first seed layer; (7) preparing the solder balls, covering the chip back side with a fourth insulation resin, and exposing an electric conductive column; and (8) obtaining a three-dimensional packaging structure through a stack process. According to the invention, the process steps are reduced, the preparation process is simple, and the cost is reduced.
Description
Technical field
The present invention relates to a kind of multiple-level stack fan-out package structure and preparation method thereof, belong to technical field of semiconductor encapsulation.
Background technology
Along with electronic product multifunction and miniaturized trend, high density microelectronic mounting technology becomes main flow gradually on electronic product of new generation.In order to coordinate the development of electronic product of new generation, the especially development of smart mobile phone, palmtop PC, the product such as super, the future developments such as the size of chip is higher to density, speed is faster, size is less, cost is lower.The appearance of fan-out square chip level package technology (FanoutPanelLevelPackage, FOPLP), as the upgrade technique of fan-out-type Wafer level packaging (FanoutWaferLevelPackage, FOWLP), has more vast potential for future development.
The develop rapidly of the science and technology such as smart mobile phone, intelligence wearing, Internet of Things, human body chip, leads chip encapsulation technology towards trend developments such as miniaturization, densification, three dimensional stresses.Height degree three-dimension packaging chip technology becomes the hot technology of chip package.
As shown in Figure 1, disclosed in the patent application US2015206866A1 of Taiwan Semiconductor Manufacturing Co., structure 100a is for comprising logic chip 112a, conductive posts 108a, the fan-out package chip of packing material 114a.Structure 300a is the packaged chip containing memory chip.Structure 100a and structure 300a is by PoP(PackageonPackage) mode be packaged together.Structure 100a is first at Carrier(carrying tablet) upper formation conductive posts 108a, then pasting chip 112a, potting resin 114a between conductive posts 108a and chip 112a.Conductive posts 108a, chip 112a, resin 114a three are roughly in one plane.And then do the structures such as conducting wire.Finally, by the mode of attachment, structure 300a is mounted on structure 100a.
As shown in Figure 2, disclosed in the patent application CN104538375A of Hua Tian, structure 50b is fan-out package chip structure, and 60b is WireBonding(wire bonding) chip structure.The manufacture method of 50b part makes electric conductor 2b, then chip placement 3b for using etching, electric plating method, and the front of chip 3b is concordant with the upper surface of electric conductor, makes the structures such as RDL at chip 3b upper surface.The methods such as the use of chip lower surface polishes are exposed.Surface makes UBM(UnderBumpMetal under the die) structure, and at lower surface pasting chip 60b.
Multilayer of the prior art is cut stacking fan-out-type removing from mould encapsulating structure and mostly be there is following defect: the production method of conductive pole or electric conductor is comparatively complicated, need to ensure conductive pole, chip and resin etc. in one plane, implement and comparatively bother, technique become more meticulous require higher.
Summary of the invention
The object of this part is some aspects of general introduction embodiments of the invention and briefly introduces some preferred embodiments.May do in the specification digest and denomination of invention of this part and the application a little simplify or omit with avoid making this part, specification digest and denomination of invention object fuzzy, and this simplification or omit and can not be used for limiting the scope of the invention.
In view of in above-mentioned and/or existing semiconductor packages, the multiple-level stack fan-out package structure of Problems existing is comparatively complicated, and preparation technology becomes more meticulous and requires more high defect, proposes the present invention.
The object of the invention is to overcome the deficiencies in the prior art, provide a kind of multiple-level stack fan-out package structure and preparation method thereof, decrease processing step, manufacture craft is simple, reduces costs.
According to technical scheme provided by the invention, the preparation method of described multiple-level stack fan-out package structure, comprises the following steps:
(1) carrying tablet is as base material, the interim bonding film of carrying tablet surface coverage;
(2) form the first sublayer at interim bonding film surface, adopt graphic plating or chemical plating process to form the metal column of requirement in the first sub-layer surface;
(3) wafer frontside makes metal salient point, and Heraeus is posted at the back side, forms one single chip by scribing;
(4) be attached on the first sublayer by the Heraeus of chip one side, chip adopts the first insulating resin to cover, and the first sublayer, metal column and chip wrap by the first insulating resin;
(5) polish thinning for the first insulating resin, expose metal column and metal salient point, metal column, metal salient point and the first insulating resin are positioned at same surface;
(6) form the second insulating resin on the first insulating resin surface, the second insulating resin forms resin opening by photoetching process, and metal column and metal salient point expose by resin opening; Form the second sublayer on the second insulating resin surface, the second sublayer covers the surface of the second insulating resin, metal column and metal salient point; Then at the second sub-layer surface resist coating, make the second sublayer, opening exposed portion on a photoresist by photoetching process, form the opening figure of conducting wire, in making conducting wire, opening figure place;
(7) photoresist and the second sublayer of exposing is removed, at conducting wire and the second insulating resin surface-coated the 3rd insulating resin, on the 3rd insulating resin, making opening by photoetching process, conducting wire, exposed portion, forming the opening figure for making soldered ball;
(8) remove carrying tablet, interim bonding film and the first sublayer, expose metal column;
(9) soldered ball is made at the soldered ball opening figure place of the 3rd insulating resin; Then cover the 4th insulating resin at chip back and the first insulating resin back side, the 4th insulating resin forms opening through photoetching process, exposes conductive pole;
(10) encapsulating structure that packaging body and step (9) obtain is carried out stacking, form three-dimension packaging structure.
Further, described step (8) can also adopt following technique: remove carrying tablet and interim bonding film, expose the first sublayer; Retain the first sublayer on metal column surface.
Further, the encapsulating structure that described step (10) described packaging body is obtained by mode and the step (9) of soldered ball or routing carries out stacking.
Further, described carrying tablet is the lamellar body that silicon, silicon dioxide, pottery, glass, metal, alloy or organic material are made, or for the board device with temperature control can be heated.
Further, described interim bonding film is thermoplastic or heat curing-type organic material, or the inorganic material containing Cu, Ni, Cr or Co.
Described multiple-level stack fan-out package structure, comprises the first packaging body and the second packaging body that stack gradually; Its feature: described first packaging body comprises the chip that front has metal salient point, Heraeus is posted at the back side, chip is wrapped in the first insulating resin, metal column is provided with in the first insulating resin, the two ends of metal column are concordant with the front and back of the first insulating resin respectively, and the metal salient point of chip front side is concordant with the front of the first insulating resin; Cover the 4th insulating resin at the back side of described first insulating resin, the 4th insulating resin is provided with the opening exposing metal column, and the first packaging body and the second packaging body realize electrical connection by the metal column of the 4th insulating resin opening part; Be provided with the second insulating resin, Seed Layer, conducting wire and the 3rd insulating resin in the front of described first insulating resin successively, the 3rd insulating resin be provided with the opening of soldered ball, arrange soldered ball at opening part, conducting wire connects soldered ball and metal column.
Further, described second packaging body is chip with encapsulating structure or bare chip.
Further, described second packaging body is flip-chip or lead-bonding chip.
Further, described metal column is one or more metal or alloy in gold, silver, copper, tin, titanium, nickel, magnesium, bismuth, palladium, nickel, chromium, iron, indium; Described metal column (104) is for spherical, cylindrical or conical.
Further, described metal salient point is metal material, and the mode laser sintered by plating, chemical plating, evaporation, sputtering, printing, routing makes.
The present invention has the following advantages:
(1) metal column production method and mode of exposing simple, metal column can use plants the technique such as ball, printing and makes, and once can form several ten thousand to millions of metal columns, manufacture craft and cost of manufacture all can significantly reduce; The mode of exposing of metal column use polishing thinning etc. mode is exposed, once expose whole metal column, manufacture craft and cost of manufacture all can significantly reduce.
(2) chip front side makes metal salient point, and chip attachment, front plastic packaging expose metal column and metal salient point after polishing, and metal column and metal salient point are at same plane and easily realize, for the making that becomes more meticulous of conducting wire below provides precondition.
(3) in three-dimensional stacking structure, both can use WireBonding chip, also can use flip-chip, flexible configuration.
(4) eliminate base plate for packaging in technique, be conducive to the minimizing of processing step and the reduction of cost.
(5) structure is simple, reduces owing to eliminating base plate for packaging product structure complexity.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 is the structural representation of Taiwan Semiconductor Manufacturing Co.'s patent application in prior art.
Fig. 2 is the structural representation of prior art China sky patent application.
Fig. 3-1 ~ Fig. 3-11 is the schematic diagram of embodiment one preparation process.Wherein:
Fig. 3-1 is the schematic diagram covering interim bonding film on carrying tablet.
Fig. 3-2 is the schematic diagram making the first sublayer and metal column.
Fig. 3-3 is the schematic diagram of the one single chip making metal salient point and Heraeus.
Fig. 3-4 is the schematic diagram of employing first insulating resin parcel chip, the first sublayer and metal column.
Fig. 3-5 is the schematic diagram of thinning first insulating resin.
Fig. 3-6 is the schematic diagram of making second insulating barrier, the second sublayer and conducting wire.
Fig. 3-7 is the schematic diagram of making the 3rd insulating barrier and soldered ball opening figure.
Fig. 3-8 is the schematic diagram removing carrying tablet, temporarily bonding film and the first sublayer.
Fig. 3-9 is the schematic diagram making soldered ball and the 4th insulating resin.
Fig. 3-10 is the schematic diagram being formed three-dimension packaging structure by back-off mode.
Fig. 3-11 is the schematic diagram being formed three-dimension packaging structure by wire bonding mode.
Fig. 4 is the schematic diagram after removing carrying tablet and interim bonding film in embodiment two.
Embodiment
In order to enable above-mentioned purpose of the present invention, feature and advantage become apparent more, are further described the specific embodiment of the present invention below in conjunction with concrete accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here carrys out embodiment, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space that should comprise length, width and the degree of depth in making is being implemented.
Embodiment one: a kind of preparation method of multiple-level stack fan-out package structure, comprises the following steps:
(1) carrying tablet 101 is as base material, uses the modes such as roll extrusion, spin coating, spraying, printing, non-rotating coating, hot pressing, vacuum pressing-combining, immersion, pressure laminating at the interim bonding film 102 of carrying tablet 101 surface coverage; Obtain structure as shown in figure 3-1.
The material of described carrying tablet 101 can be the square piece of the compositions such as silicon, silicon dioxide, pottery, glass, metal, alloy, organic material, disk or irregular, also can be can carry out heating and the board device of temperature control.
Described interim bonding film 102 is thermoplastic or heat curing-type organic material, also can be the inorganic material containing compositions such as Cu, Ni, Cr, Co; Described interim bonding film 102 can be removed by heating, machinery, chemistry, laser, the mode such as freezing.
(2) form the first sublayer 103 on interim bonding film 102 surface, use the method such as graphic plating, chemical plating to form metal column 104 on the first surface, sublayer 103; Obtain structure as shown in figure 3-2.
The first sublayer 103 described is metal or alloy material; The first sublayer 103 can be deposited on interim bonding film 102 by methods such as plating, chemical plating, evaporation, sputtering, coating, pressings.
Described metal column 104 is metal material, one or more metals or its alloys such as such as gold, silver, copper, tin, titanium, nickel, magnesium, bismuth, palladium, nickel, chromium, iron, indium; Described metal column 104 can be spherical, also can be cylindrical, conical or other three-dimensional shapes.
(3) wafer frontside that wafer factory produces makes metal salient point 105, and Heraeus 106 is posted at the back side, forms one single chip 107, as shown in Fig. 3-3 by scribing.
Described metal salient point 105 is metal material, can be made by plating, chemical plating, evaporation, sputtering, printing, routing, the mode such as laser sintered.
Described Heraeus 106 is organic material.
(4) be attached on the first sublayer 103 by the Heraeus 106 of chip 107 one side, chip 107 adopts the first insulating resin 108 to cover, and the first sublayer 103, metal column 104 and chip 107 wrap by the first insulating resin 108; Obtain structure as shown in Figure 3-4.
Described first insulating resin 108 is organic material or contains Packed organic material.
(5) polish thinning for the first insulating resin 108, expose metal column 104 and metal salient point 105, as in Figure 3-5; Described metal column 104, metal salient point 105 and the first insulating resin 108 are positioned at same surface;
The described thinning method polished comprises that machinery polishes, chemistry polishes, plasma etching etc.
(6) form the second insulating resin 109, second insulating resin 109 on the first insulating resin 108 surface and form resin opening 110 by the method for photoetching, metal column 104 and metal salient point 105 expose by resin opening 110; Form the second sublayer 103-1 on the second insulating resin 109 surface again, the second sublayer 103-1 covers the surface of the second insulating resin 109, metal column 103 and metal salient point 105.
Then at the second sublayer 103-1 surface resist coating 111, on photoresist 111, make the second sublayer, opening exposed portion 103-1 by the method for photoetching, form the opening figure of conducting wire 112; On the second sublayer 103-1 at opening figure place, conducting wire 112 is formed by methods such as plating, chemical platings; Obtain structure as seen in figures 3-6.
Described second insulating resin 109 is organic material, comprise photosensitive resin and the resin that can be formed figure by techniques such as dry etchings, such as polyimides, photosensitive type epoxy resin, solder mask, green paint, dry film, photosensitive type increase layer material, the two benzocyclobutene resin of BCB() or PBO(phenyl benzo dioxazole resin).
Described second insulating resin 109 can be made by modes such as roll extrusion, spin coating, spraying, printing, non-rotating coating, hot pressing, vacuum pressing-combining, immersion, pressure laminatings.
The thickness of described second insulating resin 109 is 3 ~ 50 μm.The thickness of described the second sublayer 103-1 is 0.2 ~ 18 μm.The thickness of described conducting wire 112 is 0.2 ~ 18 μm.
Described conducting wire 112 is metal material.
(7) photoresist 111 and the second sublayer 103-1 exposed is removed, at conducting wire 112 and the second insulating resin 109 surface-coated the 3rd insulating resin 113, opening is made on the 3rd insulating resin 113 surface by the method for photoetching, conducting wire, exposed portion 112, forms the opening figure for making soldered ball; As shown in fig. 3 to 7.
Described 3rd insulating resin 113 is organic material, can be identical or different with the second insulating resin 109.Described 3rd insulating resin 113 is comprised photosensitive resin and can be formed the resin of figure by techniques such as dry etchings, and such as polyimides, photosensitive type epoxy resin, solder mask, green paint, dry film, photosensitive type increase layer material, the two benzocyclobutene resin of BCB() or PBO(phenyl benzo dioxazole resin).
Described 3rd insulating resin 113 can be made by modes such as roll extrusion, spin coating, spraying, printing, non-rotating coating, hot pressing, vacuum pressing-combining, immersion, pressure laminatings.
(8) remove carrying tablet 101, interim bonding film 102 and the first sublayer 103, expose metal column 104, as shown in figures 3-8.
(9) soldered ball 114 is made at the soldered ball opening figure place of the 3rd insulating resin 113; Then cover the 4th insulating resin 115 at chip 107 back side and first insulating resin 108 back side, the 4th insulating resin 115 forms opening through photoetching process, exposes conductive pole 104; Obtain structure as shown in figs. 3-9.
Described soldered ball 114 is metal material.
Described 4th insulating resin 115 is organic material, can with the first insulating resin 108 and the second insulating resin 109 identical or different.
Described 4th insulating resin 115 can be made by modes such as roll extrusion, spin coating, spraying, printing, non-rotating coating, hot pressing, vacuum pressing-combining, immersion, pressure laminatings.
(10) encapsulating structure flip-chip 201 and step (9) obtained is stacking in the mode of back-off by soldered ball, forms three-dimension packaging structure, as shown in figs. 3-10; Or encapsulating structure lead-bonding chip 202 and step (9) obtained is stacking by the mode of routing, form three-dimension packaging structure, as shown in Fig. 3-11.
Embodiment two: a kind of preparation method of multiple-level stack fan-out package structure, comprises the following steps:
Step (1) ~ step (7) is identical with embodiment one.
Step (8) removes carrying tablet 101 and interim bonding film 102, exposes the first sublayer 103; Retain the first sublayer 103 on metal column 104 surface, as shown in Figure 4.
Step (9) ~ step (10) is identical with embodiment one.
It should be noted that, above embodiment is only in order to illustrate technical scheme of the present invention and unrestricted, although with reference to preferred embodiment to invention has been detailed description, those of ordinary skill in the art is to be understood that, can modify to technical scheme of the present invention or equivalent replacement, and not departing from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of right of the present invention.
Claims (10)
1. a preparation method for multiple-level stack fan-out package structure, its feature, comprises the following steps:
(1) carrying tablet (101) is as base material, the interim bonding film (102) of carrying tablet (101) surface coverage;
(2) form the first sublayer (103) on interim bonding film (102) surface, adopt graphic plating or chemical plating process to form the metal column (104) of requirement on the first sublayer (103) surface;
(3) wafer frontside makes metal salient point (105), and Heraeus (106) is posted at the back side, forms one single chip (107) by scribing;
(4) Heraeus (106) of chip (107) one side is attached on the first sublayer (103), chip (107) adopts the first insulating resin (108) to cover, and the first sublayer (103), metal column (104) and chip (107) wrap by the first insulating resin (108);
(5) polish thinning for the first insulating resin (108), expose metal column (104) and metal salient point (105), metal column (104), metal salient point (105) and the first insulating resin (108) are positioned at same surface;
(6) form the second insulating resin (109) on the first insulating resin (108) surface, the second insulating resin (109) forms resin opening (110) by photoetching process, and metal column (104) and metal salient point (105) expose by resin opening (110); Form the second sublayer (103-1) on the second insulating resin (109) surface, the second sublayer (103-1) covers the surface of the second insulating resin (109), metal column (103) and metal salient point (105); Then at the second sublayer (103-1) surperficial resist coating (111), by photoetching process at photoresist (111) upper making the second sublayer, opening exposed portion (103-1), form the opening figure of conducting wire (112), in making conducting wire, opening figure place (112);
(7) photoresist (111) and the second sublayer (103-1) of exposing is removed, in conducting wire (112) and the second insulating resin (109) surface-coated the 3rd insulating resin (113), on the 3rd insulating resin (113), opening is made by photoetching process, conducting wire, exposed portion (112), forms the opening figure for making soldered ball;
(8) remove carrying tablet (101), temporarily bonding film (102) and the first sublayer (103), expose metal column (104);
(9) soldered ball (114) is made at the soldered ball opening figure place of the 3rd insulating resin (113); Then cover the 4th insulating resin (115) at chip (107) back side and the first insulating resin (108) back side, the 4th insulating resin (115) forms opening through photoetching process, exposes conductive pole (104);
(10) encapsulating structure that packaging body and step (9) obtain is carried out stacking, form three-dimension packaging structure.
2. the preparation method of multiple-level stack fan-out package structure as claimed in claim 1, is characterized in that: described step (8) can also adopt following technique: remove carrying tablet (101) and interim bonding film (102), expose the first sublayer (103); Retain the first sublayer (103) on metal column (104) surface.
3. the preparation method of multiple-level stack fan-out package structure as claimed in claim 1, is characterized in that: the encapsulating structure that described step (10) described packaging body is obtained by mode and the step (9) of soldered ball or routing carries out stacking.
4. the preparation method of multiple-level stack fan-out package structure as claimed in claim 1, it is characterized in that: the lamellar body that described carrying tablet (101) is silicon, silicon dioxide, pottery, glass, metal, alloy or organic material are made, or for the board device with temperature control can be heated.
5. the preparation method of multiple-level stack fan-out package structure as claimed in claim 1, is characterized in that: described interim bonding film (102) is thermoplastic or heat curing-type organic material, or the inorganic material containing Cu, Ni, Cr or Co.
6. a multiple-level stack fan-out package structure, comprises the first packaging body and the second packaging body that stack gradually; Its feature: described first packaging body comprises the chip (107) that front has metal salient point (105), Heraeus (106) are posted at the back side, chip (107) is wrapped in the first insulating resin (108), metal column (104) is provided with in the first insulating resin (108), the two ends of metal column (104) are concordant with the front and back of the first insulating resin (108) respectively, and the metal salient point (105) in chip (107) front is concordant with the front of the first insulating resin (108); The 4th insulating resin (115) is covered at the back side of described first insulating resin (108), 4th insulating resin (115) is provided with the opening exposing metal column (104), and the first packaging body and the second packaging body realize electrical connection by the metal column (104) of the 4th insulating resin (115) opening part; The second insulating resin (109), Seed Layer, conducting wire (112) and the 3rd insulating resin (113) is provided with successively in the front of described first insulating resin (108), 3rd insulating resin (113) is provided with the opening of soldered ball (114), arrange soldered ball (114) at opening part, conducting wire (112) connect soldered ball (114) and metal column (107).
7. multiple-level stack fan-out package structure as claimed in claim 6, is characterized in that: described second packaging body is chip with encapsulating structure or bare chip.
8. multiple-level stack fan-out package structure as claimed in claim 6, is characterized in that: described second packaging body is flip-chip or lead-bonding chip.
9. multiple-level stack fan-out package structure as claimed in claim 6, is characterized in that: described metal column (104) is gold, silver, one or more metal or alloy in copper, tin, titanium, nickel, magnesium, bismuth, palladium, nickel, chromium, iron, indium; Described metal column (104) is for spherical, cylindrical or conical.
10. multiple-level stack fan-out package structure as claimed in claim 6, is characterized in that: described metal salient point (105) is metal material, and the mode laser sintered by plating, chemical plating, evaporation, sputtering, printing, routing makes.
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