CN105097568A - Semiconductor lamination packaging method - Google Patents
Semiconductor lamination packaging method Download PDFInfo
- Publication number
- CN105097568A CN105097568A CN201510459158.XA CN201510459158A CN105097568A CN 105097568 A CN105097568 A CN 105097568A CN 201510459158 A CN201510459158 A CN 201510459158A CN 105097568 A CN105097568 A CN 105097568A
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- salient point
- metal salient
- chip
- packaging
- plastic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
The invention provides a semiconductor lamination packaging method. The method is characterized by comprising the following steps: A, manufacturing an upper packaging body; B, manufacturing a lower packaging body packaged with a chip; and C, performing lamination packaging on the upper packaging body and the lower packaging body. The step B comprises: S101, providing a metal plate for manufacturing the lower packaging body; S102, forming metal bumps on the upper surface of the metal plate; S103, connecting a chip to be loaded with the upper surface of the metal plate; S104, fixing and packaging the chip on the metal plate to form a plastic-sealed body by use of a plastic packaging bottom filling material; S105, polishing the plastic-sealed body; S106, removing the metal plate; and S107, forming a rewiring metal layer at the upper surface of the plastic-sealed body which is processed in S106, and forming first solder balls on the rewiring metal layer. According to the packaging method provided by the invention, the metal bumps are formed on the metal plate and are taken as electrodes of the lower packaging body so that multiple chips are vertically conducted in the whole packaging body; and the plastic-sealed body is polished so as to reduce the packaging thickness and improve the packaging density.
Description
Technical field
The present invention relates to a kind of method for packaging semiconductor, particularly relate to a kind of semiconductor laminated method for packing.
Background technology
Along with the development of semiconductor fabrication and three-dimensional encapsulation technology, electronic device and electronic product to multifunction and microminiaturized requirement more and more higher, require that the package dimension of chip constantly reduces simultaneously.In order to realize the microminiaturization of chip package, improve the integrated level of chip package, Stacked Die Packaging (stackeddiepackage) technology becomes the main flow of technical development gradually.
Stacked Die Packaging technology, also known as three-dimensional packaging technology, the specifically encapsulation technology of stacking at least two chips in same packaging body.Stacked Die Packaging technology can realize the Large Copacity of semiconductor device, multi-functional, the technical need such as small size, low cost, and therefore laminated chips technology obtains flourish in recent years.To use the memory of stacked package technology, compared to the memory not using stack technology, adopt the memory of stacked package technology can have the memory capacity of more than twice.In addition, use stacked package technology more can effectively utilize the area of chip, be applied to the aspect such as the USB flash disk of large memory space, SD card more.
Stacked Die Packaging technology can be realized by multiple technologies means, such as routing technique, silicon through hole (throughsiliconvia is called for short TSV) technology or plastic packaging through hole (throughmoldingvia is called for short TMV) technology.
Such as, silicon through hole (TSV) technology, forms through hole exactly on chip, recharges conductive materials formation through hole effect realize connecting up and down at through-hole side wall formation metal level.This process costs is high, and yields is low, directly easily causes damage to chip in silicon chip upper shed or makes full wafer wafer intensity losses cause the problems such as fragmentation, realizing difficulty larger.
And for example, plastic packaging through hole (TMV) technology refers at plastic packaging layer opening, namely use the methods such as laser to get through plastic packaging layer, filled conductive material after plastic packaging, but this technique is in the plastic packaging layer opening degree of depth and wayward in the bore edges insulating barrier getting through plastic packaging layer.
Remaining be exactly some first prefabricated can conducting material as matrix framework, carry out polishing, the technique such as routing be for connecting.
Above-mentioned technique, in the process of stacked chips, is filled dielectric medium and is not easily formed electrode in passing hole, the difficulty realizing chip upper and lower conducting in a whole packaging body of multiple packaging body encapsulation is comparatively large, and cost is higher.
Summary of the invention
Provide hereinafter about brief overview of the present invention, to provide about the basic comprehension in some of the present invention.Should be appreciated that this general introduction is not summarize about exhaustive of the present invention.It is not that intention determines key of the present invention or pith, and nor is it intended to limit the scope of the present invention.Its object is only provide some concept in simplified form, in this, as the preorder in greater detail discussed after a while.
The object of this invention is to provide a kind of semiconductor laminated method for packing, solve in existing packaging technology techniques such as () such as TSV, TMV that to form electrode more difficult, not easily realize the problem of chip upper and lower conducting in an overall package of stacked package.
The invention provides a kind of semiconductor laminated method for packing, comprising:
A: packaging body in making,
B: make the lower package body being packaged with chip,
C: by described upper packaging body and described lower package body stacked package,
Wherein, described step B comprises:
S101: the metallic plate making described lower package body is provided;
S102: form metal salient point at described metallic plate upper surface, the height of described metal salient point is more than or equal to the thickness waiting to load chip;
S103: described waiting is loaded the upper surface that chip is connected to described metallic plate;
S104: with filler at the bottom of plastic packaging said chip fixed and be packaged on described metallic plate forming plastic-sealed body, the coated described metal salient point of described plastic-sealed body;
S105: described plastic-sealed body of polishing, exposes the upper surface of described metal salient point and described chip;
S106: remove described metallic plate, exposes the lower surface of described metal salient point;
S107: the upper surface of the plastic-sealed body after step S106 process forms interconnection metal layer again, on described interconnection metal layer again, the correspondence position of wiring place of corresponding described metal salient point and described chip forms the first soldered ball.
The semiconductor laminated method for packing of one provided by the invention, realize interconnected by forming salient point on a metal plate, solve in passing hole in existing encapsulation technology and fill dielectric medium and form the more difficult problem of electrode, and the restriction such as in encapsulation tin ball is interconnected, realize chip a upper and lower conducting of packaging body; Chip to be fixed by filler at the bottom of plastic packaging and is encapsulated on a metal plate by the chip of lower package body, disposablely completes fixing and encapsulation two steps, reduces the problem of packaging body warpage in traditional stacked package; Reduced by the thickness of whole packaging body by the metallic plate below polishing plastic-sealed body and removal metal salient point, encapsulation saves space more, realizes the microminiaturization of chip package, improves the integrated level of chip package simultaneously.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the flow chart that the present invention makes the lower package body being packaged with chip;
Fig. 2-Fig. 7 is the process schematic that the present invention makes the lower package body being packaged with chip;
Fig. 8 is laminated packaging structure schematic diagram of the present invention.
Reference numeral:
1-metallic plate 2-metal salient point 3-chip
4-plastic-sealed body 5-is interconnection metal layer 6-first soldered ball again
Packaging body on 7-second soldered ball 8-
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.The element described in an accompanying drawing of the present invention or a kind of execution mode and feature can combine with the element shown in one or more other accompanying drawing or execution mode and feature.It should be noted that for purposes of clarity, accompanying drawing and eliminate expression and the description of unrelated to the invention, parts known to persons of ordinary skill in the art and process in illustrating.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art obtain under the prerequisite not paying creative work, all belongs to the scope of protection of the invention.
The invention provides a kind of semiconductor laminated method for packing, comprising:
A: packaging body in making,
B: make the lower package body being packaged with chip,
C: by described upper packaging body and described lower package body stacked package,
Wherein, be illustrated in figure 1 and make the step B being packaged with the lower package body of chip and comprise:
S101: the metallic plate making described lower package body is provided;
S102: form metal salient point at described metallic plate upper surface, the height of described metal salient point is more than or equal to the thickness waiting to load chip;
S103: described waiting is loaded the upper surface that chip is connected to described metallic plate;
S104: with filler at the bottom of plastic packaging said chip fixed and be packaged on described metallic plate forming plastic-sealed body, the coated described metal salient point of described plastic-sealed body;
S105: described plastic-sealed body of polishing, exposes the upper surface of described metal salient point and described chip;
S106: remove described metallic plate, exposes the lower surface of described metal salient point;
S107: the upper surface of the plastic-sealed body after step S106 process forms interconnection metal layer again, position corresponding with wiring place of described metal salient point and described chip on described interconnection metal layer again forms the first soldered ball.
Above-mentioned steps provides a kind of method that making is packaged with the lower package body of chip, as shown in Fig. 2-Fig. 3, implementation step S101-S103, provides the metallic plate 1 of preparation lower package body, forming metal salient point 2 at metallic plate 1 upper surface, loading waiting the upper surface that chip 3 is connected to metallic plate 1.
Optionally, metal salient point 2 can be formed by physics or chemical method at metallic plate 1 upper surface in step S102.
Further, prepare metal salient point by physical method, be specially: get a thinner metallic plate, at the upper surface weld metal Column preparation metal salient point 2 of metallic plate;
Or, prepare metal salient point by chemical method, be specially: get a thicker metallic plate, the metal salient point 2 with certain altitude is formed by the method for half-etching at the upper surface of metallic plate, namely at the upper surface pad pasting of metallic plate 1, exposure imaging, etch, form metal salient point 2.
Optionally, the material of metal salient point 2 is for having high connductivity and dystectic metal material, as copper etc., such as, metal salient point 2 can be copper post, in the present embodiment, the height of copper post is more than or equal to chip thickness to be loaded in lower package body, and copper post and chip have all been encapsulated in plastic-sealed body, and needs to carry out polishing in a subsequent step and expose copper post and chip, so the height of copper post does not need too high, save material and be convenient to following step.
Optionally, step S102 also comprises after described metallic plate upper surface forms metal salient point: protect copper agent in the upper surface plating of described metal salient point.Optionally, protecting copper agent is organic or inorganic guarantor weldering film.Organic or the inorganic oxide film at described metal salient point Surface Creation one deck; this tunic has anti-oxidation; heat-resisting; the characteristic of moisture-proof, can protect metal salient point surface non-corrosive under normal conditions, for follow-up technique is laid a good foundation; simultaneously; in follow-up welding high temperature, described oxide-film to be easy to remove by scaling powder, expose clean metal salient point surface and be combined into firmly solder joint with the scolding tin of melting in a short period of time.
As shown in Figure 4, implementation step S104 is fixing and be packaged on metallic plate 1 and form plastic-sealed body 4, plastic-sealed body 4 clad metal salient point 2 by chip 3 with filler at the bottom of plastic packaging.
Optionally, step S104 chips 3 to be fixed on metallic plate 1 with filler at the bottom of plastic packaging and to be encapsulated in plastic-sealed body 4 inner.The encapsulation of chip adopts molded underfill technology, and chip and described metal salient point are all wrapped in plastic-sealed body inside.
The above-mentioned glue for molded underfill technology is a kind of chemical glue, main component can be epoxy resin, space between chip 3 and metal salient point 2, metallic plate 1 is filled up, and wrap up described chip 3 and metal salient point 2, filling glue is heating and curing, the object of reinforcing can be reached, the guaranteed electrical security of welding procedure.
Then implementation step S105, above-mentioned plastic-sealed body of polishing, exposes the upper surface of metal salient point 2 and chip 3, as shown in Figure 5.
This step makes the height of copper post identical with the thickness of chip, filler at the bottom of plastic packaging is concordant with the upper surface of chip, expose the upper surface of metal salient point 2 and chip 3, facilitate the follow-up upper surface at copper post and chip to form interconnection metal layer more on the one hand, the thickness being thinned packaging body on the other hand makes encapsulation more be tending towards high density.
Optionally, after step S105 exposes the upper surface of metal salient point 2 and chip 3, the upper surface of clean metal salient point 2, needs to plate at the upper surface at the metal salient point 2 exposed to protect copper agent again, protects the metal salient point exposed, for follow-up technique is laid a good foundation.
Then implementation step S106, removes the metallic plate 1 in Fig. 5, exposes the lower surface of metal salient point 2, simultaneously the lower surface of also exposed chip 3, as shown in Figure 6.By this step, the thickness being thinned packaging body further makes encapsulation more be tending towards high density.
As shown in Figure 7, implementation step S107, the upper surface of the plastic-sealed body after step S106 process forms interconnection metal layer 5 again, and position corresponding with wiring place of metal salient point 2 and chip 3 on interconnection metal layer 5 again forms the first soldered ball 6.
Form interconnection metal layer 5 by the upper surface of the plastic-sealed body after step S106 process, then corresponding with wiring place of metal salient point 2 and chip 3 on interconnection metal layer 5 again position forms the first soldered ball 6, is welded on printed circuit board (PCB) after being convenient to so again.
Through above-mentioned steps, the lower package body being packaged with chip completes, then step C is carried out: by described upper packaging body and described lower package body stacked package, need upper packaging body and the docking of described lower package body, carry out reflow soldering again to form semiconductor laminated encapsulating structure, form encapsulating structure as shown in Figure 8.As shown in Figure 8, in the embodiment of the present invention, upper packaging body 8 base plate bottom is preferably metallic plate, as the conductive connection part position of upper packaging body 8.
Further, the position of the corresponding metal salient point 2 of lower surface of the plastic-sealed body after step C is included in step S106 process forms the second soldered ball 7; The second soldered ball 7 that upper packaging body 8 conductive connection part position is arranged by the lower surface of metal salient point 2 docks with described lower package body, then carries out reflow soldering formation semiconductor laminated encapsulating structure as shown in Figure 8.
But the lower package body that the above embodiment of the present invention provides, the lower surface stood good in upper packaging body has tin ball or tin ball to add the situation of metal salient point, such as, can in fig. 8 shown in the lower surface of metallic plate of upper packaging body 8 form the second soldered ball 7; Upper packaging body 8 is docked with the lower surface of the metal salient point 2 of above-mentioned lower package body by the second soldered ball 7 of its lower surface, then carries out reflow soldering formation semiconductor laminated encapsulating structure as shown in Figure 8.
Fig. 8 is laminated packaging structure schematic diagram of the present invention, lower package body realizes electrical interconnection by metal salient point 2 and upper packaging body 8, and plastic-sealed body of polishing makes the height of described metal salient point 2 equal the thickness of described chip 3, after docking and reflow soldering process, upper lower package body combines and defines laminated packaging structure.Simultaneously, the stacked package that this programme proposes is the connection of upper and lower two packaging bodies, according to the actual needs, the packaging body number of stacked package can determine according to actual conditions, can at the more chip package layer of upper packaging body upper surface stacked package, also can between upper packaging body and lower package body the more chip package layer of stacked package, increase the structure of stacked package.
Semiconductor laminated method for packing provided by the invention is in the process of preparation lower package body, by forming the electrode of metal salient point as lower package body on a metal plate, to connect upper packaging body, solve in the packaging technologies such as TSV, TMV and in passing hole, fill the more difficult problem of dielectric medium formation electrode, better electrical property is had because copper post is interconnected, also solve the restrictions such as the interconnected volume of tin ball simultaneously, conveniently realize multiple chips upper and lower conducting in an overall package of stacked package; Chip to be fixed by filler at the bottom of plastic packaging and is encapsulated on a metal plate by the chip of lower package body, disposablely completes fixing and encapsulation two steps, reduces the problem of packaging body warpage in traditional stacked package, decrease the time of manufacture, and improve mechanical stability, reduce costs, improve reliability; By polishing plastic-sealed body, remove metallic plate, expose metal salient point and connect, reduce the thickness of whole packaging body further, make stacked package high density more.
In the embodiments such as apparatus and method of the present invention, obviously, each parts or each step reconfigure after can decomposing, combine and/or decomposing.These decompose and/or reconfigure and should be considered as equivalents of the present invention.Simultaneously, above in the description of the specific embodiment of the invention, the feature described for a kind of execution mode and/or illustrate can use in one or more other execution mode in same or similar mode, combined with the feature in other execution mode, or substitute the feature in other execution mode.
Should emphasize, term " comprises/comprises " existence referring to feature, key element, step or assembly when using herein, but does not get rid of the existence or additional of one or more further feature, key element, step or assembly.
Although last it is noted that described the present invention and advantage thereof in detail above, be to be understood that and can carry out various change when not exceeding the spirit and scope of the present invention limited by appended claim, substituting and converting.And scope of the present invention is not limited only to the specific embodiment of process, equipment, means, method and step described by specification.One of ordinary skilled in the art will readily appreciate that from disclosure of the present invention, can use perform the function substantially identical with corresponding embodiment described herein or obtain and its substantially identical result, existing and that will be developed in the future process, equipment, means, method or step according to the present invention.Therefore, appended claim is intended to comprise such process, equipment, means, method or step in their scope.
Claims (9)
1. a semiconductor laminated method for packing, comprising:
A: packaging body in making,
B: make the lower package body being packaged with chip,
C: by described upper packaging body and described lower package body stacked package,
It is characterized in that, described step B comprises:
S101: the metallic plate making described lower package body is provided;
S102: form metal salient point at described metallic plate upper surface, the height of described metal salient point is more than or equal to the thickness of chip to be loaded;
S103: upper surface chip described to be loaded being connected to described metallic plate;
S104: with filler at the bottom of plastic packaging said chip fixed and be packaged on described metallic plate forming plastic-sealed body, the coated described metal salient point of described plastic-sealed body;
S105: described plastic-sealed body of polishing, exposes the upper surface of described metal salient point and described chip;
S106: remove described metallic plate, exposes the lower surface of described metal salient point;
S107: the upper surface of the plastic-sealed body after step S106 process forms interconnection metal layer again, wiring place formation first soldered ball of corresponding described metal salient point and described chip on described interconnection metal layer again.
2. method according to claim 1, is characterized in that, described step C comprises:
The position of the corresponding metal salient point of lower surface of the plastic-sealed body after described step S106 process forms the second soldered ball;
Upper packaging body conductive connection part position is docked with described lower package body by above-mentioned second soldered ball, then carries out reflow soldering and form semiconductor laminated encapsulating structure.
3. method according to claim 1, is characterized in that, described step C comprises:
The second soldered ball is formed in upper packaging body conductive connection part position;
Upper packaging body is docked with the metal salient point lower surface in described lower package body by described second soldered ball, then carries out reflow soldering and form semiconductor laminated encapsulating structure.
4. according to the method in claim 2 or 3, it is characterized in that, step S102 forms metal salient point at described metallic plate upper surface and is specially:
Metal salient point is formed by the method for welding at the upper surface of described metallic plate; Or; Metal salient point is formed by the method for half-etching at the upper surface of described metal salient point.
5. method according to claim 4, is characterized in that, the metal salient point described in step S102 is copper post.
6. method according to claim 1, is characterized in that, chip described in step S104 to be fixed on described metallic plate with filler at the bottom of plastic packaging and to be encapsulated in described plastic-sealed body inner.
7. method according to claim 1, is characterized in that, step S102 also comprises after described metallic plate upper surface forms metal salient point: protect copper agent in the upper surface plating of described metal salient point.
8. method according to claim 1, is characterized in that, after step S105 exposes the upper surface of described metal salient point and described chip, cleans the upper surface of described metallized metal salient point, protects copper agent in the upper surface plating of the metal salient point exposed.
9. the method according to claim 7 or 8, is characterized in that, described in protect copper agent be organic or inorganic guarantor weldering film.
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| CN201510459158.XA CN105097568A (en) | 2015-07-30 | 2015-07-30 | Semiconductor lamination packaging method |
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| CN201510459158.XA CN105097568A (en) | 2015-07-30 | 2015-07-30 | Semiconductor lamination packaging method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105470149A (en) * | 2015-12-22 | 2016-04-06 | 南通富士通微电子股份有限公司 | Patch element manufacturing method |
| CN105514099A (en) * | 2015-12-22 | 2016-04-20 | 华进半导体封装先导技术研发中心有限公司 | Multiple-layer stacked fan-out type packaging structure and preparation method thereof |
| CN106960827A (en) * | 2017-03-29 | 2017-07-18 | 袁鹰 | Three-dimension packaging structure and its method for packing |
| CN109034789A (en) * | 2017-06-08 | 2018-12-18 | 鸿骅科技股份有限公司 | Method for online payment, computer program product and mobile payment card thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538375A (en) * | 2014-12-30 | 2015-04-22 | 华天科技（西安）有限公司 | Fan-out PoP packaging structure and manufacturing method thereof |
-
2015
- 2015-07-30 CN CN201510459158.XA patent/CN105097568A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538375A (en) * | 2014-12-30 | 2015-04-22 | 华天科技（西安）有限公司 | Fan-out PoP packaging structure and manufacturing method thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105470149A (en) * | 2015-12-22 | 2016-04-06 | 南通富士通微电子股份有限公司 | Patch element manufacturing method |
| CN105514099A (en) * | 2015-12-22 | 2016-04-20 | 华进半导体封装先导技术研发中心有限公司 | Multiple-layer stacked fan-out type packaging structure and preparation method thereof |
| CN105470149B (en) * | 2015-12-22 | 2018-07-31 | 通富微电子股份有限公司 | Surface mount elements processing method |
| CN106960827A (en) * | 2017-03-29 | 2017-07-18 | 袁鹰 | Three-dimension packaging structure and its method for packing |
| CN109034789A (en) * | 2017-06-08 | 2018-12-18 | 鸿骅科技股份有限公司 | Method for online payment, computer program product and mobile payment card thereof |
| CN109034789B (en) * | 2017-06-08 | 2022-02-15 | 鸿骅科技股份有限公司 | Method for online payment, computer program product and mobile payment card thereof |
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Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong |
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Application publication date: 20151125 |