CN111293098B - Embedded chip package, manufacturing method thereof and laminated packaging structure - Google Patents
Embedded chip package, manufacturing method thereof and laminated packaging structure Download PDFInfo
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- CN111293098B CN111293098B CN201811486670.3A CN201811486670A CN111293098B CN 111293098 B CN111293098 B CN 111293098B CN 201811486670 A CN201811486670 A CN 201811486670A CN 111293098 B CN111293098 B CN 111293098B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
Abstract
The invention provides an embedded chip package, a manufacturing method thereof and a laminated packaging structure. The circuit board comprises a glass substrate and at least one conductive through hole. The glass substrate is provided with a first surface, a second surface opposite to the first surface and a through groove penetrating through the glass substrate. The conductive through hole penetrates through the glass substrate. The chip is arranged in the through groove. The dielectric material layer is filled in the through groove and covers the chip. The build-up circuit structure is configured on the circuit board. The build-up circuit structure is electrically connected with the conductive through hole. The lower surface of the chip is exposed outside the dielectric material layer.
Description
Technical Field
The present invention relates to chip packages, methods of fabricating the same, and stacked package structures, and particularly to an embedded chip package, a method of fabricating the same, and a stacked package structure.
Background
The conventional chip packaging method requires a first packaging adhesive layer to protect the chip, and then continues to add other circuits or package in a two-dimensional direction. Then, the stacking and assembling often cause a large warpage, which affects the yield and subsequent reliability of the package.
Disclosure of Invention
The invention provides an embedded chip package with better package yield and reliability.
The invention provides a laminated packaging structure which has the advantage of increasing a stacked structure and a circuit.
The invention provides a manufacturing method of an embedded chip package, which is used for manufacturing the embedded chip package and can improve the warping problem generated by a build-up circuit or the package.
The embedded chip package comprises a circuit board, a chip, a dielectric material layer and a build-up circuit structure. The circuit board comprises a glass substrate and at least one conductive through hole. The glass substrate is provided with a first surface, a second surface opposite to the first surface and a through groove penetrating through the glass substrate. The conductive through hole penetrates through the glass substrate. The chip is arranged in the through groove. The dielectric material layer is filled in the through groove and covers the chip. The build-up circuit structure is configured on the circuit board. The build-up circuit structure is electrically connected with the conductive through hole. The lower surface of the chip is exposed outside the dielectric material layer.
In an embodiment of the invention, a lower surface of the chip is flush with the second surface of the glass substrate.
In an embodiment of the invention, the build-up circuit structure includes a first circuit layer, a first dielectric layer, a second circuit layer, and at least one first via hole. The first dielectric layer covers the first circuit layer. The second circuit layer and the first circuit layer are respectively positioned at two opposite sides of the first dielectric layer. The first via hole penetrates through the first dielectric layer to electrically connect the first circuit layer and the second circuit layer.
In an embodiment of the invention, the build-up circuit structure is disposed on the first surface of the glass substrate. The embedded chip package further comprises a patterned conductive layer and solder balls or copper pillars. The patterned conductive layer is disposed on the second surface of the glass substrate, so that the build-up circuit structure and the patterned conductive layer are respectively located on two opposite sides of the glass substrate. The solder ball or the copper column is arranged on the patterned conductive layer, so that the solder ball or the copper column and the circuit board are respectively positioned at two opposite sides of the patterned conductive layer.
In an embodiment of the invention, the lower surface of the chip is an active surface. The active surface faces the patterned conductive layer and is electrically connected with the patterned conductive layer.
In an embodiment of the invention, the build-up circuit structure is electrically connected to the patterned conductive layer through the conductive via.
In an embodiment of the invention, the build-up circuit structure is disposed on the second surface of the glass substrate. The embedded chip package further comprises solder balls or copper pillars. The tin ball or the copper column is configured on the layer-adding circuit structure, so that the tin ball or the copper column and the circuit board are respectively positioned at two opposite sides of the layer-adding circuit structure.
In an embodiment of the invention, the lower surface of the chip is an active surface. The active surface faces the build-up circuit structure and is electrically connected with the build-up circuit structure.
In an embodiment of the invention, the through groove connects the first surface and the second surface of the glass substrate.
The stacked package structure of the present invention includes a circuit board, at least one embedded chip package (the build-up circuit structure is disposed on the first surface of the glass substrate) (hereinafter referred to as a first embedded chip package) and at least one embedded chip package (the build-up circuit structure is disposed on the second surface of the glass substrate) (hereinafter referred to as a second embedded chip package). The first embedded chip package is configured on the circuit board. The second embedded chip package is disposed on the first embedded chip package. The second embedded chip package and the circuit board are respectively positioned at two opposite sides of the first embedded chip package.
In an embodiment of the invention, the solder balls or the copper pillars of the second embedded chip package are electrically connected to the build-up circuit structure of the first embedded chip package. The solder balls or copper columns of the first embedded chip package are electrically connected with the circuit board.
The manufacturing method of the embedded chip package comprises the following steps. First, a carrier and a release layer on the carrier are provided. Then, a chip is disposed on the release layer. And configuring the circuit board on the release layer. The circuit board comprises a glass substrate and at least one conductive through hole. The glass substrate is provided with a first surface, a second surface opposite to the first surface and a through groove penetrating through the glass substrate. The conductive through hole penetrates through the glass substrate. After the chip and the circuit board are arranged on the release layer and the chip is embedded into the through groove, the dielectric material layer is formed on the release layer. The dielectric material layer is filled in the through groove and covers the chip. Then, the release layer and the carrier are removed, so that the lower surface of the chip is exposed outside the dielectric material layer. After the release layer and the carrier are removed, a build-up circuit structure is formed on the circuit board so as to electrically connect the build-up circuit structure and the conductive through hole.
In an embodiment of the invention, the build-up circuit structure is disposed on the first surface of the glass substrate. The manufacturing method of the embedded chip package further comprises the following steps. And forming a patterned conductive layer on the second surface of the glass substrate, so that the build-up circuit structure and the patterned conductive layer are respectively positioned on two opposite sides of the glass substrate. And forming a solder ball or a copper column on the patterned conductive layer, so that the solder ball or the copper column and the circuit board are respectively positioned at two opposite sides of the patterned conductive layer.
In an embodiment of the invention, the build-up circuit structure is disposed on the second surface of the glass substrate. The manufacturing method of the embedded chip package further comprises the following steps. And forming a solder ball or a copper column on the layer-adding circuit structure, so that the solder ball or the copper column and the circuit board are respectively positioned at two opposite sides of the layer-adding circuit structure.
Based on the above, in the embedded chip package, the manufacturing method thereof and the stacked package structure of the invention, the embedded chip package includes a circuit board, a chip, a dielectric material layer and a build-up circuit structure. The circuit board comprises a glass substrate and a conductive through hole, wherein the glass substrate is provided with a through groove penetrating through the glass substrate. Then, the chip is arranged in the through groove, the dielectric material layer is filled in the through groove, and the layer-adding circuit structure is arranged on the circuit board. By the design, the manufacturing method of the embedded chip package can improve the warping problem generated by the layer-adding circuit or the package, so that the embedded chip package has better package yield and reliability, and the laminated package structure has the advantage of increasing the stacking structure and the circuit.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1A to fig. 1F are schematic cross-sectional views illustrating a method for manufacturing an embedded chip package according to an embodiment of the invention.
Fig. 1G is a schematic bottom view of the embedded chip package of fig. 1F.
Fig. 1H is a schematic cross-sectional view of a buried chip package according to another embodiment of the invention.
Fig. 2A to fig. 2B are schematic cross-sectional views illustrating a method for manufacturing a buried chip package according to another embodiment of the invention.
Fig. 2C is a schematic cross-sectional view of a buried chip package according to another embodiment of the invention.
Fig. 3A to 3B are schematic cross-sectional views illustrating a side-by-side package structure according to various embodiments of the invention.
Fig. 4A to 4B are schematic cross-sectional views illustrating package on package structures according to various embodiments of the invention.
[ notation ] to show
10. 10 a: parallel packaging structure
10b, 10 c: laminated packaging structure
100. 100a, 100b, 100 c: embedded chip package
110: carrier
112: release layer
120: chip and method for manufacturing the same
121: lower surface
122: active surface
130: circuit board
131: glass substrate
132: first surface
133: second surface
134: trough penetrating
135: conductive vias
140: dielectric material layer
150. 150 b: layer-adding circuit structure
151: first circuit layer
152: a first dielectric layer
153: second circuit layer
154: first via hole
155: a second dielectric layer
156: second via hole
160: patterned conductive layer
170. 170 a: tin ball
172. 172 a: copper column
200. 200a, 200b, 200 c: circuit board
Detailed Description
The foregoing and other technical and scientific aspects, features and utilities of the present invention will be apparent from the following detailed description of various embodiments, which is to be read in connection with the accompanying drawings. Directional terms as referred to in the following examples, for example: "upper", "lower", "front", "rear", "left", "right", etc., are simply directions with reference to the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting.
In the detailed description of the embodiments, terms such as "first," "second," "third," "fourth," etc. may be used to describe various elements. These terms are only used to distinguish one element from another, but in the structure, these elements should not be limited by these terms. For example, a first element may be termed a second element, and, similarly, a second element may be termed a first element, without departing from the scope of the present inventive concept. In addition, the order of formation of such elements or components in a manufacturing process should not be limited by these terms, except as to the particular manufacturing flow. For example, the first element may be formed before the second element. Alternatively, the first element may be formed after the second element. Alternatively, the first element and the second element may be formed in the same manufacturing or step.
Also, the thickness of layers and regions in the drawings may be exaggerated for clarity. The same or similar reference numerals denote the same or similar elements, and the description thereof will not be repeated in the following paragraphs.
Fig. 1A to fig. 1F are schematic cross-sectional views illustrating a method for manufacturing an embedded chip package according to an embodiment of the invention. Fig. 1G is a schematic bottom view of the embedded chip package of fig. 1F. For clarity and convenience of illustration, the patterned conductive layer 160 and the solder balls 170 are omitted from fig. 1G.
Referring to fig. 1A, a carrier 110 and a release layer 112 disposed on the carrier 110 are provided, and then a chip 120 is disposed on the release layer 112. In the present embodiment, the carrier 110 may be a metal substrate, a silicon substrate, a glass substrate, a ceramic substrate, or other suitable carrier that can be used for supporting. The release layer 112 may be formed of a polymer-based material, which may be removed in a subsequent step together with the carrier 110. In some embodiments, the release layer 112 is an epoxy-based heat release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 112 may be an Ultraviolet (UV) glue that loses its adhesive properties when exposed to UV light. The release layer 112 may be dispensed as a liquid and cured, and the release layer 112 may be a laminate film (laminate film) laminated to the carrier 110, or may be in other forms.
Referring to fig. 1B, the circuit board 130 is disposed on the release layer 112. In the present embodiment, the circuit board 130 includes a glass substrate 131 and at least one conductive via 135. The glass substrate 131 has a first surface 132, a second surface 133 opposite to the first surface 132, and a through hole 134 penetrating through the glass substrate 131. In some embodiments, the through-groove 134 connects the first surface 132 and the second surface 133 of the glass substrate 131.
The following steps may be utilized to form the conductive via 135, but not limited thereto. First, the glass substrate 131 is drilled by laser or machining to form a through hole penetrating the glass substrate 131. Wherein the through hole connects the first surface 132 and the second surface 133. Then, a seed layer (not shown) is formed in the via hole, and a conductive material (not shown) is formed in the via hole by electroplating, thereby forming a conductive via 135 penetrating through the glass substrate 131. Here, the conductive material may be a metal or a metal alloy, such as copper, titanium, tungsten, aluminum, or the like, or a combination thereof.
It should be noted that, in the embodiment, the chip 120 is disposed on the release layer 112, the circuit board 130 is disposed on the release layer 112, and the through-groove 134 of the circuit board 130 is aligned with the chip 120, so that the chip 120 is embedded in the through-groove 134 of the circuit board 130, but the invention is not limited thereto. That is, in other embodiments, the circuit board 130 may be disposed on the release layer 112, the chip 120 may be disposed on the release layer 112, and the chip 120 may be embedded in the through groove 134 of the circuit board 130.
In addition, in the embodiment, the thickness of the circuit board 130 and the thickness of the chip 120 may be the same or different, and is not limited in the present invention. In addition, although the sizes of the through-grooves 134 and the chips 120 are not limited in this embodiment, it should be noted that the cross-sectional area of the through-grooves 134 of the circuit board 130 is larger than that of the chips 120, so that the chips 120 are suitably embedded in the through-grooves 134 of the circuit board 130.
Next, referring to fig. 1C, after the chip 120 and the circuit board 130 are disposed on the release layer 112 and the chip 120 is embedded in the through groove 134, a dielectric material layer 140 is formed on the release layer 112, so that the dielectric material layer 140 is filled in the through groove 134 and covers the chip 120. In this embodiment, a resin (e.g., epoxy), silane (e.g., Hexamethyldisiloxane (HMDSN), Tetraethoxysilane (TEOS), bis (dimethylamino) dimethylsilane (bddms)), or other suitable dielectric material may be coated on the release layer 112 and cured to form the dielectric material layer 140. Therefore, the dielectric material layer 140 can be filled in the through-groove 134 and located between the chip 120 and the circuit board 130, so that a good buffer is provided between the chip 120 and the circuit board 130.
Referring to fig. 1D, after the dielectric material layer 140 is formed, the release layer 112 and the carrier 110 are removed, so that the lower surface 121 of the chip 120 is exposed outside the dielectric material layer 140. In some embodiments, the lower surface 121 of the chip 120 is exposed outside the through-groove 134 of the circuit board 130. In addition, since the circuit board 130 and the chip 120 are both disposed on the release layer 112 and in contact with the release layer 112, the lower surface 121 of the chip 120 can be flush with the second surface 133 of the glass substrate 131.
Referring to fig. 1E, after removing the release layer 112 and the carrier 110, a build-up circuit structure 150 is formed on the circuit board 130, and a patterned conductive layer 160 is formed on the circuit board 130. The build-up circuit structure 150 may be electrically connected to the conductive via 135, the patterned conductive layer 160 may be electrically connected to the conductive via 135, and the patterned conductive layer 160 may be electrically connected to the chip 120. Therefore, the build-up circuit structure 150 can be electrically connected to the patterned conductive layer 160 through the conductive via 135. Specifically, the build-up circuit structure 150 includes a first circuit layer 151, a first dielectric layer 152, a second circuit layer 153, and at least one first via 154. The first circuit layer 151 covers the first surface 132 of the glass substrate 131, and the first dielectric layer 152 covers the first circuit layer 151 and the first surface 132 of the glass substrate 131. The first via hole 154 penetrates the first dielectric layer 152 to electrically connect the first circuit layer 151 and the second circuit layer 153. The second circuit layer 153 and the first circuit layer 151 are respectively located on two opposite sides of the first dielectric layer 152.
In addition, in the present embodiment, since the build-up circuit structure 150 is formed on the first surface 132 of the glass substrate 131, and the patterned conductive layer 160 is formed on the second surface 133 of the glass substrate 131, the build-up circuit structure 150 and the patterned conductive layer 160 are respectively located on two opposite sides of the glass substrate 131.
In addition, in the present embodiment, the lower surface 121 of the chip 120 can be used as the active surface 122. The active surface 122 faces the patterned conductive layer 160, and the active surface 122 may be electrically connected to the patterned conductive layer 160.
Next, in order to electrically connect the embedded chip package 100 of the present embodiment with the outside, a conductive connector may be formed on the patterned conductive layer 160. In the present embodiment, the conductive connecting member may be, for example, a solder ball 170, but not limited thereto. Referring to fig. 1F, a solder ball 170 is formed on the patterned conductive layer 160, such that the solder ball 170 and the circuit board 130 are respectively located on two opposite sides of the patterned conductive layer 160. At this time, the embedded chip package 100 of the present embodiment is substantially completed.
In addition, referring to fig. 1G, in the embodiment, the shape of the through groove 134 may be a circle, but not limited thereto. That is, in other embodiments, the through-groove may have a square shape or other suitable shape as long as the chip can be embedded in the through-groove of the circuit board.
In brief, the embedded chip package 100 of the present embodiment includes a circuit board 130, a chip 120, a dielectric material layer 140, and a build-up circuit structure 150. The circuit board 130 includes a glass substrate 131 and at least one conductive via 135. The glass substrate 131 has a first surface 132, a second surface 133 opposite to the first surface 132, and a through groove 134 penetrating through the glass substrate 131. The conductive via 135 penetrates the glass substrate 131. The chip 120 is disposed in the through-groove 134. The dielectric material layer 140 is filled in the through-groove 134 and covers the chip 120. The build-up circuit structure 150 is disposed on the circuit board 130. The build-up circuitry 150 is electrically connected to the conductive via 135. The lower surface 121 of the chip 120 is exposed out of the dielectric material layer 140. By such a design, the method for manufacturing the embedded chip package 100 of the present embodiment can improve the warpage problem caused by the build-up circuit structure 150 or the package, and the embedded chip package 100 of the present embodiment has a better package yield and reliability.
Other examples will be listed below for illustration. It should be noted that the following embodiments follow the reference numerals and parts of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.
Fig. 1H is a schematic cross-sectional view of a buried chip package according to another embodiment of the invention. Referring to fig. 1F and fig. 1H, the embedded chip package 100a of the present embodiment is similar to the embedded chip package 100 of fig. 1F, but the main difference between the two is: the conductive connecting member of the embedded chip package 100a of the present embodiment is a copper pillar 172, and the build-up circuit structure 150a further includes a second dielectric layer 155 and a second via 156. Specifically, in the method for manufacturing the embedded chip package 100a of the present embodiment, after the steps shown in fig. 1A to fig. 1D are performed, referring to fig. 1H, the build-up circuit structure 150a is formed on the circuit board 130, and the patterned conductive layer 160 is formed on the circuit board 130. The build-up line structure 150a further includes a second dielectric layer 155 and a second via hole 156. The second dielectric layer 155 covers the second circuit layer 153 and the first dielectric layer 152. The second via hole 156 penetrates the second dielectric layer 155 to electrically connect to the second circuit layer 153. Then, referring to fig. 1H, copper pillars 172 are formed on the patterned conductive layer 160, such that the copper pillars 172 and the circuit board 130 are respectively located on two opposite sides of the patterned conductive layer 160.
Fig. 2A to fig. 2B are schematic cross-sectional views illustrating a method for manufacturing a buried chip package according to another embodiment of the invention. The embodiment shown in fig. 2A to 2B differs from the embodiment shown in fig. 1A to 1F in that: the position of the build-up line structure 150b of the embedded chip package 100b, the active surface 122 and the build-up line structure 150b of the embodiment are in a relative relationship. In addition, the embedded chip package 100b of the present embodiment does not include a patterned conductive layer.
Specifically, in the method for manufacturing the embedded chip package 100b of the present embodiment, the build-up circuit structure 150b is formed on the circuit board 130 after the steps shown in fig. 1A to 1D are performed, and then, referring to fig. 2A. At this time, the build-up circuit structure 150b is disposed on the second surface 133 of the glass substrate 131, and the build-up circuit structure 150b may be electrically connected to the conductive via 135. In the present embodiment, the lower surface 121 of the chip 120 may be an active surface 122. The active surface 122 faces the build-up circuit structure 150b, and the active surface 122 may be electrically connected to the build-up circuit structure 150 b.
Then, referring to fig. 2B, a solder ball 170a is formed on the build-up circuit structure 150B, such that the solder ball 170a and the circuit board 130 are respectively located on two opposite sides of the build-up circuit structure 150B. At this time, the embedded chip package 100b of the present embodiment is substantially completed.
Although the solder balls 170a are formed on the build-up circuit structure 150B in fig. 2B, the invention is not limited thereto. That is, in other embodiments, as shown in fig. 2C, a copper pillar 172a may also be formed on the build-up circuit structure 150b to complete the embedded chip package 100C according to another embodiment.
Fig. 3A to 3B are schematic cross-sectional views illustrating a side-by-side package structure according to various embodiments of the invention. The parallel type package structure is configured by arranging the manufactured embedded chip package 100 or the embedded chip package 100a on the circuit boards 200 and 200a in a parallel manner. Referring to fig. 3A, in the parallel package structure 10 of the present embodiment, 2 embedded chip packages 100 are schematically disposed on a circuit board 200. The 2 embedded chip packages 100 can be electrically connected to the circuit board 200 through the solder balls 170. Referring to fig. 3B, in the parallel package structure 10a of the present embodiment, 2 embedded chip packages 100a are schematically disposed on the circuit board 200 a. The 2 embedded chip packages 100a can be electrically connected to the circuit board 200a through the copper pillars 172.
It should be noted that although fig. 3A (or fig. 3B) schematically illustrates 2 embedded chip packages 100 (or embedded chip packages 100a) disposed on the circuit board 200 (or circuit board 200a), the number of embedded chip packages 100 (or embedded chip packages 100a) in the side-by-side package structure is not limited in the present invention. That is, in other embodiments not shown, more than 2 embedded chip packages 100 (or embedded chip packages 100a) may be disposed on the circuit board 200 (or circuit board 200a) to form different parallel package structures.
Fig. 4A to 4B are schematic cross-sectional views illustrating a package on package structure according to various embodiments of the invention. The stacked package structure is formed by stacking the embedded chip packages 100, 100a, 100b, 100c, or a combination thereof on the circuit boards 200b, 200 c. Referring to fig. 4A, in the stacked package structure 10b of the present embodiment, 1 of the embedded chip packages 100 is schematically disposed on the circuit board 200b, and 1 of the embedded chip packages 100b is disposed on the embedded chip package 100. The embedded chip package 100b and the circuit board 200b are respectively located at two opposite sides of the embedded chip package 100. In addition, the solder balls 170a of the embedded chip package 100b may be electrically connected to the build-up circuit structure 150 of the embedded chip package 100. The solder balls 170 of the embedded chip package 100 are electrically connected to the circuit board 200 b.
Referring to fig. 4B, in the stacked package structure 10c of the present embodiment, 1 of the embedded chip packages 100a is schematically disposed on the circuit board 200c, and 1 of the embedded chip packages 100c is disposed on the embedded chip package 100 a. The embedded chip package 100c and the circuit board 200c are respectively located at two opposite sides of the embedded chip package 100 a. In addition, the copper pillar 172a of the embedded chip package 100c may be electrically connected to the build-up circuit structure 150a of the embedded chip package 100 a. The copper pillar 172 of the embedded chip package 100a may be electrically connected to the circuit board 200 c.
It should be noted that although fig. 4A (or fig. 4B) schematically configures 1 embedded chip package 100 (or embedded chip package 100a) between the embedded chip package 100B (or embedded chip package 100c) and the circuit board 200B (or circuit board 200c), the present invention does not limit the number of embedded chip packages 100 (or embedded chip packages 100a) in the stacked package structure. That is, in other embodiments that are not shown, more than 1 embedded chip package 100 (or embedded chip package 100a) may be disposed between the embedded chip package 100b (or embedded chip package 100c) and the circuit board 200b (or circuit board 200c) to form a stacked package structure having a plurality of stacked layers. In other words, the stack package structures 10b and 10c of the present embodiment have the advantage of increasing the stacking structure and the circuit.
In summary, in the embedded chip package, the manufacturing method thereof and the stacked package structure of the invention, the embedded chip package includes a circuit board, a chip, a dielectric material layer and a build-up circuit structure. The circuit board comprises a glass substrate and a conductive through hole, wherein the glass substrate is provided with a through groove penetrating through the glass substrate. Then, the chip is arranged in the through groove, the dielectric material layer is filled in the through groove, and the layer-adding circuit structure is arranged on the circuit board. By the design, the manufacturing method of the embedded chip package can improve the warping problem generated by the layer-adding circuit or the package, so that the embedded chip package has better package yield and reliability, and the laminated package structure has the advantage of increasing the stacking structure and the circuit.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (18)
1. A buried chip package, comprising:
a wiring board, comprising:
the glass substrate is provided with a first surface, a second surface opposite to the first surface and a through groove penetrating through the glass substrate; and
the at least one conductive through hole penetrates through the glass substrate, and two ends of the conductive through hole are respectively flush with the first surface and the second surface of the glass substrate;
the chip is configured in the through groove;
the dielectric material layer is filled in the through groove and covers the chip; and
a build-up circuit structure disposed on the circuit board, wherein the build-up circuit structure is electrically connected to the conductive via, and the lower surface of the chip is exposed outside the dielectric layer, wherein the build-up circuit structure includes:
a first circuit layer directly contacting either one of the two ends of the conductive via;
a first dielectric layer covering the first circuit layer;
the second circuit layer and the first circuit layer are respectively positioned at two opposite sides of the first dielectric layer; and
at least one first via hole penetrates through the first dielectric layer to electrically connect the first circuit layer and the second circuit layer.
2. The embedded chip package of claim 1, wherein the lower surface of the chip is flush with the second surface of the glass substrate.
3. The embedded chip package of claim 1, wherein the build-up circuitry structure is disposed on the first surface of the glass substrate, the embedded chip package further comprising:
the patterned conducting layer is configured on the second surface of the glass substrate, so that the build-up circuit structure and the patterned conducting layer are respectively positioned on two opposite sides of the glass substrate; and
and the solder balls or the copper columns are arranged on the patterned conductive layer, so that the solder balls or the copper columns and the circuit board are respectively positioned at two opposite sides of the patterned conductive layer.
4. The embedded chip package of claim 3, wherein the lower surface of the chip is an active surface facing the patterned conductive layer and electrically connected to the patterned conductive layer.
5. The embedded chip package of claim 3, wherein the build-up circuitry structure is electrically connected to the patterned conductive layer through the conductive via.
6. The embedded chip package of claim 1, wherein the build-up circuitry structure is disposed on the second surface of the glass substrate, the embedded chip package further comprising:
the tin ball or the copper column is configured on the layer-adding circuit structure, so that the tin ball or the copper column and the circuit board are respectively positioned at two opposite sides of the layer-adding circuit structure.
7. The embedded chip package of claim 6, wherein the lower surface of the chip is an active surface facing the build-up circuitry structure and electrically connected thereto.
8. The embedded chip package of claim 1, wherein the through-trench connects the first surface and the second surface of the glass substrate.
9. A package on package structure comprising:
a circuit board;
at least one embedded chip package according to claim 3, disposed on the circuit board; and
the embedded chip package of claim 6, disposed on the embedded chip package of claim 3, wherein the embedded chip package of claim 6 and the circuit board are respectively located at opposite sides of the embedded chip package of claim 3.
10. The package on package structure of claim 9, wherein the solder balls or the copper pillars of the embedded chip package of claim 6 are electrically connected to the build-up circuitry structure of the embedded chip package of claim 3, and the solder balls or the copper pillars of the embedded chip package of claim 3 are electrically connected to the circuit board.
11. A manufacturing method of an embedded chip package comprises the following steps:
providing a carrier and a release layer configured on the carrier;
configuring a chip on the release layer;
configuring a circuit board on the release layer, the circuit board comprising:
the glass substrate is provided with a first surface, a second surface opposite to the first surface and a through groove penetrating through the glass substrate; and
the at least one conductive through hole penetrates through the glass substrate, and two ends of the conductive through hole are respectively flush with the first surface and the second surface of the glass substrate;
after the chip and the circuit board are arranged on the release layer and the chip is embedded in the through groove, a dielectric material layer is formed on the release layer, wherein the dielectric material layer is filled in the through groove and covers the chip;
removing the release layer and the carrier to expose the lower surface of the chip outside the dielectric material layer;
after removing the release layer and the carrier, forming a build-up circuit structure on the circuit board so as to electrically connect the build-up circuit structure with the conductive via, wherein the build-up circuit structure comprises:
a first circuit layer directly contacting either one of the two ends of the conductive via;
a first dielectric layer covering the first circuit layer;
the second circuit layer and the first circuit layer are respectively positioned at two opposite sides of the first dielectric layer; and
at least one first via hole penetrates through the first dielectric layer to electrically connect the first circuit layer and the second circuit layer.
12. The method of fabricating the embedded chip package of claim 11, wherein the lower surface of the chip is flush with the second surface of the glass substrate.
13. The method of claim 11, wherein the build-up circuitry structure is disposed on the first surface of the glass substrate, the method further comprising:
forming a patterned conductive layer on the second surface of the glass substrate, so that the build-up circuit structure and the patterned conductive layer are respectively located on two opposite sides of the glass substrate; and
and forming a solder ball or a copper column on the patterned conductive layer, so that the solder ball or the copper column and the circuit board are respectively positioned at two opposite sides of the patterned conductive layer.
14. The method of claim 13, wherein the lower surface of the chip is an active surface facing the patterned conductive layer and electrically connected to the patterned conductive layer.
15. The method of claim 13, wherein the build-up circuitry structure is electrically connected to the patterned conductive layer through the conductive via.
16. The method of claim 11, wherein the build-up circuitry structure is disposed on the second surface of the glass substrate, the method further comprising:
and forming a solder ball or a copper column on the layer-adding circuit structure, so that the solder ball or the copper column and the circuit board are respectively positioned at two opposite sides of the layer-adding circuit structure.
17. The method of claim 16, wherein the lower surface of the chip is an active surface facing the build-up circuitry structure and electrically connected to the build-up circuitry structure.
18. The method of claim 11, wherein the through-trench connects the first surface and the second surface of the glass substrate.
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| CN113314474A (en) * | 2021-05-27 | 2021-08-27 | 广东工业大学 | Embedded fan-out type packaging structure and processing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201019438A (en) * | 2008-11-07 | 2010-05-16 | Advanced Semiconductor Eng | Structure and process of embedded chip package |
| CN103594386A (en) * | 2012-08-17 | 2014-02-19 | 宏启胜精密电子(秦皇岛)有限公司 | Laminated packaging composition and making method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW201019438A (en) * | 2008-11-07 | 2010-05-16 | Advanced Semiconductor Eng | Structure and process of embedded chip package |
| CN103594386A (en) * | 2012-08-17 | 2014-02-19 | 宏启胜精密电子(秦皇岛)有限公司 | Laminated packaging composition and making method thereof |
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