TWI395318B - Thin stack package using embedded-type chip carrier - Google Patents

Abstract

A 3D electronic packaging structure is provided in this invention. The first electronic device is attached to the second one where the devices toward outward, and then they are embedded in a chip carrier. There are conductive vias in the chip carrier. After connecting the first and the second electronic device to the chip carrier, the vertical interconnections are constructed to make a 3D electronic packaging structure. Moreover, there are no vias in the electronic device which prevents the device from failure in the via-manufacturing processes. Furthermore, the attached chips reduce the packaging height because the junction layers are decreased.

Description

Thin three-dimensional stacked package structure using embedded wafer carrier

The invention relates to a three-dimensional stacked electronic package structure, which uses a wafer carrier as a carrier, and the electronic chip is embedded in the wafer carrier by means of an embedded method and generates a telecommunication connection with the wafer carrier, and the vertical conduction of the telecommunication is carried out by using the wafer. The via holes on the board are connected. The package structure avoids the process of fabricating the via holes on the electronic wafer, and prevents the electronic chip components from being damaged during the process of fabricating the via holes. In addition, the present invention utilizes wafers to be attached to each other, thereby greatly reducing the package height after the three-dimensional stacking and packaging, and achieving the goal of miniaturization of electronic products.

Today's electronic products are aimed at miniaturization, high performance, high precision, high reliability, and high reactivity. To achieve the above objectives, the three-dimensional stacked electronic package structure is a development trend. In each of the three-dimensional stacked package forms, the method of fabricating the via holes in the wafer can shorten the inter-wafer telecommunications transmission path and reduce the noise generated by the signal. However, as the circuit of the electronic product becomes more compact, the distribution density of the circuit components is too high. The size of the circuit is greatly reduced, and the area where the via hole can be formed on the wafer is greatly reduced, and the probability of damage of the wafer element during the via hole fabrication process is also greatly improved. The thin three-dimensional stacked package structure of the embedded wafer carrier proposed by the invention avoids the process of fabricating the via holes on the wafer, can improve the yield of the package, and has the advantages of the via hole shortening the telecommunication transmission path.

A conventional stacked-type integrated circuit chip package, as disclosed in US Pat. No. 6,236,115, discloses a high-density integrated circuit chip package structure, see FIG. 1; the package structure is still formed by wafer stacking, but in order to reduce the use of the bonding wire as described above As a signal delay phenomenon which may occur when the inter-wafer signal is transmitted, the first integrated circuit wafer 101, the second integrated circuit wafer 102, and the third integrated circuit wafer 103 do not form an electrical communication path by the wire bonding operation. The patent is mainly formed by using a plurality of via holes 106 in the wafer, and the metallization line 104 is disposed on the hole wall, and the fixing structure 105 having the conductive property is matched, so that the inter-wafer telecommunications transmission path can be effectively shortened, and the signal generation is reduced. However, this stacking method requires the formation of via holes on the wafer, which has the opportunity to damage the components on the wafer during the fabrication of the via holes, causing damage to the wafer.

In view of the integration of multiple microelectronic components stacked electronic packages with system integration will become the trend of electronic structure modules such as microelectronics, high frequency communication or actuation sensors, and to reduce the technical cost of stacked packages, and to achieve a small package size Objective: How to develop a high-density, high-structure and electrical reliability, and design and assemble a plurality of micro-electronic component packaging structures that can be appropriately adjusted according to the application requirements, which is an urgent problem to be solved.

In view of the lack of the foregoing technologies, and the system-integrated microelectronic component stacked electronic package will become a trend of electronic structure modules such as microelectronics, high frequency communication or actuation sensors, etc., the present invention has the following objects: A three-dimensional stacked electronic package structure of a microelectronic component completed by a wafer carrier. The purpose is to stack the microelectronic components by inserting the wafer into the wafer carrier, improve the working efficiency of the electronic components, and reduce the volume of the electronic package.

Another object of the present invention is to improve the general wafer stack package in which it is necessary to fabricate via holes on the wafer, thereby creating the risk of damaging the wafer components. In the wafer stack package of the present invention, the via holes are distributed on the wafer carrier, so that the process of fabricating the via holes on the wafer can be avoided.

Another object of the present invention is to reduce the height of the wafer stack package structure. In the wafer stack package of the present invention, the first wafer and the second wafer are attached to each other with the electronic components facing outward, and then embedded in the wafer carrier. In this manner, the wafer stack package structure can be highly effectively reduced.

Another object of the present invention is to provide an electronic wafer stack package structure having system integration capability for integrating wafers of different sizes and functions into the same electronic package structure.

To achieve the foregoing objective, the electronic chip stack package structure of the present invention comprises: a single or multiple layers of electronic component carrier, the carrier has at least one hole for inlaying electronic components, and has at least one or more telecommunications a contact pad and a vertical via hole, wherein the via hole is connected to the telecommunications plane of the electronic component carrier, the upper conduction plane and the lower conduction plane; and the first electronic component, the total surface area of the first electronic component is not equal to or equal to the hole of the carrier board And having at least one or a plurality of telecommunication contact pads on the conductive plane of the electronic component and a non-conducting plane having no contact pads; and the second electronic component having a size not equal to or equal to the first electronic component and having at least one or plural The telecommunication contact pads are on the conductive plane of the electronic component and the non-conducting plane having no contact pads, and the first electronic component and the second electronic component are adhered to each other by a non-conducting plane, and the thickness after attachment is equal to the thickness of the electronic component carrier; The first electronic component and the second electronic component attached to each other are embedded in the holes of the electronic component carrier, after being mounted The voids are filled to make the first electronic component conducting plane and the second electronic component conducting plane are respectively aligned with the conductive plane and the lower conducting plane of the electronic component carrier; forming a connection between the first electronic component contact pad and the electronic component carrier a conductive line of the planar contact pad, and thereafter forming a conduction line connecting the second electronic component contact pad and the conductive planar contact pad of the electronic component carrier; and the electronic carrier board together with the first electronic component and the second electronic component as a unit package structure The vertical circuit between the unit packages is formed by the telecommunication connector by using the conductive planar contact pads and the lower conductive planar contact pads on the electronic carrier.

The foregoing and other objects, features, and advantages of the present invention will be more

The invention discloses an electronic wafer stack package structure. In detail, the present invention utilizes a wafer carrier to perform electronic wafer stacking and packaging in a wafer embedded carrier mode, thereby avoiding the fabrication of via holes on the wafer and reducing the risk of damaging the wafer. The embodiments of the present invention are described in detail below, but the preferred embodiments are described herein, and are not intended to limit the invention.

2A to 2C are cross-sectional views showing the manufacturing process of the electronic wafer stacking and packaging unit structure of the present invention for explaining the stacked unit structure of the present invention, which is also the A-A' cross section in FIG. The first electronic component wafer 201 in FIG. 2A, the material composition of the wafer may be tantalum, niobium, tin, carbon, or a combination of the above elements and its semiconductor characteristic elements; the surface 211 is a first electronic component layer, the electron The component can be an active electronic component, a passive electronic component, a sensing component, a test component, a microelectromechanical wafer, or a combination of the above electronic components; the surface 212 is a first electronic component wafer underlayer that does not have any functional electronic components. a second electronic component wafer 202, the material composition of which may be tantalum, niobium, tin, carbon, or a combination of the above elements and its semiconductor characteristic elements; the surface 213 is a second electronic component layer, which may be active Electronic component, passive electronic component, sensing component, test component, microelectromechanical wafer or a combination of the above electronic components; surface 214 is a second electronic component wafer underlayer that does not have any functional electronic components. The first electronic component wafer 201 and the second electronic component wafer 202 are adhered to each other by the adhesive 203 with the first electronic component underlayer 212 and the second electronic component underlayer 214.

As shown in FIG. 2B, the two mutually attached two wafers are embedded in a wafer carrier 206, which is a pre-prepared substrate, which may be made of yttrium, lanthanum, tin, carbon, or a mixture of the above elements. Or in combination with a semiconductor characteristic element, or a polymer material such as an epoxy material or a polyamide material, or a ceramic substrate. The pre-prepared wafer carrier has a hole having a larger size than the first electronic component chip and the second electronic component wafer, and a via hole 205 is prepared in advance in the wafer carrier, and the via hole can be mechanically drilled. Hole, laser drilling, dry-wet etching or other suitable method; the conductive metal filled in the via hole may be tin, silver, gold, aluminum, tantalum, copper, nickel, tantalum, tungsten or above. A combination of an alloy or a material that is electrically conductive. After the two wafers attached to each other are embedded in the holes of the wafer carrier 206, the gap between the wafer and the holes is filled with the filler 204, and the filler 204 can be a non-conductive polymer material.

As shown in FIG. 2C, after the two wafers are embedded in the wafer carrier, the cover layer 209 is covered on the surface of the electronic component layer and the wafer carrier by a coating process, etc.; the first electronic component layer 211 and the second electronic component layer 213 The electrical contact pad 207 is disposed on the circuit for transmitting the internal circuit of the electronic component and the external signal. The wire layer 208 above the electrical contact pad is formed by sputtering, electroplating or other suitable method, and the first electronic component is formed. The circuit signals on the chip 201 and the second electronic component chip 202 are redistributed to the vias 205 on the wafer carrier 206; thereafter, the fabrication of the telecommunication contacts 210 is completed on the wafer carrier, the telecommunications contacts thereon The telecommunication contact protection layer can be formed by screen printing, stencil printing, tumble coating, inkjet coating, lithography, or other suitable means. After the fabrication of the telecommunication contacts is completed on both sides of the via hole, the electronic chip stack package unit structure 200 proposed by the present invention is completed. As depicted in Figure 2C-1, the telecommunication contacts may not be located above or below the vias, but at any location on the wafer carrier.

FIG. 3 is a top view of the electronic wafer stack package structure proposed by the present invention. After the wafer 301 is embedded in the wafer carrier 306, the gap between the wafer and the void is filled with the filler 304, and the filler 304 can be a non-conductive polymer material. The chip 301 is provided with a telecommunication contact pad 307, which is a way for the internal circuit of the electronic component to transmit external signals. The wire layer 308 above the telecommunication contact pad is formed by sputtering, electroplating or other suitable method, and the wafer 301 is formed. The circuit signals are redistributed onto the wafer carrier 306; the fabrication of the telecommunications contacts 310 is then completed on the wafer carrier.

4A to 4C are second embodiment of the present invention, which is an electronic chip stack package unit structure of the present invention. The first electronic component wafer 401 and the second electronic component wafer 402 in FIG. 4A, wherein the first electronic component wafer size is not equal to the second electronic component wafer, and the first electronic component bottom layer and the second electronic component bottom layer are made by the adhesive 403 Attached to each other. As shown in FIG. 4B, the aforementioned two wafers attached to each other are embedded in the wafer carrier 406. The pre-prepared wafer carrier has a hole having a larger size than the first electronic component wafer and the second electronic component wafer, and the via hole 405 is prepared in advance in the wafer carrier. After the two wafers attached to each other are embedded in the holes of the wafer carrier 406, the gap between the wafer and the holes is filled with the filling adhesive 404, and the gap between the first electronic component wafer 401 and the second electronic component wafer 402 is also Filled with filler 404. As shown in FIG. 4C, after the two wafers are embedded in the wafer carrier, the cover layer 409 is covered on the surface of the electronic component layer and the wafer carrier by a coating process; the first electronic component wafer and the second electronic component wafer are cloth-coated. The electrical contact pad 407 is a way for the internal circuit of the electronic component to transmit external signals. The wire layer 408 above the electrical contact pad is formed by sputtering, electroplating or other suitable method, and the first electronic component chip 401 is formed. The circuit signals on the second electronic component wafer 402 are redistributed to the vias 405 on the wafer carrier 406; thereafter, the fabrication of the telecommunications contacts 410 is completed on the wafer carrier. After the fabrication of the telecommunication contacts is completed on both sides of the via holes, the electronic wafer stack package unit structure 400 of the present invention is completed. As depicted in Figure 4C-1, the telecommunication contacts may not be located above or below the vias, but at any location on the wafer carrier.

FIG. 5 is a cross-sectional view showing a third embodiment of the present invention for performing stacked package using the electronic chip stack package unit structure of the present invention. The first stacked package unit 510, the second stacked package unit 520, and the third stacked package unit 530 connect the circuit signals between the stacked package units by using the telecommunication contacts 501, 502, and 503. The telecommunication contact 501 is used to connect the telecommunication of the first stacked package unit 510 and the second stacked package unit 520; the telecommunication contact 502 is used to connect the telecommunication of the second stacked package unit 520 and the third stacked package unit 530; the telecommunication contact The 503 is used for connecting the telecommunications between the third stacked package unit 530 and the substrate 504. The substrate 504 is electrically connected to the external circuit by using the telecommunication contact 505 to complete the electronic component wafer stacking and packaging. The foregoing description of the preferred embodiments is merely illustrative and not intended to limit the invention.

Figure 6 is a cross-sectional view showing a fourth embodiment of the present invention for stacking and packaging using the electronic chip stack package unit structure of the present invention. The first stacked package unit 610, the second stacked package unit 620, and the third stacked package unit 630 connect the circuit signals between the stacked package units by using the bonding material 601 and the telecommunication contacts 602 and 603 of the telecommunication transmission. The bonding material 601 can be an anisotropic conductive tape. The bonding material 601 is used to connect the telecommunication of the first stacked package unit 610 and the second stacked package unit 620; the telecommunication contact 602 is used to connect the telecommunication of the second stacked package unit 620 and the third stacked package unit 630; the telecommunication contact 603 The 604 is connected to the telecommunications between the third stacking and packaging unit 630 and the substrate 604. The substrate 604 is electrically connected to the external circuit by using the telecommunication contact 605 to complete the electronic component wafer stacking and packaging. The foregoing description of the preferred embodiments is merely illustrative and not intended to limit the invention.

The preferred embodiments of the present invention are described above, and the technical scope of the present invention can be modified without departing from the spirit of the present invention. The scope of patent protection is further dependent on the scope of the patent application and its equivalent fields. set.

101. . . First integrated circuit chip

102. . . Second integrated circuit chip

103. . . Third integrated circuit chip

104. . . Metallized line

105. . . Fixing structure

106. . . Via

200. . . Electronic chip stack package unit structure

201. . . First electronic component chip

202. . . Second electronic component chip

203. . . Viscose

204. . . Filler

205. . . Via

206. . . Wafer carrier

207. . . Telecommunications contact pad

208. . . Wire layer

209. . . Cover layer

210. . . Telecommunications contact

211. . . First electronic component layer

212. . . First electronic component wafer bottom layer

213. . . Second electronic component layer

214. . . Second electronic component wafer bottom layer

301. . . Electronic component chip

304. . . Filler

306. . . Wafer carrier

307. . . Telecommunications contact pad

308. . . Wire layer

310. . . Telecommunications contact

400. . . Electronic chip stack package unit structure

401. . . First electronic component chip

402. . . Second electronic component wafer

403. . . Viscose

404. . . Filler

405. . . Via

406. . . Wafer carrier

407. . . Telecommunications contact pad

408. . . Wire layer

409. . . Cover layer

410. . . Telecommunications contact

411. . . First electronic component layer

412. . . First electronic component wafer bottom layer

413. . . Second electronic component layer

414. . . Second electronic component wafer bottom layer

501. . . Telecommunications contact

502. . . Telecommunications contact

503. . . Telecommunications contact

504. . . Substrate

505. . . Telecommunications contact

510. . . First stacked package unit

520. . . Second stacked package unit

530. . . Third stacked package unit

601. . . Bonding material with telecommunications

602. . . Telecommunications contact

603. . . Telecommunications contact

604. . . Substrate

605. . . Telecommunications contact

610. . . First stacked package unit

620. . . Second stacked package unit

630. . . Third stacked package unit

The preferred embodiment of the present invention will be explained in more detail in the following description with the following figures:

FIG. 1 is a schematic diagram of a conventional high-density integrated circuit chip package structure formed by wafer drilling.

2A to 2C are cross-sectional views showing the manufacturing process of the electronic chip stack package unit structure of the present invention (A-A' cross section of FIG. 3).

Figure 2C-1 shows a variant of the first embodiment of the invention in which the telecommunication contacts may not be above or below the vias.

FIG. 3 is a top view of the electronic wafer stack package structure proposed by the present invention.

4A to FIG. 4C are cross-sectional views showing a second embodiment of the present invention, which is a manufacturing process of the electronic chip stack package unit structure of the present invention.

Figure 4C-1 is a variation of the second embodiment of the present invention, wherein the telecommunication contacts may not be above or below the vias.

FIG. 5 is a cross-sectional view showing a third embodiment of the present invention for performing stacked package using the electronic chip stack package unit structure of the present invention.

Figure 6 is a cross-sectional view showing a fourth embodiment of the present invention for stacking and packaging using the electronic chip stack package unit structure of the present invention.

200. . . Electronic chip stack package unit structure

201. . . First electronic component chip

202. . . Second electronic component wafer

203. . . Viscose

204. . . Filler

205. . . Via

206. . . Wafer carrier

207. . . Telecommunications contact pad

208. . . Wire layer

209. . . Cover layer

210. . . Telecommunications contact

211. . . First electronic component layer

213. . . Second electronic component layer

Claims (20)

An electronic package structure comprising: at least one or more layers of electronic component carriers, the carrier has at least one hole for inlaying electronic components, and has at least one or more telecommunication contact pads and vertical vias, The via hole is connected to the telecommunications plane of the electronic component carrier, and the telecommunications plane of the upper conduction plane and the lower conduction plane; the first electronic component, the first electronic component has a total surface area equal to or not equal to the hole of the carrier board, and has at least one or a plurality of telecommunications The contact pad is on the conductive plane of the electronic component and has a non-conducting plane without the contact pad; the second electronic component has a size equal to or not equal to the first electronic component, and has at least one or a plurality of telecommunication contact pads on the conductive plane of the electronic component And the non-conducting plane without the contact pad, the first electronic component and the second electronic component are attached to each other by a non-conducting plane, and the thickness after attachment is equal to or close to the thickness of the electronic component carrier; the first electrons attached to each other The component and the second electronic component are embedded in the hole of the electronic component carrier, and the void is filled after the inlay is made The conduction plane of the electronic component and the conduction plane of the second electronic component respectively have the same level of plane height as the conduction plane and the lower conduction plane of the electronic component carrier; forming a contact plane contact pad between the first electronic component contact pad and the electronic component carrier. The conductive line is followed by a conductive line connecting the second electronic component contact pad and the conductive planar contact pad under the electronic component carrier. The electronic package structure of claim 1, wherein the electronic component carrier may be made of yttrium, lanthanum, tin, carbon, or a combination of the above elements or a combination of other semiconductor characteristic elements. The electronic package structure of claim 1, wherein the electronic component carrier is made of a polymer material such as an epoxy material or a polyamide material. The electronic package structure of claim 1, wherein the electronic component carrier is made of a ceramic substrate. The electronic package structure of claim 1, wherein the electronic component can be an active electronic component, a passive electronic component, a sensing component, a test component, a microelectromechanical wafer, or a combination of the above electronic components. The electronic package structure of claim 1, wherein the via holes are formed by, for example, mechanical drilling, laser drilling, dry-wet etching, or other suitable means. The electronic package structure of claim 1, wherein the conductive hole filled in the conductive metal may be tin, silver, gold, aluminum, tantalum, copper, nickel, tantalum, tungsten or the like. Or a combination of materials that he has electrically conductive. The electronic package structure of claim 1, wherein the telecommunications contact is formed by screen printing, stencil printing, roller coating, inkjet coating, lithography or other suitable means. Telecommunications contact protection layer. The electronic package structure of claim 1, wherein the telecommunication contact is connected to the test signal of the internal electronic component of the package structure to form an electronic package structure with a test function. A three-dimensional stacked electronic package structure, the structure comprising at least: a single or a plurality of layers of electronic component carriers, the carrier has at least one hole for inlaying electronic components, and has at least one or more telecommunication contact pads and vertical conduction a hole, the via hole is connected to the telecommunications plane, the upper conduction plane and the lower conduction plane telecommunications; the first electronic component, the first electronic component has a total surface area equal to or not equal to the hole of the carrier board, and has at least one or more a telecommunication contact pad on the conductive plane of the electronic component and a non-conducting plane having no contact pad; the second electronic component having a size equal to or not equal to the first electronic component and having at least one or a plurality of telecommunication contact pads on the electronic component a conductive plane, and a non-conducting plane having no contact pads, the first electronic component and the second electronic component are attached to each other by a non-conducting plane, and the thickness after attachment is equal to or close to the thickness of the electronic component carrier; An electronic component and a second electronic component are embedded in the holes of the electronic component carrier, and the voids are formed after the inlay Fully making the first electronic component conduction plane and the second electronic component conduction plane have the same level of planar height as the conduction plane and the lower conduction plane of the electronic component carrier; forming a connection between the first electronic component contact pad and the electronic component carrier a conductive line of the planar contact pad, and thereafter forming a conduction line connecting the second electronic component contact pad and the conductive planar contact pad of the electronic component carrier; and the electronic carrier board together with the first electronic component and the second electronic component as a unit package structure The vertical circuit between the unit packages is formed by the telecommunication connector by using the conductive planar contact pads and the lower conductive planar contact pads on the electronic carrier. A three-dimensional stacked electronic package structure having a plurality of package unit bodies as claimed in claim 10, wherein the electronic component carrier board may have a material composition element of yttrium, lanthanum, tin, carbon, or a mixture of the above elements or He has a combination of semiconductor characterization elements. A three-dimensional stacked electronic package structure having a plurality of package unit bodies as claimed in claim 10, wherein the electronic component carrier plate has a material composition of a polymer material such as an epoxy material or a polyamide material. A three-dimensional stacked electronic package structure having a plurality of package unit bodies as claimed in claim 10, wherein the electronic component carrier plate has a material composition of a ceramic substrate. A three-dimensional stacked electronic package structure having a plurality of package unit bodies as claimed in claim 10, wherein the electronic components are active electronic components, passive electronic components, sensing components, test components, MEMS or above A combination of components. A three-dimensional stacked electronic package structure having a plurality of package unit bodies as claimed in claim 10, wherein the through holes are formed by using mechanical drilling, laser drilling, dry-wet etching or other suitable methods. . A three-dimensional stacked electronic package structure having a plurality of package unit bodies as claimed in claim 10, wherein the conductive holes filled in the conductive holes may be tin, silver, gold, aluminum, bismuth, copper or nickel. , tantalum, tungsten or a combination of a metal material of the above or a material of its kind. A three-dimensional stacked electronic package structure having a plurality of package unit bodies, wherein the telecommunications contacts can be screen-printed, stencil-printed, drum-coated, ink-jet coated, and the like. The lithography or other suitable means forms a telecommunication contact protection layer. The three-dimensional stacked electronic package structure of the plurality of package unit bodies, wherein the telecommunications contact is connected to the test signal of the internal electronic components of the package structure to form a test function electronic component. Package structure. A three-dimensional stacked electronic package structure having a plurality of package unit bodies as claimed in claim 10, wherein the vertical telecommunication universal telecommunication connector is a leaded and lead-free solder joint. The three-dimensional stacked electronic package structure of the plurality of package unit bodies of claim 10, wherein the vertical telecommunication universal telecommunication connector can be an anisotropic conductive tape or other conductor with similar functions.