TW201017864A - Thin stack package using embedded-type chip carrier - Google Patents

Thin stack package using embedded-type chip carrier Download PDF

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TW201017864A
TW201017864A TW097139654A TW97139654A TW201017864A TW 201017864 A TW201017864 A TW 201017864A TW 097139654 A TW097139654 A TW 097139654A TW 97139654 A TW97139654 A TW 97139654A TW 201017864 A TW201017864 A TW 201017864A
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Taiwan
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electronic
electronic component
plane
wafer
telecommunication
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TW097139654A
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Chinese (zh)
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TWI395318B (en
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Chan-Yen Chou
Ming-Chih Yew
Kuo-Ning Chiang
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Kuo-Ning Chiang
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A 3D electronic packaging structure is provided in this invention. The first electronic device is attached to the second one where the devices toward outward, and then they are embedded in a chip carrier. There are conductive vias in the chip carrier. After connecting the first and the second electronic device to the chip carrier, the vertical interconnections are constructed to make a 3D electronic packaging structure. Moreover, there are no vias in the electronic device which prevents the device from failure in the via-manufacturing processes. Furthermore, the attached chips reduce the packaging height because the junction layers are decreased.

Description

201017864 六、發明說明： 【發明所屬之技術領域】 本發明係錢-種立断#電子難結構 =載板作誠具，電子^ _職人方式埋人 ，曰曰片載板產生電訊連結，電訊垂直方向導通則利二= 板上之導通孔連結。此封裝結構避免於電子 ^本發明_晶片相互_方式進行封裝，可大 堆叠封裝後的封裝高度，達到f子產品小型化的目標。- 心現Λ電子產品多以符合小型化、高性能、高精度、高俨 if展之趨勢。在各個立體堆#封裝形式中，5 =訊f產^雜訊的情形，__電子產品之^ 路凡件之分佈密度過高、電路之體精 :電 ，導通孔的區域將大幅縮減，導通孔製作過程^日^可= ===高。本發明所提出之嵌入式晶 ❹ ίί鞋H裝構避免在晶片上製作導通孔的製程，可接 门、、’同時兼具導通孔縮短電訊傳遞路徑等優點。 【先前技術】 fi娜習上"!堆疊型積體電路晶片封裝如美國專利宋躲 現象，第一積ΐίί曰號時所可能產生之訊號延遲 積體電路晶片103門、，一積體電路晶片102與第三 要利用複數鱗^ 線作業形成電連通路。該專利主 通孔106軸於晶片中，同時於孔壁佈上金屬 201017864 化線路104，並配合具導電特性之固著結構1〇5，故可有效縮 短晶片間電訊傳遞路徑，減少訊號產生雜訊之情形；然而此堆 疊方式需要在晶片上製作導通孔’在導通孔的製作過程中有機 會損害晶片上的元件，造成晶片的損毀。 有機201017864 VI. Description of the invention: [Technical field of invention] The invention is a money-type vertical break #电子难结构=carrier board for honesty, electronic ^ _ staff mode buried, sputum carrier board generates telecommunications link, telecommunications Conducting in the vertical direction is the connection of the via holes on the board. The package structure is prevented from being packaged by the electronic method of the present invention, and the package height after the package is large, and the target of miniaturization of the f sub-product is achieved. - The electronic products are mostly in line with the trend of miniaturization, high performance, high precision, and high-definition. In each three-dimensional stack # package form, 5 = the situation of the noise, the distribution density of the electronic product is too high, the body of the circuit is fine: the area of the via hole will be greatly reduced, Via hole fabrication process ^ day ^ can = = = = high. The embedded crystal H 鞋 H H 装 装 避免 避免 避免 避免 避免 H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H [Prior Art] Fi Na Xi "! Stacked integrated circuit chip package, such as the US patent Song hiding phenomenon, the first possible accumulation of signal delay delay integrated circuit chip 103 gate, an integrated circuit The wafer 102 and the third are to be electrically connected by a plurality of scales. The patent main via 106 is axially mounted on the wafer, and the metal 201017864 line 104 is placed on the hole wall, and the fixed structure 1〇5 with conductive characteristics is used, thereby effectively shortening the inter-wafer telecommunications transmission path and reducing signal generation. However, this stacking method requires the fabrication of vias on the wafers. During the fabrication of the vias, there is a chance to damage the components on the wafer, causing damage to the wafer. organic

鑑於具系統整合之多個微電子元件堆疊電子封裝將成為 微電子、尚頻通訊或致動感測器等電子結構模組之趨勢，並^ 為減低堆疊封裝之技術成本，與達成封裝體積微小化之目的， 如何發展出一種高密度、高結構與電性可靠度，同時設計、組 裝可依據應用需求功能作適當彈性調整之多個微電子元件封 裝結構，實為當前急需解決的問題。 【發明内容】 鑑於别述技術之缺失，且具系統整合之微電子元件堆疊 電子封裝·將成為微電子、尚頻通訊或致動感測器等，電子纟士構 模組之趨勢，本發明具有以下之目的： 本發明提出一利用晶片載板完成之微電子元件立體堆疊 電子封裝結構。其目的在於利用晶片嵌入晶片載板的方式進行 微電子元件之堆疊’提高電子元件工作效能，縮減電子封裝體 體積。 本發明另一目的在於改善一般的晶片堆疊封裝中，需要 f晶片上製作導通孔，進而產生破壞晶片元件的風險。本發明 提出之晶片堆疊封裝巾’導通孔乃分佈於晶片触上，故^以 避免於晶片上製作導通孔的製程。 本發明之另一目的在於減少晶片堆疊封裝結構高度。本 發明提出之晶片堆疊封裝中，第一晶片和第二晶片以電子元件 朝外之方式相互貼附，再嵌入晶片載板中，利用該方 片堆疊封裝結構高度有效降低。 201017864 本發明之另一目的在於提供一種 構’該結構具有系統整合能力，將不同 曰曰片堆疊封裝結 合至同一電子封裝結構中。 寸不同功能之晶片整 ❿ 為達成前述目的，本發明所提出之 構，包含有··單或複數層電子元件载板堆疊封裝結 孔用以鑲嵌電子元件，並至少具有單 ^ 至J具有一空 觸塾及垂直導通孔，導通孔連接電子元上電訊接點接 及下導通平面m電子中=導通平面 面積不等於或等於上職板之1第一電子元件總表 訊接觸墊於電子元件料伟Γ及不複數個電 具接二電第簡電觸子 :通平面相互附t，附著後厚度等η以 Βΐί£-— :元件接觸導塾通與平電面子接 執刹:H用電子餘上導通平面接觸墊、τ導通平面接觸 】用電訊連接體形解傾裝體_直電路導通。 發明，前述及其他目的、特徵、以及優點，將藉由下 中參照圖不之較佳實施例之詳細說明得以更明確。 5 201017864 【實施方式】 本發明揭露一種電子晶片堆疊封裝結構。詳言之，本發 明利用一晶片載板’以晶片嵌入載板方式進行電子晶片堆疊封 裝’避免於晶片上製作導通孔，降低破壞晶片之風險。該發明 之實施例詳細說明如下，唯所述之較佳實施例做一說明，並非 用以限定本發明。In view of the integration of multiple microelectronic components stacked electronic packages with system integration will become the trend of electronic structure modules such as microelectronics, frequency communication or actuation sensors, and to reduce the technical cost of stacked packages and achieve miniaturization of package size. The purpose is how to develop a high-density, high-structure and electrical reliability, and at the same time design and assemble a plurality of micro-electronic component packaging structures that can be appropriately adjusted according to the application requirements, which is an urgent problem to be solved. SUMMARY OF THE INVENTION In view of the lack of other technologies, and the systematic integration of microelectronic components stacked electronic packages, which will become microelectronics, frequency communication or actuating sensors, etc., the trend of electronic gentleman modules, the present invention has The following objects: The present invention provides a three-dimensional stacked electronic package structure of a microelectronic component completed by a wafer carrier. The purpose is to stack the microelectronic components by inserting the wafer into the wafer carrier board to improve the operating efficiency of the electronic component and reduce the volume of the electronic package. Another object of the present invention is to improve the fabrication of vias on a f-wafer in a conventional wafer-stack package, thereby creating the risk of damaging the wafer components. The via-stack of the wafer-stacked package of the present invention is distributed on the wafer, so that the process of fabricating the via-hole on the wafer is avoided. Another object of the present invention is to reduce the height of the wafer stack package structure. In the wafer stack package of the present invention, the first wafer and the second wafer are attached to each other with the electronic components facing outward, and then embedded in the wafer carrier, and the package structure is highly effectively reduced by the chip. 201017864 Another object of the present invention is to provide a structure that has system integration capabilities to combine different wafer stack packages into the same electronic package structure. In order to achieve the foregoing objective, the present invention provides a structure comprising a single or multiple layers of electronic component carrier board package package junction holes for inlaying electronic components, and having at least one single to one J having an empty The contact hole and the vertical via hole are connected to the telecommunications contact point on the electronic component and the lower conduction plane m. The area of the conduction plane is not equal to or equal to the first electronic component of the upper board. Wei Wei and no number of electric tools are connected to the second electric simple contact: the planes are attached to each other, and the thickness after attachment is η Βΐ £ £ £ : : : : : : : : 元件 元件 元件 元件 元件 元件 元件 元件 元件 元件 元件 元件 元件 元件 元件 元件 元件 元件 元件 元件 元件 元件 元件 元件Remaining conduction plane contact pad, τ conduction plane contact] using a telecommunication connection body to resolve the tilting body _ straight circuit conduction. The above and other objects, features, and advantages of the invention will be apparent from the appended claims. [2010] [Embodiment] The present invention discloses an electronic wafer stack package structure. In particular, the present invention utilizes a wafer carrier board to perform electronic wafer stack mounting in a wafer-embedded carrier mode to avoid fabrication of vias on the wafer, reducing the risk of damaging the wafer. The embodiments of the present invention are described in detail below, but the preferred embodiments are not described to limit the invention.

圖二A至圖二C為本發明之電子晶片堆疊封裝單元結構 製作過程截面圖，用以闡述本發明之堆疊單元結構，亦是圖三 中A-A’截面。圖二A中第一電子元件晶片2〇1，該晶片其材料 組成可為矽、鍺、錫、碳，或以上元素與它種具半導體特性元 素之組合；表面211為第一電子元件層，該電子元件可為主動 電子元件、被動電子元件、感測元件、測試元件、微機電晶片 或以上電子元件之組合；表面212為第一電子元件晶片底層， ，底層不具任何功能性電子元件。第二電子元件晶片2〇2，該 晶片其材料組成可為矽、鍺、錫、碳，或以上元素與 j體特性元素之組合；表面灿為第二電子元4與 件可為主動電子％件、被動電子元件、感測元件、測試元件、 =電晶上電子元件之組合；表面214衫二件 t片底層’該底層不具任何魏性電子元件。上述第一電子元 件f片201及第二電子元件晶片2G2利用黏膠2()3使第 讀底層212及第二電子元件底層214坡貼附。 杯？ηΓΓ:B中所緣’將前述相互貼附之二晶片嵌入晶片載 g 206山中’該晶片載板為預先製備之基板，其材料可為梦、錯戰 之混合或無半導體特性元素之組 製備導通孔2。5 孔於= 6 201017864 式蝕刻或其他適合之方式形成；導通孔其内部所充填之導電金 屬可為錫、銀、金、銘、鈹、銅、錄、姥、鶴或以上金屬材料 合金或他種具導電性之材料的組合。將上述相互貼附之二晶片 嵌入晶片載板206之空孔後’晶片與空孔間的空隙利用填充膠 204填滿，填充膠204可為不具導電性之高分子材料。2A to 2C are cross-sectional views showing the manufacturing process of the electronic chip stack package unit structure of the present invention for explaining the structure of the stacked unit of the present invention, which is also the A-A' cross section in FIG. The first electronic component wafer 2〇1 in FIG. 2A, the material composition of the wafer may be tantalum, niobium, tin, carbon, or a combination of the above elements and its semiconductor characteristic elements; the surface 211 is a first electronic component layer. The electronic component can be an active electronic component, a passive electronic component, a sensing component, a test component, a microelectromechanical wafer, or a combination of the above electronic components; the surface 212 is a first electronic component wafer bottom layer, and the bottom layer does not have any functional electronic components. The second electronic component wafer 2〇2, the material composition of the wafer may be yttrium, lanthanum, tin, carbon, or a combination of the above elements and the j-body characteristic elements; the surface may be the second electron element 4 and the component may be the active electron% Piece, passive electronic component, sensing component, test component, = combination of electronic components on the surface; surface 214 shirt two pieces of t-layer bottom layer 'the bottom layer does not have any Wei electronic components. The first electronic component f-chip 201 and the second electronic component wafer 2G2 are attached to the first underlayer 212 and the second electronic component underlayer 214 by the adhesive 2 () 3 . cup? ΓΓΓΓ: The edge of B is embedded in the wafers attached to the wafers in the g 206 mountain. The wafer carrier is a pre-prepared substrate, and the material can be a combination of dreams, mismatches or semiconductor-free elements. The via hole is formed by etch or other suitable method; the conductive metal filled in the via hole may be tin, silver, gold, m, 铍, copper, ruthenium, ruthenium, crane or above metal. A combination of a material alloy or a material of its kind. After the two wafers attached to each other are embedded in the holes of the wafer carrier 206, the gap between the wafer and the voids is filled with the filling adhesive 204, and the filler 204 can be a non-conductive polymer material.

參 如圖一 C所繪，上述一晶片嵌入晶片載板後，利用塗佈 等製程將覆蓋層209覆蓋於電子元件層及晶片載板之表面；第 -電子元件層211及第二電子元件層213上佈有電訊號接觸塾 207，為電子元件内部電路與外部訊號傳遞之途徑，位於電訊 號接觸塾上方之導線層208 ’以濺鑛、電鑛或其他適合之方式 形成，並將第-電子元件晶片2()1及第二電子元件晶片2〇2上 之電路讯號重新分佈至晶片載板206上的導通孔2〇5 ;其後於 曰曰片載板上元成電訊接點21〇的製作，所述之電訊接點，其上 可利用網版印刷、模板物、滚筒式塗佈、喷墨塗佈、微g技 術或其他適合之方式形成電訊接點保護層。於導通孔兩侧完成 電訊接點的製作後，完成本發明提&之電子晶牌叠封裝單元 結構200。如圖二c-Ι所繪，電訊接點可不位於導通 或下方，而位於晶片載板上任意位置。 上方 圖三為本發明提出之電子晶片堆疊封裝結構上視圖。晶 H1 ίΐΐΐ載板306後，晶片與空孔間的空隙利用填充膠 304填滿，填充膠3〇4可為不具導電性之高分子材料。晶片3〇1 ίΪίΐ訊3〇7 ’為電子元件内部電路與外部訊號傳 ίίί二ί電訊號接輕上方之導線層308，以着、電 鑛或其他適合之方式形成，並將晶片301上之電路訊號重新分 以 子晶綱封襄單元結;“:=元 7 201017864 及第二電子元件晶片402，其中第一電子元件晶片尺寸大小不 等於第二電子元件晶片，利用黏膠403使第一電子元件底層及 第二電子元件底層相互貼附。如圖四B中所繪，將前述相互貼 附之二晶片嵌入晶片載板406中。於該預先製備之晶片載板中 具有一空孔，該空孔尺寸大於前述之第一電子元件晶片及第二 電子元件晶片，於晶片載板中預先製備導通孔405。將上述相 互貼附之二晶片叙入晶片載板406之空孔後，晶片與空孔間的 空隙利用填充膠404填滿，此外第一電子元件晶片4〇1與第二As shown in FIG. 1C, after the wafer is embedded in the wafer carrier, the cover layer 209 is covered on the surface of the electronic component layer and the wafer carrier by a coating process; the first electronic component layer 211 and the second electronic component layer. The 213 is provided with a telecommunication contact 207, which is a way for the internal circuit of the electronic component to transmit external signals. The wire layer 208' located above the telecommunication contact port is formed by splashing, electric ore or other suitable method, and will be - The circuit signals on the electronic component chip 2 () 1 and the second electronic component chip 2 重新 2 are redistributed to the via holes 2 〇 5 on the wafer carrier 206; thereafter, the slab carrier is turned into a telecommunication contact. 21 〇 fabrication, the telecommunications contact, on which the telecommunication contact protection layer can be formed by screen printing, template, roller coating, inkjet coating, microg technology or other suitable means. After the fabrication of the telecommunication contacts is completed on both sides of the via hole, the electronic cell stack package unit structure 200 of the present invention is completed. As shown in Figure 2 c-Ι, the telecommunication contacts may not be on or under, but located anywhere on the wafer carrier. Figure 3 is a top view of the electronic chip stack package structure proposed by the present invention. After the crystal H1 is applied to the carrier 306, the gap between the wafer and the void is filled with the filler 304, and the filler 3〇4 can be a non-conductive polymer material. The chip 3 〇 1 Ϊ ΐ 〇 〇 〇 ' ' ' ' 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子 电子The circuit signal is re-divided into a sub-crystal sealing unit junction; ": = element 7 201017864 and the second electronic component wafer 402, wherein the first electronic component wafer size is not equal to the second electronic component wafer, and the first is made by the adhesive 403 The bottom layer of the electronic component and the bottom layer of the second electronic component are attached to each other. As shown in FIG. 4B, the two wafers attached to each other are embedded in the wafer carrier 406. The pre-prepared wafer carrier has a hole therein. The via hole size is larger than the first electronic component wafer and the second electronic component wafer, and the via hole 405 is prepared in advance in the wafer carrier. After the two wafers attached to each other are introduced into the hole of the wafer carrier 406, the wafer and the wafer are The gap between the holes is filled with the filling glue 404, and further the first electronic component wafer 4〇1 and the second

電子元件晶片402間的空隙亦由填充膠404填滿。如圖四c所 繪，上述二晶片嵌入晶片載板後，利用塗佈等製程將覆蓋層 409覆蓋於電子元件層及晶片載板之表面；第一電子元件晶片 及第二電子元件晶片上佈有電訊號接觸墊4〇7，為電子元;内 部電路與外部訊號傳遞之途徑，位於電訊號接觸墊上方之導 層408，以濺鍍、電鍍或其他適合之方式形成，並將第一 ”子 元件晶片401及第二電子元件晶片402上之電路訊號重新分佑 至晶片載板4G6上的導通孔4〇5 ;其後於晶片載板上 接點410的製作。於導通孔兩侧完成電訊接點的製作後，^ 土發明提出之電子晶片堆疊封裝單元結構·。如圖四J ί任W辦版认咖，驗於晶片载板 冗手截=== 裝：：二第-堆細單元： 號。其中電訊接點5〇Γ用二=各=，元間^ 堆疊封裝單元52。之電及第二 裝單元520及第三堆疊封裝單接;占502用於連結第二堆叠封 於連結第三堆叠封裝單元53η 之電訊，電訊接點503用 利用電訊接點505與外部504間之電訊，基板504 ㈣電路進行電訊連結，完成電子元件晶 201017864The gap between the electronic component wafers 402 is also filled by the filling glue 404. As shown in FIG. 4c, after the two wafers are embedded in the wafer carrier, the cover layer 409 is covered on the surface of the electronic component layer and the wafer carrier by a coating process; the first electronic component wafer and the second electronic component wafer are cloth-coated. The electrical contact pad 4〇7 is an electronic element; the internal circuit and the external signal transmission path are located on the conductive layer 408 above the telecommunication contact pad, formed by sputtering, electroplating or other suitable manner, and the first "" The circuit signals on the sub-element wafer 401 and the second electronic component wafer 402 are re-divided to the via holes 4〇5 on the wafer carrier 4G6; thereafter, the fabrication of the contacts 410 on the wafer carrier is completed on both sides of the vias. After the manufacture of the telecommunications contacts, the structure of the electronic chip stacking and packaging unit proposed by the invention was as follows: Figure 4 J ί 任 版 认 , , , , , , , , , , , , 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片 晶片Fine unit: No. The telecommunications contact 5 uses two = each =, the inter-element ^ stacks the package unit 52. The electricity and the second loading unit 520 and the third stacked package are connected; the 502 is used to connect the second stack Sealed in telecommunications, electricity connected to the third stacked package unit 53n Using the signal contacts 503 with contacts 505 and the external telecommunications 504, the circuit substrate 504 (iv) the telecommunications link, to complete the electronic component crystal 201017864

說明，並非 片堆疊封裝之目的。前迷 用以限定本發明。 圖六為本發明之第四實姑办丨 堆疊封裝單元結構進行*二二I為利用本發明之電子晶片 單元610、第二堆疊封裴單亓截面不意圖。第一堆疊封裝 利用具電訊傳遞之接合材料_ 三堆叠封裝單元630Note that it is not the purpose of chip stacking. The former is used to define the invention. FIG. 6 is a fourth embodiment of the present invention. The structure of the stacked package unit is performed. The two-dimensional I is not intended to utilize the electronic chip unit 610 and the second stacked package of the present invention. First stacked package using bonding material with telecommunications _ three-stack package unit 630

為非等向性導電膠帶。其中接二之接合材料601可 襄單元6丨嶋二_^ ==== =連=第二堆疊封裝單元62G及第三堆疊封裝 間之封裝& 63g及基板6〇4 稱，、做一說明，並非用以限定本發明。 本發明較佳實齡彳說g胁上，*熟悉此領域技蔽，在不 ，離本發明之精神範圍内，當可做些許更動潤飾，1專利保護 範圍更當視後附之申請專利範圍及其等同領域而定。 【圖式簡單說明】 本發明之較佳實施例將於下述說明中辅以下列圖形做更詳細 的閣述： 、 圖一為習知以晶圓鑽孔方式形成之高密度積體電路晶片封裝 結構之示意圖。 圖二A至圖二c為本發明之第一實施例，為本發明電子晶片堆 疊封裝單元結構製作過程截面圖（圖三之A-A’截面）。 圖二C-1為本發明第一實施例之變體，其中電訊接點可不在導 通孔之上方或下方。 201017864 圖三為本發明提出之電子晶片堆疊封裝結構上視圖。 圖四A至圖四C為本發明之第二實施例，為本發明電子晶片 疊封裝單元結構製作過程截面圖。 圖四C-1為本發明第二實施例之變體，其中電訊接點 通孔之上方或下方。 圖五為本發明之第三實施例’為利用本發明之電子 裝單元結構進行堆疊封裝之截面示意圖。 圖六為本發明之第四實施例，為利用本發明之電子晶片堆疊 ❿ 裝單元結構進行堆疊封裝之截面示意圖。 且 【主要元件符號說明】 101 第一積體電路晶片 102 第二積體電路晶片 103 第三積體電路晶片 104 金屬化線路 105 固著結構 106 導通孔 200 電子晶片堆疊封裝單元結構 201 第一電子元件晶片 202 第二電子元件晶片 203 黏膠 204 填充膠 205 導通孔 206 晶片載板 207 電訊號接觸墊 208 導線層 201017864 209 覆蓋層 210 電訊接點 211 第一電子元件層 212 第一電子元件晶片底層 213 第二電子元件層 214 第二電子元件晶片底層 301 電子元件晶片 304 填充膠 306 晶片載板 307 電訊號接觸墊 ❹ 308導線層 310 電訊接點 400 電子晶片堆疊封裝單元結構 401 第一電子元件晶片 402 第二電子元件晶片 403 黏膠 404 填充膠 405 導通孔 406 晶片載板 φ 407 電訊號接觸墊 408 導線層 409 覆蓋層 410 電訊接點 411 第一電子元件層 412 第一電子元件晶片底層 413 第二電子元件層 414 第二電子元件晶片底層 501 電訊接點 502 電訊接點 11 201017864 503 電訊接點 504基板 505 電訊接點 510 第一堆疊封裝單元 520 第二堆疊封裝單元 530 第三堆疊封裝單元 601 具電訊傳遞之接合材料 602 電訊接點 603 電訊接點 604 基板 ❿ 605電訊接點 610 第一堆疊封裝單元 620 第二堆疊封裝單元 630 第三堆疊封裝單元It is an anisotropic conductive tape. The bonding material 601 of the second can be used for the unit 6丨嶋2_======= the second stacked package unit 62G and the third stacked package between the package & 63g and the substrate 6〇4, It is not intended to limit the invention. The present invention is better in terms of age, and is familiar with the technical aspects of the field. If not, within the scope of the spirit of the present invention, when a little more retouching can be done, the scope of patent protection is more closely attached to the patent application scope. And its equivalent field. BRIEF DESCRIPTION OF THE DRAWINGS A preferred embodiment of the present invention will be described in more detail in the following description in the following description: FIG. 1 is a conventional high-density integrated circuit chip formed by wafer drilling. Schematic diagram of the package structure. 2A to 2C are cross-sectional views showing the manufacturing process of the electronic wafer stacking and packaging unit structure of the present invention (A-A' cross section of Fig. 3). Figure 2C-1 shows a variant of the first embodiment of the invention in which the telecommunication contacts may not be above or below the vias. 201017864 FIG. 3 is a top view of the electronic wafer stack package structure proposed by the present invention. 4A to 4C are cross-sectional views showing a second embodiment of the present invention, which is a manufacturing process of the electronic wafer package unit structure of the present invention. Figure 4C-1 shows a variant of the second embodiment of the invention in which the telecommunications contacts are above or below the via. Figure 5 is a schematic cross-sectional view showing a third embodiment of the present invention for stacking and packaging using the electronic unit structure of the present invention. Figure 6 is a cross-sectional view showing a fourth embodiment of the present invention for stacking and packaging using the electronic wafer stacking unit structure of the present invention. And [main element symbol description] 101 first integrated circuit chip 102 second integrated circuit chip 103 third integrated circuit wafer 104 metallized line 105 fixed structure 106 via hole 200 electronic chip stacked package unit structure 201 first electron Component wafer 202 second electronic component wafer 203 adhesive 204 filling adhesive 205 via 206 206 wafer carrier 207 electrical contact pad 208 wire layer 201017864 209 cover layer 210 telecommunication contact 211 first electronic component layer 212 first electronic component wafer bottom layer 213 second electronic component layer 214 second electronic component wafer bottom layer 301 electronic component wafer 304 filler 306 wafer carrier 307 electrical contact pad 308 wire layer 310 telecommunications contact 400 electronic chip stack package unit structure 401 first electronic component wafer 402 second electronic component wafer 403 adhesive 404 filling adhesive 405 via 406 wafer carrier φ 407 electrical contact pad 408 wire layer 409 cover layer 410 telecommunication contact 411 first electronic component layer 412 first electronic component wafer bottom layer 413 Two electronic component layer 414 second electronic component wafer bottom layer 501 telecommunication contact 502 telecommunication contact 11 201017864 503 telecommunication contact 504 substrate 505 telecommunication contact 510 first stacked package unit 520 second stacked package unit 530 third stacked package unit 601 telecommunications transfer material 602 telecommunication contact 603 Telecommunication contact 604 substrate 605 605 telecommunication contact 610 first stacked package unit 620 second stacked package unit 630 third stacked package unit

1212

Claims (1)

201017864 七、申請專利範圍： 1· 一種電子封裝結構，該結構至少包含： 單或複數層電子元件载板’該載板至少具有一空孔用以鑲嵌電 子元件，並至少具有單或複數個以上電訊接點接觸墊及垂直導 通孔，導通孔連接電子元件载板中，上導通平面及下導通平面 之電訊； 第一電子元件，上述第一電子元件總表面積等於或不等於上述 載板之空孔，並至少具有單或複數個電訊接觸墊於電子元件導 通平面’及不具接觸塾之非導通平面；201017864 VII. Patent application scope: 1. An electronic package structure, the structure at least comprising: a single or multiple layers of electronic component carrier board. The carrier board has at least one hole for inlaying electronic components, and has at least one or more telecommunications a contact pad and a vertical via hole, wherein the via hole is connected to the telecommunications plane, the upper conduction plane and the lower conduction plane telecommunications; the first electronic component, the first electronic component has a total surface area equal to or not equal to the hole of the carrier board And having at least one or a plurality of telecommunication contact pads on the conductive plane of the electronic component and a non-conducting plane having no contact; 第二電子元件，該電子元件大小等於或不等於第一電子元件， 並至少具有單或複數個電訊接觸墊於電子元件導通平面，及不 接觸墊之料通平面，第—電子元件及第二電子元件藉由非 f通，面相著’附著後厚鮮於或接近於上述電子元件載 扳之厚度； 之第—電子元件及第二電子元件鑲嵌於電子元 t in，鑲嵌後触孔郎:填滿使第—電子元件導通 及下導子元輸上導通平面 载板下導通恤切__子元件 菸:以;子:裝;構碳其:=電:元件 合或與他種具半導體特性元素之組合碳，或以上凡素之混 13 201017864 4載’其切述電子元件 5·如申請專利範圍第1項之電子封裝結構，其中所 件可為主動電子元件、被動電子元件、感測元件 微機電晶片或以上電子元件之組合。 &件、 6.如申請專利範圍第1項之電子封裝結構，其中所述之 可利用如機械鑽孔、雷射鑽孔、乾溼式蝕刻或其他適合之方 ΊΤ^ Jw 〇 \a second electronic component, the electronic component having a size equal to or not equal to the first electronic component, and having at least one or a plurality of telecommunication contact pads on the conductive plane of the electronic component, and not contacting the material plane of the pad, the first electronic component and the second component The electronic component is non-f-passed, and the surface is thicker than or close to the thickness of the electronic component carrier; the first electronic component and the second electronic component are embedded in the electronic component t in, and the inlaid contact hole is filled: The full-scale electronic component conduction and the lower-conducting sub-element are connected to the conduction plane carrier under the tee-cutting __ sub-component smoke: to; sub-assembly; structure carbon:: electricity: component or with its semiconductor properties The combination of elements, or the combination of the above elements 13 201017864 4 contains 'the description of the electronic components 5 · as claimed in the scope of the electronic package structure of the first item, which can be active electronic components, passive electronic components, sensing Component MEMS wafer or a combination of the above electronic components. &, 6. The electronic package structure of claim 1, wherein the use may be such as mechanical drilling, laser drilling, dry-wet etching or other suitable means J^ Jw 〇 \ 7.如申明專利範圍第1項之電子封裝結構，其中所述之 其内部所充填之導電金屬可為錫、銀、金、銘、鈹、銅 铑、鎢或以上金屬材料合金或他種具導電性之材料的組合/、 8點如ΓίίίΙ翻第1項之f子封裝結構，其中所述之電訊接 上可利用網版印刷、模板印刷、滾筒式塗佈、噴墨塗佈、 微衫技術或其他適合之方式形成電訊接點保護層。7. The electronic package structure according to claim 1, wherein the conductive metal filled in the interior thereof may be tin, silver, gold, samarium, tantalum, copper or the like or an alloy of the above metal materials or other materials thereof. A combination of conductive materials, 8 points, such as 子ίίίΙ, the sub-package structure of the first item, wherein the telecommunications connection can utilize screen printing, stencil printing, drum coating, inkjet coating, micro shirt A telecommunication contact protection layer is formed by technology or other suitable means. i如範圍第1項之電子封裝結構，其中所述之電訊接 Ίΐϊ封裝結構内部電子元件之測試訊號相連通，形成 一具測喊功能之電子封裝結構。 =一體堆#電子職結構，舰少包含： =株，ί電子讀載板’該載板至少具有—空孔用以鑲嵌電 通孔具有單或複數個以上電訊接點接觸整及垂直導 之電訊f11連接電子元件餘巾，上導通平面及下導通平面 第電子7C件’上述第一電子元件總表面積等於或不等於上述 201017864 不電訊接觸墊於電子元件導 二：=====元:， 相絲著，_财度料錢胁上«子 平面、第二電子元件導通平面分 電子兀件導通 及下導通平面具有同-等級的平面高度；她上導通平面 載板下導通平面接觸塾之導通線路;接觸塾與電子元件 以上述電子载板連同第-電子元件、第 上路：通平*接觸$ =合锡、碳，或以上元素之混合或與他：半以： 電子封封立體堆* 材料、聚醯胺材料等高分子材料。 /、材料，，且成可為環氧 電子封裝結構’：述以 =封 15 201017864 基板。 1 電4子私叙立想料 雷早分杜返電子70件可為主動電子元件、被動 HT!' ^ 之立體堆疊 雷射 iSSF=* 16. 了為錫、銀、金、|g、皱、铜、德 守电隹屬 金或他種具導電性之材料的ί合豸錢、料以上金屬材料合 式形成電訊接點賴層。雜錄技錢適合之方 。 S : ，l成二具““功‘之電g封裝“ ^如申請專觀圍第1G項之具複數個封裝單 錯及無=舞二中所述垂直電訊導通用之電訊連接體可為^ 201017864 20.如申請專利範圍第10項之具複數個封裝單元體之立體堆疊 電子封裝結構，其中所述垂直電訊導通用之電訊連接體可為異 向導電膠帶或其他具類似功能之導體。 參i. The electronic package structure of item 1, wherein the test signal of the internal electronic component of the telecommunication interface package structure is connected to form an electronic package structure with a shouting function. = One-piece stack #电子职结构, ship less contains: = strain, ί electronic read carrier board 'The carrier board has at least - holes for inlaid electrical through holes with single or multiple telecommunication contacts to contact the whole and vertical guide telecommunications F11 is connected to the electronic component waste towel, the upper conduction plane and the lower conduction plane electronic part 7C 'the total surface area of the first electronic component is equal to or not equal to the above 201017864 non-telecommunication contact pad on the electronic component guide two: ===== yuan: The phase of the wire, the financial sector of the money, the sub-plane, the second electronic component conduction plane, the electronic component conduction and the lower conduction plane have the same level of plane height; Conduction line; contact 塾 with electronic components with the above electronic carrier board together with the first electronic component, the first way: the leveling * contact $ = tin, carbon, or a mixture of the above elements or with him: half to: electronically seal the three-dimensional stack * Polymer materials such as materials and polyamide materials. /, material, and can be an epoxy electronic package structure ': described as = seal 15 201017864 substrate. 1 electric 4 children privately think about the thunder and early return to the electronic 70 pieces can be active electronic components, passive HT! ' ^ stereo stacked laser iSSF = * 16. For tin, silver, gold, | g, wrinkles The copper, the German shovel is a gold or his kind of conductive material, and the above metal materials form a telecommunications contact layer. Miscellaneous skills are suitable for the party. S : , l into two "power "electric g package" ^ If you apply for the special 1G item, there are multiple package single error and no = the second vertical telecom guide telecommunication connector can be ^ 201017864 20. The three-dimensional stacked electronic package structure of the plurality of package unit bodies according to claim 10, wherein the vertical telecommunication universal telecommunication connector can be an anisotropic conductive tape or other conductor with similar functions. Reference 1717
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013127035A1 (en) * 2012-02-28 2013-09-06 Liu Sheng Fan-out wafer level semiconductor chip three-dimensional stacked package structure and process
CN104733411A (en) * 2014-12-30 2015-06-24 华天科技（西安）有限公司 Three-dimensional wafer level fan-out package-on-package (PoP) structure and manufacturing method thereof

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9171795B2 (en) * 2013-12-16 2015-10-27 Stats Chippac Ltd. Integrated circuit packaging system with embedded component and method of manufacture thereof
CN111584449A (en) * 2020-05-20 2020-08-25 上海先方半导体有限公司 Chip packaging structure and preparation method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5270261A (en) * 1991-09-13 1993-12-14 International Business Machines Corporation Three dimensional multichip package methods of fabrication
US6002177A (en) * 1995-12-27 1999-12-14 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
JP2001077301A (en) * 1999-08-24 2001-03-23 Amkor Technology Korea Inc Semiconductor package and its manufacturing method
US6906403B2 (en) * 2002-06-04 2005-06-14 Micron Technology, Inc. Sealed electronic device packages with transparent coverings
TWI263313B (en) * 2005-08-15 2006-10-01 Phoenix Prec Technology Corp Stack structure of semiconductor component embedded in supporting board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013127035A1 (en) * 2012-02-28 2013-09-06 Liu Sheng Fan-out wafer level semiconductor chip three-dimensional stacked package structure and process
CN103296014A (en) * 2012-02-28 2013-09-11 刘胜 Fan-out wafer level semiconductor chip three-dimensional stacking packaging structure and technology
CN104733411A (en) * 2014-12-30 2015-06-24 华天科技（西安）有限公司 Three-dimensional wafer level fan-out package-on-package (PoP) structure and manufacturing method thereof

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