JP2010153491A5 - Electronic device, manufacturing method thereof, and semiconductor device - Google Patents
Electronic device, manufacturing method thereof, and semiconductor device Download PDFInfo
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- JP2010153491A5 JP2010153491A5 JP2008328256A JP2008328256A JP2010153491A5 JP 2010153491 A5 JP2010153491 A5 JP 2010153491A5 JP 2008328256 A JP2008328256 A JP 2008328256A JP 2008328256 A JP2008328256 A JP 2008328256A JP 2010153491 A5 JP2010153491 A5 JP 2010153491A5
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Description
本発明は、電子装置及びその製造方法、並びに前記電子装置を構成する半導体装置に関する。 The present invention relates to an electronic device, a method for manufacturing the same , and a semiconductor device constituting the electronic device .
そこで本発明は、上述した問題点に鑑みなされたものであり、内部接続端子を構成する対向配置された２つの導電性ボールの位置ずれを小さくすると共に、内部接続端子を構成する導電性ボールの高さばらつきを小さくすることで、内部接続端子を介して電気的に接続される半導体装置間の電気的接続信頼性を向上させることのできる電子装置及びその製造方法、並びに前記電子装置を構成する半導体装置を提供することを目的とする。 Accordingly, the present invention has been made in view of the above-described problems, and while reducing the positional deviation between the two conductive balls arranged opposite to each other that constitute the internal connection terminal, the present invention provides a conductive ball constituting the internal connection terminal. An electronic device that can improve electrical connection reliability between semiconductor devices that are electrically connected via internal connection terminals by reducing height variation, a manufacturing method thereof, and the electronic device are configured. An object is to provide a semiconductor device .
本発明の一観点によれば、上面に第１の内部接続用パッドが形成された第１の配線基板の、前記上面に第１の電子部品を搭載し、第１の半導体装置を形成する第１の半導体装置形成工程と、前記第１の内部接続用パッドに第１の導電性ボールを形成する第１の導電性ボール形成工程と、前記第１の導電性ボールの上部に、前記第１の電子部品よりも上方に位置する平坦面を形成する平坦面形成工程と、下面に第２の内部接続用パッドが形成された第２の配線基板に、第２の電子部品を搭載し、第２の半導体装置を形成する第２の半導体装置形成工程と、前記第２の内部接続用パッドに第２の導電性ボールを形成する第２の導電性ボール形成工程と、前記第１の内部接続用パッドと前記第２の内部接続用パッドとが対向するように前記第１の半導体装置上に前記第２の半導体装置を配置し、前記第１の導電性ボールの平坦面と前記第２の導電性ボールとを接合する導電性ボール接合工程と、を有する電子装置の製造方法が提供される。 According to one aspect of the present invention, the first electronic component is mounted on the upper surface of the first wiring board having the first internal connection pad formed on the upper surface, and the first semiconductor device is formed. A semiconductor device forming step, a first conductive ball forming step of forming a first conductive ball on the first internal connection pad, and the first conductive ball on the first conductive ball. Mounting a second electronic component on a second wiring board having a flat surface forming step for forming a flat surface located above the electronic component and a second internal connection pad formed on the lower surface; A second semiconductor device forming step of forming a second semiconductor device, a second conductive ball forming step of forming a second conductive ball on the second internal connection pad, and the first internal connection And the second internal connection pad are opposed to each other. Placing the second semiconductor device on the body unit, a method of manufacturing an electronic device having a conductive ball bonding step of bonding a flat surface and the second conductive balls of the first conductive ball Is provided.
本発明の他の観点によれば、第１の配線基板と、前記第１の配線基板の上面に設けられた第１の内部接続用パッドと、前記第１の内部接続用パッド上に設けられた第１の導電性ボールと、前記第１の配線基板の上面に搭載された第１の電子部品と、を有し、前記第１の導電性ボール上部に、前記第１の電子部品よりも上方に位置する平坦面が設けられている半導体装置が提供される。 According to another aspect of the present invention, the first wiring board, the first internal connection pad provided on the upper surface of the first wiring board, and the first internal connection pad are provided. And a first electronic component mounted on an upper surface of the first wiring board, and the first conductive ball is located above the first electronic component than the first electronic component. A semiconductor device provided with a flat surface located above is provided .
Claims (20)
前記第１の内部接続用パッドに第１の導電性ボールを形成する第１の導電性ボール形成工程と、 A first conductive ball forming step of forming a first conductive ball on the first internal connection pad;
前記第１の導電性ボールの上部に、前記第１の電子部品よりも上方に位置する平坦面を形成する平坦面形成工程と、 A flat surface forming step of forming a flat surface positioned above the first electronic component on the first conductive ball;
下面に第２の内部接続用パッドが形成された第２の配線基板に、第２の電子部品を搭載し、第２の半導体装置を形成する第２の半導体装置形成工程と、 A second semiconductor device forming step of mounting a second electronic component on a second wiring board having a second internal connection pad formed on the lower surface to form a second semiconductor device;
前記第２の内部接続用パッドに第２の導電性ボールを形成する第２の導電性ボール形成工程と、 A second conductive ball forming step of forming a second conductive ball on the second internal connection pad;
前記第１の内部接続用パッドと前記第２の内部接続用パッドとが対向するように前記第１の半導体装置上に前記第２の半導体装置を配置し、前記第１の導電性ボールの平坦面と前記第２の導電性ボールとを接合する導電性ボール接合工程と、を有する電子装置の製造方法。 The second semiconductor device is disposed on the first semiconductor device so that the first internal connection pad and the second internal connection pad face each other, and the first conductive ball is flattened. And a conductive ball bonding step for bonding the surface and the second conductive ball.
前記モールド樹脂及び前記第１の導電性ボールを研磨し、前記第１の導電性ボールの上部に、前記モールド樹脂から露出する前記平坦面を形成する請求項１記載の電子装置の製造方法。 The method of manufacturing an electronic device according to claim 1, wherein the mold resin and the first conductive ball are polished to form the flat surface exposed from the mold resin on the first conductive ball.
前記平坦面形成工程では、前記平坦面を、前記Ｃｕボールの上部に形成する請求項１乃至７の何れか一項記載の電子装置の製造方法。 The method for manufacturing an electronic device according to claim 1, wherein in the flat surface forming step, the flat surface is formed on an upper portion of the Cu ball.
前記第１の配線基板の上面に設けられた第１の内部接続用パッドと、 A first internal connection pad provided on the upper surface of the first wiring board;
前記第１の内部接続用パッド上に設けられた第１の導電性ボールと、 A first conductive ball provided on the first internal connection pad;
前記第１の配線基板の上面に搭載された第１の電子部品と、を有し、 A first electronic component mounted on the upper surface of the first wiring board,
前記第１の導電性ボール上部に、前記第１の電子部品よりも上方に位置する平坦面が設けられている半導体装置。 A semiconductor device, wherein a flat surface located above the first electronic component is provided on the first conductive ball.
前記平坦面は、前記モールド樹脂から露出している請求項１１又は１２記載の半導体装置。 The semiconductor device according to claim 11, wherein the flat surface is exposed from the mold resin.
前記Ｃｕボールの上部に前記平坦面が設けられている請求項１１乃至１５の何れか一項記載の半導体装置。 The semiconductor device according to claim 11, wherein the flat surface is provided on an upper portion of the Cu ball.
前記半導体装置上に配置された第２の半導体装置と、を有し、 A second semiconductor device disposed on the semiconductor device,
前記第２の半導体装置は、第２の配線基板と、前記第２の配線基板に搭載された第２の電子部品と、前記第２の配線基板の下面に設けられた第２の導電性ボールと、を備え、 The second semiconductor device includes a second wiring board, a second electronic component mounted on the second wiring board, and a second conductive ball provided on a lower surface of the second wiring board. And comprising
前記第１の導電性ボールの前記平坦面に、前記第２の導電性ボールが接合されている電子装置。 An electronic device in which the second conductive ball is bonded to the flat surface of the first conductive ball.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008328256A JP5340718B2 (en) | 2008-12-24 | 2008-12-24 | Manufacturing method of electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008328256A JP5340718B2 (en) | 2008-12-24 | 2008-12-24 | Manufacturing method of electronic device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010153491A JP2010153491A (en) | 2010-07-08 |
| JP2010153491A5 true JP2010153491A5 (en) | 2012-02-09 |
| JP5340718B2 JP5340718B2 (en) | 2013-11-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2008328256A Expired - Fee Related JP5340718B2 (en) | 2008-12-24 | 2008-12-24 | Manufacturing method of electronic device |
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| JP (1) | JP5340718B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8546932B1 (en) * | 2012-08-15 | 2013-10-01 | Apple Inc. | Thin substrate PoP structure |
| US8906743B2 (en) | 2013-01-11 | 2014-12-09 | Micron Technology, Inc. | Semiconductor device with molded casing and package interconnect extending therethrough, and associated systems, devices, and methods |
| CN105556662A (en) * | 2013-07-15 | 2016-05-04 | 英闻萨斯有限公司 | Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001298115A (en) * | 2000-04-13 | 2001-10-26 | Seiko Epson Corp | Semiconductor device, manufacturing method for the same, circuit board as well as electronic equipment |
| JP2005005358A (en) * | 2003-06-10 | 2005-01-06 | Sharp Corp | Connection structure between laminated substrates of semiconductor module |
| JP4322844B2 (en) * | 2005-06-10 | 2009-09-02 | シャープ株式会社 | Semiconductor device and stacked semiconductor device |
| JP5025443B2 (en) * | 2007-12-11 | 2012-09-12 | パナソニック株式会社 | Semiconductor device manufacturing method and semiconductor device |
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- 2008-12-24 JP JP2008328256A patent/JP5340718B2/en not_active Expired - Fee Related
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