TW201822331A - Electronic package - Google Patents

Abstract

Provided is an electronic package, comprising an insulating layer, an electronic element and a conductive bump embedded in the insulating layer, and a circuit structure formed on the insulating layer and electrically connected to the conductive bump, thereby avoiding the use of a conventional board body to reduce the overall package thickness and thus meet the demand for miniaturization.

Description

 Electronic package  

The present invention relates to a semiconductor packaging technology, and more particularly to an electronic package and a method of fabricating the same.

With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, and in order to improve electrical functions and save packaging space, flip chip technology has been developed.

FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package 1. As shown in FIG. 1, the semiconductor package 1 is first provided with a package substrate 10 having a board body 10a and a line structure 10b, and then a semiconductor device 11 is bonded to the line structure 10b by flip chip bonding. An encapsulant 13 is formed on the package substrate 10 to encapsulate the semiconductor element 11.

Specifically, the semiconductor device 11 has an opposite active surface 11a and a non-active surface 11b. The active surface 11a has a plurality of electrode pads 110 for electrically connecting the electrode pads 110 and the circuit structure 10b by a plurality of solder bumps 12, for example. The circuit layer 100 is formed between the semiconductor device 11 and the package substrate 10 to cover the solder bumps 12.

However, in the process of the conventional semiconductor package 1, when the semiconductor element 11 is of a large size or a high pin count, the flow of the encapsulant 13 does not easily fill the semiconductor element 11 and the package substrate 10. The space between the semiconductor element 11 and the package substrate 10 is caused by a void 14 so that the cavity 14 is prone to a popcorn effect during subsequent curing of the encapsulant 13 . Lead to a decline in product yield.

Furthermore, in the conventional semiconductor package 1, since the package substrate 10 has the plate body 10a, the overall thickness of the semiconductor package 1 is difficult to be effectively reduced, and the demand for lighter and thinner electronic products cannot be met.

Therefore, how to overcome the shortcomings of the prior art is a technical problem that is currently being solved by all walks of life.

In view of the above-mentioned deficiencies of the prior art, the present invention provides an electronic package comprising: an insulating layer; an electronic component incorporating a plurality of conductive bumps embedded in the insulating layer and having a surface of the conductive bump Exposed to the insulating layer; and the wiring structure is formed on the insulating layer and the conductive bump is exposed on the surface of the insulating layer and electrically connected to the conductive bump.

The invention provides a method for manufacturing an electronic package, comprising: disposing an electronic component combined with a plurality of conductive bumps on a carrier; forming an insulating layer on the carrier, so that the insulating layer covers the electronic component And exposing a portion of the surface of the conductive bump to the insulating layer; forming a wiring structure on the insulating layer and the conductive bump on the surface of the insulating layer, and electrically connecting the conductive structure to the conductive bump; And removing the carrier.

In the above electronic package and method of manufacturing the same, the electronic component has opposite active and non-active surfaces, and the active surface is coupled to the conductive bumps to electrically connect the electronic component to the conductive bumps. For example, after the carrier is removed, the inactive surface of the electronic component is exposed to the insulating layer; or the non-active surface of the electronic component is coupled to the heat sink.

In the foregoing electronic package and method of manufacturing the same, after the carrier is removed, the electronic component is exposed to the insulating layer.

In the foregoing electronic package and the method of manufacturing the same, the conductive bump is a solder bump.

In the foregoing electronic package and method of manufacturing the same, the complex conductive component is formed on the circuit structure.

In addition, in the foregoing electronic package and the manufacturing method thereof, the plurality of conductive pillars are formed in the insulating layer, and the conductive pillars are electrically connected to the wiring structure. For example, after removing the carrier, the end face of the conductive post is exposed to the insulating layer. Further, the complex includes attaching the electronic device to the end surface of the conductive pillar.

As can be seen from the above, the electronic package of the present invention and the method for manufacturing the same are mainly characterized in that the electronic component and the conductive bump are coated with the insulating layer, and the wiring structure is formed on the insulating layer, so that the insulating layer does not need to flow. Between the electronic component and the circuit structure, there is no void between the electronic component and the circuit structure, so the present invention can effectively improve the product yield compared to the prior art.

Moreover, the electronic package of the present invention only forms a line structure, and does not need to use a board of a conventional package substrate, so that the overall thickness of the electronic package can be greatly reduced compared to the prior art to meet the demand for thinning and thinning. .

1‧‧‧Semiconductor package

10‧‧‧Package substrate

10a‧‧‧ board

10b, 24, 24’‧‧‧ line structure

100,240‧‧‧circuit layer

11‧‧‧Semiconductor components

11a, 21a‧‧‧ action surface

11b, 21b‧‧‧ non-active surface

110,210‧‧‧electrode pads

12‧‧‧ solder bumps

13‧‧‧Package colloid

14‧‧‧ hollow

2,3‧‧‧Electronic package

20‧‧‧Carrier

200‧‧‧ metal layer

21‧‧‧Electronic components

22‧‧‧Electrical bumps

22a‧‧‧ top surface

23‧‧‧Insulation

23a‧‧‧ first surface

23b‧‧‧ second surface

241‧‧‧Electric conductor

242‧‧‧ dielectric layer

25‧‧‧Conductive components

26,26’‧‧‧ Heat sink

30‧‧‧conductive column

30a, 30b‧‧‧ end face

31‧‧‧Electronic devices

32‧‧‧Connecting bumps

1 is a schematic cross-sectional view of a conventional semiconductor package; and FIGS. 2A to 2E are cross-sectional views showing a method of fabricating the first embodiment of the electronic package of the present invention; wherein, the 2E' and 2E" diagrams are 2A to 3C are cross-sectional views showing a method of manufacturing the second embodiment of the electronic package of the present invention; wherein the 3C' is another embodiment of the 3C.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "first", "second" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments in the relative relationship are considered to be within the scope of the present invention.

2A to 2E are schematic cross-sectional views showing the manufacturing method of the first embodiment of the electronic package 2 of the present invention.

As shown in FIG. 2A, an electronic component 21 incorporating a plurality of conductive bumps 22 is disposed on a carrier 20.

In the embodiment, a surface of the carrier 20 is formed with a metal layer 200. In the present embodiment, the carrier 20 is a substrate, such as a copper foil substrate or other plate, but is not particularly limited. This embodiment is described by a copper foil substrate having a metal layer 200 on both sides.

Furthermore, the electronic component 21 is a semiconductor component which is an active component, a passive component or a combination thereof, and the active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 21 is a semiconductor wafer having an opposite active surface 21a and a non-active surface 21b. The active surface 21a has a plurality of electrode pads 210 for bonding the conductive bumps 22 to electrically elect the conductive bumps 22. The electronic component 21 is connected to the electronic component 21 with its non-active surface 21b adhered to the metal layer 200 by a bonding layer (not shown).

Moreover, the conductive bump 22 is a solder bump.

As shown in FIG. 2B, an insulating layer 23 is formed on the metal layer 200 of the carrier 20 such that the insulating layer 23 covers the electronic component 21 and the conductive bumps 22.

In this embodiment, the insulating layer 23 defines an opposite first surface 23a and a second surface 23b to bond the second surface to the metal layer 200 of the carrier 20.

Furthermore, the insulating layer 23 is an epoxy encapsulant which can be formed on the carrier 20 by lamination or molding.

Moreover, the top surface 22a of the conductive bump 22 is exposed to the insulating layer 23. For example, the top surface 22a of the conductive bump 22 may be flushed with the first surface 23a of the insulating layer 23 by a leveling process. Specifically, the leveling process can remove part of the material of the conductive bump 22 and part of the material of the insulating layer 23 by grinding.

As shown in FIG. 2C to FIG. 2D, a wiring structure 24 is formed on the insulating layer 23 and the top surface 22a of the conductive bump 22, and the wiring structure 24 is electrically connected to the conductive bumps 22.

In this embodiment, the circuit structure 24 includes a circuit layer 240 disposed on the insulating layer 23 and the conductive bumps 22, a plurality of electrical conductors 241 disposed on the circuit layer 240, and a cladding circuit. The layer 240 is electrically connected to the conductive layer 242 of the conductive body 241, and the circuit layer 240 is electrically connected to the conductive bumps 22, and a part of the surface of the conductive bodies 241 is exposed to the dielectric layer 242.

Furthermore, the material forming the wiring layer 240 is copper, and the conductor 241 is a copper pillar.

Moreover, the dielectric layer 242 is formed on the insulating layer 23 by a molding method, a coating method, or a press bonding method, and the material of the dielectric layer 242 is a mold compound and a primer. Or a dielectric material such as epoxy (Epoxy).

As shown in FIG. 2E, the carrier 20 and its metal layer 200 are removed to expose the electronic component 21 to the insulating layer 23 to complete the electronic package 2 of the present invention.

In this embodiment, the non-active surface 21b of the electronic component 21 is exposed on the second surface 23b of the insulating layer 23, and a plurality of conductive elements 25 such as solder balls are formed on the conductive body 241 of the wiring structure 24, An electronic device (not shown) for subsequent connection, such as a circuit board, package structure, or other structure, such as another wafer.

Further, as shown in Fig. 2E', the wiring structure 24' formed on the insulating layer 23 may have a plurality of wiring layers 240 and a plurality of dielectric layers 242.

Further, as shown in FIG. 2E, a heat sink 26 is coupled to the non-active surface 21b of the electronic component 21 and the second surface 23b of the insulating layer 23. In an embodiment, as in the second aspect of the present invention. The carrier used in the figure may be a metal plate, and only a part of the carrier is removed in the process, and the carrier corresponding to the non-active surface 21b of the electronic component 21 is retained as the heat sink 26. The electron of the present invention The package 2 is formed by first covering the electronic component 21 and the conductive bump 22 with the insulating layer 23, and then forming the wiring structure 24 on the insulating layer 23. Therefore, the insulating layer 23 does not need to flow through the electron. Between the element 21 and the line structure 24. Therefore, when the electronic component 21 is of a large size or a high number of pins, no void is formed between the electronic component 21 and the line structure 24, thereby preventing penetration of moisture. The problem is that the popcorn effect will not occur, so it can effectively improve the product yield.

Moreover, the electronic package 2 of the present invention only forms the wiring structure 24, and does not need to fabricate the board of the conventional package substrate. Therefore, the overall thickness of the electronic package 2 can be greatly reduced to meet the thinness and lightness compared with the prior art. Demand for change.

3A to 3C are schematic cross-sectional views showing the manufacturing method of the second embodiment of the electronic package 3 of the present invention. The difference between this embodiment and the first embodiment is that a new conductive column is added, and other processes are substantially the same, so only the differences will be described below, and the same points will not be described again.

As shown in FIG. 3A, a plurality of conductive posts 30 and an electronic component 21 incorporating a plurality of conductive bumps 22 are disposed on a carrier 20.

In this embodiment, the conductive pillar 30 is a copper pillar.

As shown in FIG. 3B, the processes of FIGS. 2B to 2D are performed to form the conductive pillars 30 in the insulating layer 23, and the conductive pillars 30 are electrically connected to the wiring layer 240 of the wiring structure 24.

In this embodiment, when the leveling process of FIG. 2B is performed, part of the material of the conductive pillar 30 may be removed, so that one end surface 30a of the conductive pillar 30 is flush with the first surface 23a of the insulating layer 23. .

Moreover, after the carrier 20 is removed, the other end surface 30b of the conductive post 30 is exposed on the second surface 23b of the insulating layer 23.

Moreover, as shown in FIG. 3C, a plurality of conductive elements such as solder balls can be formed on the conductors 241 of the line structure 24 for subsequent connection such as a circuit board, a package structure or other structures (such as another wafer). Electronic device (figure omitted).

In addition, in the subsequent process, as shown in FIG. 3C, an electronic device 31 can be connected to the end surface 30b of each of the conductive posts 30 by the connecting bumps 32, so that the electronic device 31 is electrically connected to each of the conductive pillars. 30. For example, the electronic device 31 is a package, an active component, or a passive component.

It should be understood that a heat sink 26' may be coupled to the non-active surface 21b of the electronic component 21 as shown in Fig. 3C'. In one embodiment, the heat sink 26' may be a carrier (e.g., a metal plate) that retains the non-active surface 21b of the corresponding electronic component 21.

The present invention provides an electronic package 2, 3 comprising: an insulating layer 23, electronic components 21 having a plurality of conductive bumps 22, and a wiring structure 24.

The insulating layer 23 has opposite first and second surfaces 23a, 23b.

The electronic component 21 and the conductive bump 22 are embedded in the insulating layer 23 such that a part of the surface (top surface 22a) of the conductive bump 22 is exposed on the first surface 23a of the insulating layer 23.

The circuit structure 24 is formed on the first surface 23a of the insulating layer 23 and electrically connected to the conductive bumps 22.

In an embodiment, the electronic component 21 has an opposite active surface 21a and an inactive surface 21b, and the active surface 21a is coupled to the conductive bumps 22.

In one embodiment, a heat dissipating member 26, 26' is coupled to the inactive surface 21b of the electronic component 21.

In an embodiment, the electronic component 21 is exposed to the insulating layer 23. For example, the non-active surface 21b of the electronic component 21 is exposed on the second surface 23b of the insulating layer 23.

In one embodiment, the conductive bumps 22 are solder bumps.

In one embodiment, the electronic package 2, 3 includes a plurality of conductive elements 25 formed on the line structure 24.

In one embodiment, the electronic package 3 includes a plurality of conductive pillars 30 formed in the insulating layer 23, and the conductive pillars 30 are electrically connected to the wiring structure 24.

In an embodiment, the end surface 30b of the conductive post 30 is exposed on the second surface 23b of the insulating layer 23.

In one embodiment, the electronic package 3 includes an electronic device 31 attached to the end surface 30b of the conductive post 30.

In summary, the electronic package of the present invention is formed by first coating the electronic component and the conductive bump with the insulating layer, and then forming the wiring structure on the insulating layer, so the electronic component and the electronic component There is no void between the circuit structures, which can effectively improve the product yield.

Furthermore, the electronic package of the present invention only forms a wiring structure, and it is not necessary to fabricate a board body of a conventional package substrate, so that the overall thickness of the electronic package can be greatly reduced to meet the demand for thinning.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

Claims (9)

 An electronic package comprising: an insulating layer; an electronic component in which a plurality of conductive bumps are bonded by an electrode pad is embedded in the insulating layer, and a part of a surface of the conductive bump is exposed to the insulating layer, wherein The conductive bump is a solder bump; and the wiring structure is formed on the insulating layer and the conductive bump is exposed on the surface of the insulating layer and electrically connected to the conductive bump.    The electronic package of claim 1, wherein the electronic component has opposite active and non-active surfaces, and the active surface is bonded to the conductive bumps to make the electronic component electrically The conductive bump is connected.    The electronic package of claim 2, wherein the inactive surface of the electronic component is exposed to the insulating layer.    The electronic package of claim 2, wherein the non-acting surface of the electronic component incorporates a heat sink.    The electronic package of claim 1, wherein the electronic component is exposed to the insulating layer.    The electronic package of claim 1, further comprising a plurality of conductive elements formed on the circuit structure.    The electronic package of claim 1, further comprising a plurality of conductive pillars formed in the insulating layer, and the conductive pillars are electrically connected to the wiring structure.    The electronic package of claim 7, wherein the end face of the conductive post is exposed to the insulating layer.    The electronic package of claim 8 is further comprising an electronic device attached to an end surface of the conductive post.