TW202029448A - Electronic package and package substrate thereof and method for manufacturing same - Google Patents

Electronic package and package substrate thereof and method for manufacturing same Download PDF

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TW202029448A
TW202029448A TW108103305A TW108103305A TW202029448A TW 202029448 A TW202029448 A TW 202029448A TW 108103305 A TW108103305 A TW 108103305A TW 108103305 A TW108103305 A TW 108103305A TW 202029448 A TW202029448 A TW 202029448A
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build
package
substrate
thickness
patent application
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TW108103305A
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TWI691041B (en
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白裕呈
米軒皞
羅家麒
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矽品精密工業股份有限公司
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Priority to CN201910116194.4A priority patent/CN111490025B/en
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Publication of TW202029448A publication Critical patent/TW202029448A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

This invention provides a package substrate, which forms a build-up layer portion on at least one side of the substrate body to maintain a certain thickness of the package substrate to prevent deformation of the package substrate during handling or packaging processes.

Description

電子封裝件及其封裝基板與製法 Electronic package, package substrate and manufacturing method thereof

本發明係有關一種電子封裝件及其封裝基板，尤指一種可防翹曲之電子封裝件及其封裝基板與製法。 The present invention relates to an electronic package and its package substrate, in particular to a warp-proof electronic package and its package substrate and manufacturing method.

隨著電子產業的蓬勃發展，許多高階電子產品逐漸朝往輕、薄、短、小等高集積度方向發展，且隨著封裝技術之演進，晶片的封裝技術也越來越多樣化，半導體封裝結構之尺寸或體積亦隨之不斷縮小，藉以使該半導體封裝結構達到輕薄短小之目的。 With the vigorous development of the electronics industry, many high-end electronic products are gradually moving towards the direction of light, thin, short, small and high integration. With the evolution of packaging technology, the packaging technology of chips has become more and more diversified. Semiconductor packaging The size or volume of the structure has also been continuously reduced, so that the semiconductor package structure can achieve the goal of lightness, thinness and shortness.

第1圖係為習知半導體封裝件1之剖面示意圖。如第1圖所示，該半導體封裝件1係包括：一封裝基板1a、一利用銲錫材13結合於該封裝基板1a上之半導體晶片19、以及用以包覆該半導體晶片19之封裝膠體(圖略)，以將該半導體封裝件1以其封裝基板1a藉由複數銲錫材13設於一電路板18上。 FIG. 1 is a schematic cross-sectional view of the conventional semiconductor package 1. As shown in Figure 1, the semiconductor package 1 includes: a packaging substrate 1a, a semiconductor chip 19 bonded to the packaging substrate 1a by soldering material 13, and a packaging glue for covering the semiconductor chip 19 ( (Figure omitted), so that the semiconductor package 1 and its package substrate 1a are arranged on a circuit board 18 with a plurality of solder materials 13.

惟，近年來，因手持式電子裝置蓬勃發展，故該半導體封裝件1之封裝基板1a的厚度越作越薄，因而造成該封裝基板1a於封裝製程或搬運期間發生翹曲、彎曲或其它變形狀況之問題，致使該封裝基板1a之銲錫材13’,13”無法有效接合該半導體晶片19之接點190及該電路板18。 However, in recent years, due to the vigorous development of hand-held electronic devices, the thickness of the packaging substrate 1a of the semiconductor package 1 has become thinner, resulting in warping, bending or other deformation of the packaging substrate 1a during the packaging process or handling. Due to the problem of the situation, the solder materials 13', 13" of the package substrate 1a cannot effectively join the contacts 190 of the semiconductor chip 19 and the circuit board 18.

因此，如何克服習知技術中之問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the problems in the conventional technology has become an urgent problem to be solved at present.

鑑於上述習知技術之缺失，本發明提供一種封裝基板，係包括：基板本體，係具有相對之第一側與第二側，並包含有至少一介電層及形成於該介電層上之線路層；以及增層部，係為絕緣體且形成於該基板本體之第一側及/或第二側上。 In view of the deficiencies of the above-mentioned conventional technologies, the present invention provides a package substrate including: a substrate body having a first side and a second side opposite to each other, and including at least one dielectric layer and a substrate formed on the dielectric layer The circuit layer; and the build-up portion is an insulator and is formed on the first side and/or the second side of the substrate body.

本發明復提供一種封裝基板之製法，係包括：提供一基板本體，其具有相對之第一側與第二側，並包含有至少一介電層及形成於該介電層上之線路層；形成增高層於該基板本體之第一側及/或第二側上；以及移除該增高層之部分材質以形成至少一開口，俾令該形成至少一開口之增高層作為增層部。 The present invention further provides a method for manufacturing a package substrate, which includes: providing a substrate body, which has a first side and a second side opposite to each other, and includes at least one dielectric layer and a circuit layer formed on the dielectric layer; Forming an increased layer on the first side and/or the second side of the substrate body; and removing part of the material of the increased layer to form at least one opening, so that the increased layer formed with at least one opening serves as an increased layer.

前述之製法中，該增高層係以壓合方式形成於該基板本體上。 In the aforementioned manufacturing method, the height-enhancing layer is formed on the substrate body by pressing.

前述之製法中，部分該增高層之移除方式係以雷射方式或噴砂方式為之。 In the aforementioned manufacturing method, part of the method of removing the height-enhanced layer is laser or sandblasting.

前述之封裝基板及其製法中，該增層部之材質係相同於該介電層之材質。 In the aforementioned packaging substrate and its manufacturing method, the material of the build-up part is the same as the material of the dielectric layer.

前述之封裝基板及其製法中，該基板本體係定義有複數作用區域，且該增層部係位於各該作用區域之間。 In the aforementioned packaging substrate and its manufacturing method, the substrate system defines a plurality of active areas, and the build-up layer is located between the active areas.

前述之封裝基板及其製法中，該增層部係形成於該基板本體之第一側及第二側上，且該基板本體之第一側上之增層部之厚度係不同於該基板本體之第二側上之增層部之厚度。 In the aforementioned package substrate and its manufacturing method, the build-up portion is formed on the first side and the second side of the substrate body, and the thickness of the build-up portion on the first side of the substrate body is different from that of the substrate body The thickness of the build-up layer on the second side.

前述之封裝基板及其製法中，該增層部係形成於該基板本體之第一側及第二側上，且該基板本體之第一側上之增層部之厚度係等於該基板本體之第二側上之增層部之厚度。 In the aforementioned packaging substrate and its manufacturing method, the build-up portion is formed on the first side and the second side of the substrate body, and the thickness of the build-up portion on the first side of the substrate body is equal to that of the substrate body The thickness of the build-up layer on the second side.

前述之封裝基板及其製法中，該增層部係形成於該基板本體之第一側及第二側上，且該第一側上之增層部之寬度係相同或不同於該第二側上之增層部之寬度。 In the aforementioned package substrate and its manufacturing method, the build-up portion is formed on the first side and the second side of the substrate body, and the width of the build-up portion on the first side is the same or different from the second side The width of the upper build-up section.

前述之封裝基板及其製法中，該增層部之頂部係具有絕緣保護層。 In the aforementioned packaging substrate and its manufacturing method, the top of the build-up portion has an insulating protective layer.

前述之封裝基板及其製法中，該增層部係為框體結構。 In the aforementioned package substrate and its manufacturing method, the build-up part is a frame structure.

另一方面，本發明提供一種電子封裝件，係包括：一如前述之封裝基板；以及至少一電子元件，係設於該基板本體之第一側及/或第二側上。 In another aspect, the present invention provides an electronic package, which includes: a packaging substrate as described above; and at least one electronic component disposed on the first side and/or the second side of the substrate body.

本發明亦提供一種電子封裝件之製法，係包括：提供一如前述之封裝基板；以及設置至少一電子元件於該基板本體之第一側及/或第二側上。 The present invention also provides a method for manufacturing an electronic package, which includes: providing a package substrate as described above; and arranging at least one electronic component on the first side and/or the second side of the substrate body.

前述之電子封裝件及其製法中，該基板本體係定義有複數作用區域，且於單一作用區域內係設有複數規格相同之該電子元件。 In the aforementioned electronic package and its manufacturing method, the substrate system defines a plurality of active areas, and a plurality of electronic components with the same specifications are arranged in a single active area.

前述之電子封裝件及其製法中，該基板本體係定義有複數作用區域，且於單一作用區域內係設有複數規格不同之該電子元件。 In the aforementioned electronic package and its manufacturing method, the substrate system defines a plurality of active areas, and a plurality of electronic components with different specifications are arranged in a single active area.

前述之電子封裝件及其製法中，該電子元件係位於該增層部所圍束之區域內。 In the aforementioned electronic package and its manufacturing method, the electronic component is located in the area enclosed by the build-up portion.

前述之電子封裝件及其製法中，復包括封裝層，係形成於該基板本體之第一側及/或第二側上以包覆該電子元件。例如，該封裝層之厚度係大於或等於該增層部之厚度。 The aforementioned electronic package and its manufacturing method further include an encapsulation layer, which is formed on the first side and/or the second side of the substrate body to cover the electronic component. For example, the thickness of the encapsulation layer is greater than or equal to the thickness of the build-up layer.

前述之電子封裝件及其製法中，該電子元件之厚度係相同或不同於該增層部之厚度。 In the aforementioned electronic package and its manufacturing method, the thickness of the electronic component is the same or different from the thickness of the build-up part.

由上可知，本發明之電子封裝件及其封裝基板與製法，主要藉由該增層部之設計，使該封裝基板保有一定的厚度，故相較於習知技術，本發明之封裝基板可避免於搬運或封裝製程中造成如翹曲之變形問題，進而避免該電子封裝件之封裝良率下降之情況。 It can be seen from the above that the electronic package of the present invention and its packaging substrate and manufacturing method mainly rely on the design of the build-up part to maintain a certain thickness of the packaging substrate. Therefore, compared with the prior art, the packaging substrate of the present invention can Avoiding deformation problems such as warpage during the handling or packaging process, thereby avoiding the decline of the packaging yield of the electronic package.

1‧‧‧半導體封裝件 1‧‧‧Semiconductor package

1a‧‧‧封裝基板 1a‧‧‧Packaging substrate

13,13’,13”‧‧‧銲錫材 13,13’,13”‧‧‧Solder

18‧‧‧電路板 18‧‧‧Circuit board

19‧‧‧半導體晶片 19‧‧‧Semiconductor chip

190‧‧‧接點 190‧‧‧Contact

2,2’,4a‧‧‧封裝基板 2,2’,4a‧‧‧Packaging substrate

20‧‧‧基板本體 20‧‧‧Substrate body

20a‧‧‧第一側 20a‧‧‧First side

20b‧‧‧第二側 20b‧‧‧Second side

200‧‧‧介電層 200‧‧‧Dielectric layer

201‧‧‧線路層 201‧‧‧Line layer

202,203‧‧‧電性接觸墊 202,203‧‧‧electrical contact pad

21‧‧‧增高層 21‧‧‧High rise

210‧‧‧開口 210‧‧‧Open

22,22’,42‧‧‧增層部 22,22’,42‧‧‧Addition

220‧‧‧第一絕緣保護層 220‧‧‧First insulation protection layer

23‧‧‧第二絕緣保護層 23‧‧‧Second insulating protective layer

230‧‧‧開孔 230‧‧‧Opening

3,3’,3a,3b,4,4’‧‧‧電子封裝件 3,3’,3a,3b,4,4’‧‧‧electronic package

31a,31b,41‧‧‧第一電子元件 31a, 31b, 41‧‧‧First electronic component

310,320‧‧‧導電凸塊 310,320‧‧‧Conductive bump

311‧‧‧銲錫材 311‧‧‧Solder

32‧‧‧第二電子元件 32‧‧‧Second electronic component

33‧‧‧封裝層 33‧‧‧Packaging layer

A1,A2‧‧‧作用區域 A1,A2‧‧‧Affected area

D1,D2,d,H,h,H’,h’,L1,L2,t,t1,t2,t1’,t2’,R1,R2‧‧‧厚度 D1,D2,d,H,h,H’,h’,L1,L2,t,t1,t2,t1’,t2’,R1,R2‧‧‧Thickness

W1,W2,W1’,W2’‧‧‧寬度 W1,W2,W1’,W2’‧‧‧Width

第1圖係為習知電子封裝件之剖視示意圖。 Figure 1 is a schematic cross-sectional view of a conventional electronic package.

第2A至2E圖係為本發明之封裝基板及電子封裝件之製法之剖視示意圖。 2A to 2E are schematic cross-sectional views of the manufacturing method of the package substrate and the electronic package of the present invention.

第2C’圖係為第2C圖之上視示意圖。 Figure 2C' is a schematic top view of Figure 2C.

第2E’圖係為第2E圖之另一實施例。 Figure 2E' is another embodiment of Figure 2E.

第3A及3B圖係為本發明之電子封裝件之其它實施例之剖視示意圖。 3A and 3B are schematic cross-sectional views of other embodiments of the electronic package of the present invention.

第4A及4B圖係為第3A圖之其它態樣。 Figures 4A and 4B are other aspects of Figure 3A.

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The following specific examples illustrate the implementation of the present invention. Those familiar with the art can easily understand the other advantages and effects of the present invention from the contents disclosed in this specification.

須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、 比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「第一」、「第二」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this manual are only used to match the contents disclosed in the manual for the understanding and reading of those familiar with the art, and are not intended to limit the implementation of the present invention Qualified conditions, so it does not have technical significance, any structural modification, The change of the proportional relationship or the adjustment of the size should still fall within the scope covered by the technical content disclosed in the present invention without affecting the effects and objectives that can be achieved by the present invention. At the same time, the terms "on", "first", "second" and "one" cited in this specification are only for ease of description and are not used to limit the scope of the present invention. The change or adjustment of the relative relationship shall be regarded as the scope of the implementation of the present invention without substantial change in the technical content.

第2A至2C圖係為本發明之封裝基板2之製法之剖視示意圖。 2A to 2C are schematic cross-sectional views of the manufacturing method of the package substrate 2 of the present invention.

於本實施例中，該封裝基板2係適用於雙面模壓的電子封裝件3，如第2E圖所示。 In this embodiment, the packaging substrate 2 is suitable for a double-sided molded electronic package 3, as shown in FIG. 2E.

如第2A圖所示，提供一基板本體20，其具有相對之第一側20a與第二側20b。 As shown in FIG. 2A, a substrate body 20 is provided, which has a first side 20a and a second side 20b opposite to each other.

於本實施例中，該基板本體20主要為絕緣板、金屬板、或如晶圓、晶片、矽材、玻璃等之半導體板材。例如，該基板本體20係為具核心層之線路構造(圖未示)或無核心層(coreless)之線路構造(如第2A圖所示)，該線路構造係包含至少一介電層200及設於該介電層200上之如重佈線路層(redistribution layer，簡稱RDL)形式之線路層201，其最外側之線路層201係具有電性接觸墊202,203。具體地，形成該線路層201之材質係為銅，且形成該介電層200之材質係為如聚對二唑苯(Polybenzoxazole，簡稱PBO)、聚醯亞胺(Polyimide，簡稱PI)、預浸材(Prepreg，簡稱PP)等之介電材。 In this embodiment, the substrate body 20 is mainly an insulating plate, a metal plate, or a semiconductor plate such as a wafer, a chip, a silicon material, and glass. For example, the substrate body 20 is a circuit structure with a core layer (not shown) or a circuit structure without a core layer (as shown in FIG. 2A), and the circuit structure includes at least one dielectric layer 200 and A circuit layer 201 in the form of a redistribution layer (RDL) disposed on the dielectric layer 200, and the outermost circuit layer 201 has electrical contact pads 202 and 203. Specifically, the material for forming the circuit layer 201 is copper, and the material for forming the dielectric layer 200 is, for example, polybenzoxazole (PBO), polyimide (PI), and Dielectric materials such as Prepreg (PP for short).

或者，該基板本體亦可為矽中介板(Through Silicon interposer，簡稱TSI)或玻璃基板，其具有矽穿孔(Through-silicon via，簡稱TSV)與佈線層，如扇出(fan out)型RDL。因此，有關該基板本體之態樣繁多，並不限於上述。 Alternatively, the substrate body can also be a Through Silicon Interposer (TSI) or a glass substrate with Through-silicon via (TSV) and a wiring layer, such as a fan out type RDL. Therefore, there are many aspects related to the substrate body, which are not limited to the above.

又，該基板本體20之厚度t約為60~75微米(um)或60微米以下(該電性接觸墊202之厚度相對該基板本體20之厚度極薄，可省略)。 In addition, the thickness t of the substrate body 20 is about 60-75 microns (um) or less (the thickness of the electrical contact pad 202 is extremely thin relative to the thickness of the substrate body 20 and can be omitted).

如第2B圖所示，形成一增高層21於於該基板本體20之第一側20a上，以覆蓋該些電性接觸墊202。 As shown in FIG. 2B, an increased height 21 is formed on the first side 20 a of the substrate body 20 to cover the electrical contact pads 202.

於本實施例中，該增高層21之材質係包含絕緣材，如聚對二唑苯(PBO)、聚醯亞胺(PI)、預浸材(PP)等介電材，其中，形成該增高層21之材質可相同或不相同形成該介電層200之材質。 In this embodiment, the material of the height-enhanced layer 21 includes insulating materials, such as polypara-diazole benzene (PBO), polyimide (PI), prepreg (PP) and other dielectric materials, wherein the The material of the enhanced layer 21 may be the same or different from the material of the dielectric layer 200.

再者，該增高層21之厚度d係為5至25微米(視該基板本體20所需結構強度增減)。 Furthermore, the thickness d of the height-enhancing layer 21 is 5-25 microns (depending on the required structural strength of the substrate body 20).

如第2C圖所示，藉由圖案化製程(如採用雷射或噴砂方式移除該增高層21之部分材質)，以於該增高層21中形成複數開口210，以令該增高層21構成一增層部22，以令該基板本體20之第一側20a之部分表面及電性接觸墊202外露於該些開口210，以製得封裝基板2。 As shown in Figure 2C, through a patterning process (such as using laser or sandblasting to remove part of the material of the height-enhancing layer 21), a plurality of openings 210 are formed in the height-enhancing layer 21 to form the height-enhancing layer 21 A build-up portion 22 is used to expose a part of the surface of the first side 20a of the substrate body 20 and the electrical contact pads 202 to the openings 210 to make the package substrate 2.

於本實施例中，該增層部22係為封閉形式環狀框體結構，如第2C’圖所示，其無缺口或中斷處，且該基板本體20定義有複數作用區域A1,A2(該作用區域A1,A2係對應於開口210位置)，以藉由該增層部22圍繞各該作用區域A1,A2之邊緣而隔離各該作用區域A1,A2。 In this embodiment, the build-up portion 22 is a closed ring frame structure, as shown in Figure 2C', it has no gaps or interruptions, and the substrate body 20 defines a plurality of action areas A1, A2 ( The active areas A1, A2 correspond to the positions of the opening 210), so that the layer-enhancing portion 22 surrounds the edges of the active areas A1, A2 to isolate the active areas A1, A2.

再者，該增層部22(該增高層21)係可透過壓合方式形成於該基板本體20上；或者，可利用黏著層或其它方式將該增層部22接合於該基板本體20上。應可理解地，以壓合方式形成該增層部22的製作方式可節省成本。 Furthermore, the build-up portion 22 (the build-up layer 21) can be formed on the substrate body 20 by pressing; or, the build-up portion 22 can be bonded to the substrate body 20 by using an adhesive layer or other methods . It should be understood that the manufacturing method of forming the build-up portion 22 by pressing can save cost.

又，於另一實施例中，如第2D圖所示，增層部22’之頂部包含有第一絕緣保護層220。例如，於原始增層部22上形成一如防銲材之第一絕緣保護層220，且形成一如防銲材之第二絕緣保護層23於該基板本體20之第二側20b上，並使該第二絕緣保護層23形成有至少一開孔230，以令該基板本體20之第二側20b之部分表面及電性接觸墊203外露於該開孔230，以製得封裝基板2’。具體地，該封裝基板2,2’之厚度D1,D2係為85微米以下，以符合薄化之需求。 Furthermore, in another embodiment, as shown in FIG. 2D, the top of the build-up portion 22' includes a first insulating protection layer 220. For example, a first insulating protective layer 220 like a solder resist is formed on the original build-up part 22, and a second insulating protective layer 23 like a solder resist is formed on the second side 20b of the substrate body 20, and The second insulating protection layer 23 is formed with at least one opening 230, so that a part of the surface of the second side 20b of the substrate body 20 and the electrical contact pad 203 are exposed in the opening 230, so as to obtain a package substrate 2' . Specifically, the thicknesses D1, D2 of the package substrates 2, 2'are less than 85 microns to meet the thinning requirements.

另外，如第2E圖所示，於後續製作電子封裝件3之過程中，可將複數第一電子元件31a,31b,41設於該基板本體20之第一側20a之增層部22,22’所圍束之區域內，並將第二電子元件32設於該基板本體20之第二側20b上，以電性連接該電性接觸墊202,203及線路層201，再形成一封裝層33於該基板本體20之第一側20a與該第二側20b上，以包覆該增層部22,22’、該些第一電子元件31a,31b,41與第二電子元件32。 In addition, as shown in Figure 2E, in the subsequent process of manufacturing the electronic package 3, a plurality of first electronic components 31a, 31b, 41 can be placed on the build-up portions 22, 22 of the first side 20a of the substrate body 20 The second electronic component 32 is arranged on the second side 20b of the substrate body 20 to electrically connect the electrical contact pads 202, 203 and the circuit layer 201 to form an encapsulation layer 33 The first side 20a and the second side 20b of the substrate body 20 are covered with the build-up portions 22, 22', the first electronic components 31a, 31b, 41 and the second electronic components 32.

所述之第一電子元件31a,31b,41係結合於該基板本體20之第一側20a上，其係為主動元件、被動元件或其二者組合，且該主動元件係例如半導體晶片，而該被動元件係例如電阻、電容及電感。例如，該第一電子元件31a,31b係為天線型半導體晶片，其具有相對之作用面與非作用面，該作用面藉由複數導電凸塊310以覆晶方式設於該電性接觸墊202上以電性連接該線路層201；或者，該第一電子元件31a,31b可以該非作用面設於該第一側20a上並使該作用面藉由複數銲線(圖略)以打線方式電性連接該線路層201；亦或，該第一電子元件41可為被動元件，其藉由銲錫材311設於該電性接觸墊202上以電性連接該線路層201。然而，有關該第一電子元件31a,31b,41電性連接該基板本體20之方式不限於上述。 The first electronic components 31a, 31b, 41 are combined on the first side 20a of the substrate body 20, which are active components, passive components or a combination of the two, and the active components are for example semiconductor chips, and The passive components are, for example, resistors, capacitors, and inductors. For example, the first electronic component 31a, 31b is an antenna-type semiconductor chip, which has an opposite active surface and a non-active surface, and the active surface is provided on the electrical contact pad 202 in a flip chip manner by a plurality of conductive bumps 310 The circuit layer 201 is electrically connected to the upper side; alternatively, the first electronic component 31a, 31b can be arranged on the first side 20a with the non-acting surface and the active surface is electrically connected in a wire-bonding manner through a plurality of bonding wires (the figure is omitted). The circuit layer 201 is electrically connected; or, the first electronic component 41 can be a passive component, which is provided on the electrical contact pad 202 by a solder material 311 to electrically connect the circuit layer 201. However, the manner in which the first electronic components 31a, 31b, 41 are electrically connected to the substrate body 20 is not limited to the above.

另一方面，如第2E’圖及第2C圖所示，可於同一作用區域A2中設置相同規格的第一電子元件41，如相同型號、容值或阻值等被動元件置放於同一作用區域A2中，以提供較多空間區域設置該增層部22，因而提升該封裝基板2之剛性或強度。 On the other hand, as shown in Figure 2E' and Figure 2C, first electronic components 41 of the same specification can be placed in the same active area A2, such as passive components of the same model, capacitance or resistance, placed in the same function In the area A2, the build-up portion 22 is provided to provide more space, thereby improving the rigidity or strength of the packaging substrate 2.

所述之第二電子元件32係結合於該基板本體20之第二側20b上，其係為主動元件、被動元件或其二者組合等，其中，該主動元件係例如半導體晶片，且該被動元件係例如電阻、電容及電感。例如，該第二電子元件32係為半導體晶片，其作用面藉由複數導電凸塊320以覆晶方式設於該電性接觸墊203 上以電性連接該線路層201；或者，該第二電子元件32可以打線方式電性連接該線路層201；亦或，該第二電子元件32可直接接觸該線路層201。然而，有關該第二電子元件32電性連接該基板本體20之方式不限於上述。 The second electronic component 32 is coupled to the second side 20b of the substrate body 20, and it is an active component, a passive component, or a combination of the two, etc., wherein the active component is a semiconductor chip, and the passive component Components such as resistors, capacitors and inductors. For example, the second electronic component 32 is a semiconductor chip, and its active surface is provided on the electrical contact pad 203 in a flip chip manner by a plurality of conductive bumps 320 It is electrically connected to the circuit layer 201; alternatively, the second electronic component 32 can be electrically connected to the circuit layer 201 by wire bonding; or, the second electronic component 32 can directly contact the circuit layer 201. However, the manner in which the second electronic component 32 is electrically connected to the substrate body 20 is not limited to the above.

所述之封裝層33係為絕緣材，如聚醯亞胺(polyimide，簡稱PI)、乾膜(dry film)、如環氧樹脂(expoxy)之封裝膠體或封裝材(molding compound)，其可用壓合(lamination)或模壓(molding)之方式形成於該基板本體20上。例如，該封裝層33於基板本體20之第一側20a上之厚度H可大於該增層部22,22’之厚度L1,L2，如第2E圖所示。 The encapsulation layer 33 is an insulating material, such as polyimide (PI), dry film, epoxy resin (expoxy) or molding compound, which can be used The substrate body 20 is formed on the substrate body 20 by lamination or molding. For example, the thickness H of the encapsulation layer 33 on the first side 20a of the substrate body 20 may be greater than the thicknesses L1, L2 of the build-up portions 22, 22', as shown in FIG. 2E.

於其它實施例中，增層部之配置可依需求設於該基板本體20之第二側20b上(如第3A圖所示之電子封裝件3a)。具體地，該基板本體20之第一側20a之增層部22’之厚度t1可相同或不相同於該第二側20b之增層部22’之厚度t2。再者，如第3A圖所示，封裝層33於基板本體20之各別二側之厚度h可等於該增層部22’之厚度t1,t2，亦即，該封裝層33之上表面齊平該增層部22’之上表面；或者，該基板本體20之第一側20a之增層部22’之寬度W1可不相同(如第3A圖所示)於該第二側20b之增層部22’之寬度W2；亦或，該第一側20a上之增層部42之寬度W1’係相同於該第二側20b上之增層部42之寬度W2’(如第4A圖所示)。 In other embodiments, the configuration of the build-up portion can be arranged on the second side 20b of the substrate body 20 (such as the electronic package 3a shown in FIG. 3A) as required. Specifically, the thickness t1 of the build-up portion 22' on the first side 20a of the substrate body 20 may be the same or different from the thickness t2 of the build-up portion 22' on the second side 20b. Furthermore, as shown in FIG. 3A, the thickness h of the encapsulation layer 33 on each of the two sides of the substrate body 20 may be equal to the thickness t1, t2 of the build-up portion 22', that is, the upper surface of the encapsulation layer 33 is even Flatten the upper surface of the build-up portion 22'; alternatively, the width W1 of the build-up portion 22' on the first side 20a of the substrate body 20 may be different (as shown in Figure 3A) on the build-up on the second side 20b The width W2 of the portion 22'; or, the width W1' of the build-up portion 42 on the first side 20a is the same as the width W2' of the build-up portion 42 on the second side 20b (as shown in Figure 4A ).

於另一實施例中，增層部之配置可依需求設於該基板本體20之表面空曠區(如未設置電子元件之區域)。具體地，如第3A圖所示之第二側20b之增層部22’。 In another embodiment, the configuration of the build-up portion can be set in an open area on the surface of the substrate body 20 (such as an area where no electronic components are provided) as required. Specifically, the build-up portion 22' on the second side 20b shown in Figure 3A.

於另一實施例中，該增層部22,22’僅設於該基板本體20之線路層201之分佈面積較少之側。具體地，如第3B圖所示之電子封裝件3b，其基板本體20之第二側20b因僅需設置一顆晶片(該第二電子元件32)，故該基板本體20 之第二側20b會有較多的空間形成該增層部22’，因而該增層部22’未設於該第一側20a上。 In another embodiment, the build-up portions 22, 22' are only provided on the side of the substrate body 20 where the distribution area of the circuit layer 201 is smaller. Specifically, for the electronic package 3b shown in Figure 3B, the second side 20b of the substrate body 20 only needs to be provided with one chip (the second electronic component 32), so the substrate body 20 The second side 20b will have more space to form the build-up portion 22', so the build-up portion 22' is not provided on the first side 20a.

因此，本發明之封裝基板2,2’及電子封裝件3,3’,3a,3b之製法係因應該基板本體20欲薄化至75微米以下時，藉由於該基板本體20上形成該增層部22,22’，使該封裝基板2,2’保有一定的厚度D1,D2，因而能避免該封裝基板2,2’於搬運或封裝製程中造成如翹曲之變形問題，進而有效避免該電子封裝件3,3’,3a,3b之封裝良率下降之情況。 Therefore, the manufacturing method of the packaging substrates 2, 2'and electronic packages 3, 3', 3a, and 3b of the present invention is that when the substrate body 20 is to be thinned to less than 75 microns, the increase is formed on the substrate body 20. The layer portions 22, 22' enable the package substrate 2, 2'to maintain a certain thickness D1, D2, thereby preventing the package substrate 2, 2'from causing deformation problems such as warpage during the handling or packaging process, thereby effectively avoiding The packaging yield of the electronic package 3, 3', 3a, 3b has decreased.

再者，如第4A及4B圖所示之電子封裝件4,4’，該增層部42之厚度t1’,t2’可低於該第一電子元件31a,31b,41之厚度R1及第二電子元件32之厚度R2，以降低該封裝層33之厚度H’,h’而利於薄化該封裝基板4a，且該封裝層33之表面可齊平該第一電子元件31a或第二電子元件32，如第4B圖所示，以外露出該第一電子元件31a或第二電子元件32。 Furthermore, as for the electronic package 4, 4'shown in FIGS. 4A and 4B, the thickness t1', t2' of the build-up portion 42 can be lower than the thickness R1 and the first electronic component 31a, 31b, 41 The thickness R2 of the two electronic components 32 is used to reduce the thickness H', h'of the encapsulation layer 33 to facilitate the thinning of the encapsulation substrate 4a, and the surface of the encapsulation layer 33 can be flush with the first electronic component 31a or the second electronic component. The element 32, as shown in FIG. 4B, exposes the first electronic element 31a or the second electronic element 32.

本發明復提供一種封裝基板2,2’,4a，其包括：一基板本體20以及至少一增層部22,22’,42。 The present invention further provides a packaging substrate 2, 2', 4a, which includes: a substrate body 20 and at least one build-up portion 22, 22', 42.

所述之基板本體20係具有相對之第一側20a與第二側20b，且包含有至少一介電層200及設於該介電層200上之線路層201。 The substrate body 20 has a first side 20 a and a second side 20 b opposite to each other, and includes at least one dielectric layer 200 and a circuit layer 201 provided on the dielectric layer 200.

所述之增層部22,22’,42係形成於該基板本體20之第一側20a及/或第二側20b上，其中，該增層部22,22’,42係為絕緣體。 The build-up portions 22, 22', 42 are formed on the first side 20a and/or the second side 20b of the substrate body 20, wherein the build-up portions 22, 22', 42 are insulators.

於一實施例中，該增層部22,22’,42之材質係同於該介電層200之材質。 In one embodiment, the material of the build-up portion 22, 22', 42 is the same as the material of the dielectric layer 200.

於一實施例中，該基板本體20之第一側20a係定義有複數作用區域A1,A2，且該增層部22,22’,42係位於各該作用區域A1,A2之間。 In one embodiment, the first side 20a of the substrate body 20 defines a plurality of active areas A1, A2, and the build-up portion 22, 22', 42 is located between the active areas A1, A2.

於一實施例中，該增層部22’,42係形成於該基板本體20之第一側20a及第二側20b上，且該基板本體20之第一側20a上之增層部22’,42之厚度 t1,t1’係相同或不同於該基板本體20之第二側20b上之增層部22’,42之厚度t2,t2’。 In one embodiment, the build-up portions 22', 42 are formed on the first side 20a and the second side 20b of the substrate body 20, and the build-up portion 22' on the first side 20a of the substrate body 20 ,42 thickness t1, t1' are the same or different from the thickness t2, t2' of the build-up portions 22', 42 on the second side 20b of the substrate body 20.

於一實施例中，參考圖3A及圖4A所示，該增層部22’,42係形成於該基板本體20之第一側20a及第二側20b上，且該第一側20a上之增層部22’之寬度W1係不同於該第二側20b上之增層部22’之寬度W2；或者，該第一側20a上之增層部42之寬度W1’係相同於該第二側20b上之增層部42之寬度W2’。 In one embodiment, referring to FIGS. 3A and 4A, the build-up portions 22', 42 are formed on the first side 20a and the second side 20b of the substrate body 20, and the first side 20a is The width W1 of the build-up portion 22' is different from the width W2 of the build-up portion 22' on the second side 20b; or, the width W1' of the build-up portion 42 on the first side 20a is the same as the second The width W2' of the build-up portion 42 on the side 20b.

於一實施例中，該增層部22’,42之頂部係具有絕緣保護層220。 In one embodiment, the top of the build-up portion 22', 42 has an insulating protective layer 220.

本發明復提供一種電子封裝件3,3’,3a,3b,4,4’，係包括：該封裝基板2,2’,4a,4b、至少一第一電子元件31a,31b,41以及至少一第二電子元件32。 The present invention further provides an electronic package 3, 3', 3a, 3b, 4, 4', comprising: the packaging substrate 2, 2', 4a, 4b, at least one first electronic component 31a, 31b, 41 and at least A second electronic component 32.

所述之第一電子元件31a,31b,41係設於該基板本體20之第一側20a上。 The first electronic components 31a, 31b, 41 are arranged on the first side 20a of the substrate body 20.

所述之第二電子元件32係設於該基板本體20之第二側20b上。 The second electronic component 32 is arranged on the second side 20 b of the substrate body 20.

於其中一電子封裝件3’之實施例中，該基板本體20之第一側20a係定義有複數作用區域A1,A2，且於單一作用區域A2內係設有複數規格相同之該第一電子元件41。 In one embodiment of the electronic package 3', the first side 20a of the substrate body 20 is defined with a plurality of active areas A1, A2, and in a single active area A2 is provided a plurality of the same specifications of the first electronics Element 41.

於其中一電子封裝件3,3a,3b,4,4’之實施例中，該基板本體20之第一側20a係定義有複數作用區域A1,A2，且於單一作用區域A2內係設有複數規格不同之該第一電子元件31b,41。 In the embodiment of one of the electronic packages 3, 3a, 3b, 4, 4', the first side 20a of the substrate body 20 is defined with a plurality of active areas A1, A2, and a single active area A2 is provided A plurality of the first electronic components 31b, 41 with different specifications.

於一實施例中，該第一電子元件31a,31b,41或第二電子元件32係位於該增層部22,22’,42所圍束之區域內。 In one embodiment, the first electronic component 31a, 31b, 41 or the second electronic component 32 is located in the area enclosed by the build-up portion 22, 22', 42.

於一實施例中，該增層部42之厚度t1’,t2’不同於該第一電子元件31a,31b,41之厚度R1及第二電子元件32之厚度R2。 In one embodiment, the thickness t1', t2' of the build-up portion 42 is different from the thickness R1 of the first electronic element 31a, 31b, 41 and the thickness R2 of the second electronic element 32.

於一實施例中，所述之電子封裝件3,3’,3a,3b,4,4’復包括一封裝層33，係形成於該基板本體20之第一側20a及/或第二側20b上以包覆該第一電子元 件31a,31b,41或第二電子元件32。例如，該封裝層33之厚度H,H’,h’係不同於該增層部22’,42之厚度L1,L2,t1,t2,t1’,t2’；或者，該封裝層33於基板本體20之各別二側之厚度h可相同於該增層部22’之厚度t1,t2。 In one embodiment, the electronic package 3, 3', 3a, 3b, 4, 4'includes an encapsulation layer 33 formed on the first side 20a and/or the second side of the substrate body 20 20b to cover the first electronic element Pieces 31a, 31b, 41 or the second electronic component 32. For example, the thickness H, H', h'of the encapsulation layer 33 is different from the thickness L1, L2, t1, t2, t1', t2' of the build-up portion 22', 42; or, the encapsulation layer 33 is on the substrate The thickness h of the respective two sides of the main body 20 may be the same as the thickness t1 and t2 of the build-up portion 22'.

綜上所述，本發明之電子封裝件及其封裝基板與製法，主要藉由該增層部之設計，使該封裝基板保有一定的厚度，以避免該封裝基板於搬運或封裝製程中造成如翹曲之變形問題，故本發明之封裝基板能避免該電子封裝件之封裝良率下降之情況。 In summary, the electronic package and its packaging substrate and manufacturing method of the present invention mainly rely on the design of the build-up portion to maintain a certain thickness of the packaging substrate to prevent the packaging substrate from causing such problems during the transportation or packaging process. Because of the problem of warpage and deformation, the packaging substrate of the present invention can prevent the packaging yield of the electronic package from decreasing.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above-mentioned embodiments are used to exemplify the principles and effects of the present invention, but not to limit the present invention. Anyone who is familiar with the art can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

2‧‧‧封裝基板 2‧‧‧Packaging substrate

20‧‧‧基板本體 20‧‧‧Substrate body

20a‧‧‧第一側 20a‧‧‧First side

20b‧‧‧第二側 20b‧‧‧Second side

202,203‧‧‧電性接觸墊 202,203‧‧‧electrical contact pad

210‧‧‧開口 210‧‧‧Open

22‧‧‧增層部 22‧‧‧Additional Department

A1,A2‧‧‧作用區域 A1,A2‧‧‧Affected area

D1‧‧‧厚度 D1‧‧‧Thickness

Claims (36)

一種封裝基板，係包括：基板本體，係具有相對之第一側與第二側，並包含有至少一介電層及形成於該介電層上之線路層；以及增層部，係為絕緣體且形成於該基板本體之第一側及/或第二側上。 A package substrate includes: a substrate body having a first side and a second side opposite to each other, and including at least one dielectric layer and a circuit layer formed on the dielectric layer; and a build-up part which is an insulator And formed on the first side and/or the second side of the substrate body. 如申請專利範圍第1項所述之封裝基板，其中，該增層部之材質係相同於該介電層之材質。 According to the package substrate described in claim 1, wherein the material of the build-up part is the same as the material of the dielectric layer. 如申請專利範圍第1項所述之封裝基板，其中，該基板本體定義有複數作用區域，且該增層部係位於各該作用區域之間。 According to the package substrate described in item 1 of the scope of patent application, the substrate body defines a plurality of active areas, and the build-up layer is located between the active areas. 如申請專利範圍第1項所述之封裝基板，其中，該增層部係形成於該基板本體之第一側及第二側上，且該第一側上之增層部之厚度係不同於該第二側上之增層部之厚度。 According to the package substrate described in claim 1, wherein the build-up part is formed on the first side and the second side of the substrate body, and the thickness of the build-up part on the first side is different from The thickness of the build-up portion on the second side. 如申請專利範圍第1項所述之封裝基板，其中，該增層部係形成於該基板本體之第一側及第二側上，且該第一側上之增層部之厚度係相同於該第二側上之增層部之厚度。 According to the package substrate described in claim 1, wherein the build-up portion is formed on the first side and the second side of the substrate body, and the thickness of the build-up portion on the first side is the same as The thickness of the build-up portion on the second side. 如申請專利範圍第1項所述之封裝基板，其中，該增層部係形成於該基板本體之第一側及第二側上，且該第一側上之增層部之寬度係不同於該第二側上之增層部之寬度。 According to the package substrate described in claim 1, wherein the build-up part is formed on the first side and the second side of the substrate body, and the width of the build-up part on the first side is different from The width of the build-up portion on the second side. 如申請專利範圍第1項所述之封裝基板，其中，該增層部係形成於該基板本體之第一側及第二側上，且該第一側上之增層部之寬度係相同於該第二側上之增層部之寬度。 According to the package substrate described in claim 1, wherein the build-up portion is formed on the first side and the second side of the substrate body, and the width of the build-up portion on the first side is the same as The width of the build-up portion on the second side. 如申請專利範圍第1項所述之封裝基板，其中，該增層部之頂部係具有絕緣保護層。 According to the package substrate described in item 1 of the scope of patent application, the top of the build-up portion has an insulating protective layer. 如申請專利範圍第1項所述之封裝基板，其中，該增層部係為框體結構。 According to the package substrate described in item 1 of the scope of patent application, the build-up portion is a frame structure. 一種電子封裝件，係包括：一如申請專利範圍第1項所述之封裝基板；以及至少一電子元件，係設於該基板本體之第一側及/或第二側上。 An electronic package includes: a package substrate as described in item 1 of the scope of the patent application; and at least one electronic component arranged on the first side and/or the second side of the substrate body. 如申請專利範圍第10項所述之電子封裝件，其中，該基板本體係定義有複數作用區域，且於單一作用區域內係設有複數規格相同之該電子元件。 For the electronic package described in item 10 of the scope of patent application, the substrate system defines a plurality of active areas, and a plurality of electronic components with the same specifications are arranged in a single active area. 如申請專利範圍第10項所述之電子封裝件，其中，該基板本體係定義有複數作用區域，且於單一作用區域內係設有複數規格不同之該電子元件。 For the electronic package described in item 10 of the scope of patent application, wherein the substrate system defines a plurality of active areas, and a plurality of electronic components with different specifications are arranged in a single active area. 如申請專利範圍第10項所述之電子封裝件，其中，該電子元件係位於該增層部所圍束之區域內。 The electronic package described in item 10 of the scope of patent application, wherein the electronic component is located in the area enclosed by the build-up portion. 如申請專利範圍第10項所述之電子封裝件，復包括封裝層，係形成於該基板本體之第一側及/或第二側上以包覆該電子元件。 The electronic package described in item 10 of the scope of patent application includes an encapsulation layer, which is formed on the first side and/or the second side of the substrate body to cover the electronic component. 如申請專利範圍第14項所述之電子封裝件，其中，該封裝層之厚度係大於或等於該增層部之厚度。 The electronic package described in item 14 of the scope of patent application, wherein the thickness of the encapsulation layer is greater than or equal to the thickness of the build-up layer. 如申請專利範圍第10項所述之電子封裝件，其中，該電子元件之厚度係相同於該增層部之厚度。 The electronic package described in item 10 of the scope of patent application, wherein the thickness of the electronic component is the same as the thickness of the build-up portion. 如申請專利範圍第10項所述之電子封裝件，其中，該電子元件之厚度係不同於該增層部之厚度。 The electronic package described in item 10 of the scope of patent application, wherein the thickness of the electronic component is different from the thickness of the build-up portion. 一種封裝基板之製法，係包括：提供一基板本體，其具有相對之第一側與第二側，並包含有至少一介電層及形成於該介電層上之線路層；形成增高層於該基板本體之第一側及/或第二側上；以及 移除該增高層之部分材質以形成有至少一開口，俾令該形成有至少一開口之增高層作為增層部。 A method for manufacturing a package substrate includes: providing a substrate body, which has a first side and a second side opposite to each other, and includes at least one dielectric layer and a circuit layer formed on the dielectric layer; On the first side and/or the second side of the substrate body; and Part of the material of the height-enhancing layer is removed to form at least one opening, so that the height-enhancing layer formed with at least one opening serves as a layer-enhancing part. 如申請專利範圍第18項所述之封裝基板之製法，其中，該增層部之材質係相同於該介電層之材質。 As for the manufacturing method of the package substrate described in the 18th patent application, the material of the build-up part is the same as the material of the dielectric layer. 如申請專利範圍第18項所述之封裝基板之製法，其中，該基板本體係定義有複數作用區域，且該增層部係位於各該作用區域之間。 According to the method for manufacturing the package substrate described in item 18 of the scope of patent application, the substrate system defines a plurality of active areas, and the build-up layer is located between the active areas. 如申請專利範圍第18項所述之封裝基板之製法，其中，該增層部係形成於該基板本體之第一側及第二側上，且該第一側上之增層部之厚度係不同於該第二側上之增層部之厚度。 As for the manufacturing method of the package substrate described in claim 18, wherein the build-up part is formed on the first side and the second side of the substrate body, and the thickness of the build-up part on the first side is Different from the thickness of the build-up portion on the second side. 如申請專利範圍第18項所述之封裝基板之製法，其中，該增層部係形成於該基板本體之第一側及第二側上，且該第一側上之增層部之厚度係相同於該基板本體之第二側上之增層部之厚度。 As for the manufacturing method of the package substrate described in claim 18, wherein the build-up part is formed on the first side and the second side of the substrate body, and the thickness of the build-up part on the first side is Same as the thickness of the build-up part on the second side of the substrate body. 如申請專利範圍第18項所述之封裝基板之製法，其中，該增層部係形成於該基板本體之第一側及第二側上，且該第一側上之增層部之寬度係不同於該第二側上之增層部之寬度。 The manufacturing method of the package substrate as described in claim 18, wherein the build-up portion is formed on the first side and the second side of the substrate body, and the width of the build-up portion on the first side is Different from the width of the build-up portion on the second side. 如申請專利範圍第18項所述之封裝基板之製法，其中，該增層部係形成於該基板本體之第一側及第二側上，且該第一側上之增層部之寬度係相同於該第二側上之增層部之寬度。 The manufacturing method of the package substrate as described in claim 18, wherein the build-up portion is formed on the first side and the second side of the substrate body, and the width of the build-up portion on the first side is Same as the width of the build-up part on the second side. 如申請專利範圍第18項所述之封裝基板之製法，其中，該增層部之頂部係具有絕緣保護層。 According to the manufacturing method of the package substrate described in item 18 of the scope of patent application, the top of the build-up part is provided with an insulating protective layer. 如申請專利範圍第18項所述之封裝基板之製法，其中，該增層部係為框體結構。 According to the manufacturing method of the package substrate described in item 18 of the scope of patent application, the layer build-up part is a frame structure. 如申請專利範圍第18項所述之封裝基板之製法，其中，該增高層係以壓合方式形成於該基板本體上。 According to the manufacturing method of the package substrate described in item 18 of the scope of patent application, the height-enhancing layer is formed on the substrate body by pressing. 如申請專利範圍第18項所述之封裝基板之製法，其中，該增高層之移除方式係以雷射方式或噴砂方式為之。 For the method of manufacturing the package substrate described in item 18 of the scope of patent application, the method of removing the height-enhancing layer is by laser or sandblasting. 一種電子封裝件之製法，係包括：提供一如申請專利範圍第1項所述之封裝基板；以及設置至少一電子元件於該基板本體之第一側及/或第二側上。 A manufacturing method of an electronic package includes: providing a package substrate as described in item 1 of the scope of patent application; and arranging at least one electronic component on the first side and/or the second side of the substrate body. 如申請專利範圍第29項所述之電子封裝件之製法，其中，該基板本體係定義有複數作用區域，且於單一作用區域內係設有複數規格相同之該電子元件。 For the method for manufacturing an electronic package described in item 29 of the scope of patent application, the substrate system defines a plurality of active areas, and a plurality of electronic components with the same specifications are arranged in a single active area. 如申請專利範圍第29項所述之電子封裝件之製法，其中，該基板本體係定義有複數作用區域，且於單一作用區域內係設有複數規格不同之該電子元件。 The method for manufacturing an electronic package as described in item 29 of the scope of patent application, wherein the substrate system defines a plurality of active areas, and a plurality of electronic components with different specifications are arranged in a single active area. 如申請專利範圍第29項所述之電子封裝件之製法，其中，該電子元件係位於該增層部所圍束之區域內。 According to the method for manufacturing the electronic package described in item 29 of the scope of patent application, the electronic component is located in the area enclosed by the build-up portion. 如申請專利範圍第29項所述之電子封裝件之製法，復包括形成封裝層於該基板本體之第一側及/或第二側上，以包覆該電子元件。 The method for manufacturing an electronic package as described in item 29 of the scope of the patent application includes forming an encapsulation layer on the first side and/or the second side of the substrate body to cover the electronic component. 如申請專利範圍第33項所述之電子封裝件之製法，其中，該封裝層之厚度係大於或等於該增層部之厚度。 The method for manufacturing an electronic package as described in item 33 of the scope of patent application, wherein the thickness of the encapsulation layer is greater than or equal to the thickness of the build-up layer. 如申請專利範圍第29項所述之電子封裝件之製法，其中，該電子元件之厚度係相同於該增層部之厚度。 The method for manufacturing an electronic package as described in item 29 of the scope of patent application, wherein the thickness of the electronic component is the same as the thickness of the build-up portion. 如申請專利範圍第29項所述之電子封裝件之製法，其中，該電子元件之厚度係不同於該增層部之厚度。 The method for manufacturing an electronic package as described in item 29 of the scope of patent application, wherein the thickness of the electronic component is different from the thickness of the build-up portion.
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