TW201810589A - Electronic package and the manufacture thereof - Google Patents

Abstract

Provided is an electronic package, comprising an insulating layer, an electronic element and a conductive bump embedded in the insulating layer, and a circuit structure formed on the insulating layer and electrically connected to the conductive bump, thereby avoiding the use of a conventional board body to reduce the overall package thickness and thus meet the demand for miniaturization. The invention further provides a method for manufacturing the electronic package as described above.

Description

Electronic package and its manufacturing method

The invention relates to a semiconductor packaging technology, in particular to an electronic packaging part and a manufacturing method thereof.

With the evolution of semiconductor packaging technology, semiconductor device (Semiconductor device) has developed different packaging types. In addition, in order to improve electrical functions and save packaging space, flip chip technology has been developed.

FIG. 1 is a schematic cross-sectional view of a conventional semiconductor package 1. As shown in FIG. 1, the manufacturing method of the semiconductor package 1 first provides a package substrate 10 having a board body 10a and a circuit structure 10b, and then a semiconductor device 11 is bonded to the circuit structure 10b by flip chip method, and then A packaging gel 13 is formed on the packaging substrate 10 to cover the semiconductor element 11.

Specifically, the semiconductor element 11 has an opposing active surface 11a and a non-active surface 11b. The active surface 11a has a plurality of electrode pads 110 for electrically connecting the electrode pad 110 and the circuit structure 10b through a plurality of solder bumps 12 Circuit layer 100, and the packaging gel 13 is formed between the semiconductor device 11 and the packaging substrate 10 to cover the solder bumps 12.

However, in the manufacturing process of the conventional semiconductor package 1, when the semiconductor element When the component 11 is of a large size or a high pin count, the flow of the packaging gel 13 is not easy to fill the space between the semiconductor element 11 and the packaging substrate 10, resulting in the semiconductor element 11 and the packaging substrate A void 14 is generated between 10, so during the subsequent curing of the encapsulant 13, the void 14 is prone to popcorn effect, which leads to a decrease in product yield.

Furthermore, in the conventional semiconductor package 1, since the package substrate 10 has a plate body 10a, it is difficult to effectively reduce the overall thickness of the semiconductor package 1, which cannot meet the needs of today's thin and light electronic products.

Therefore, how to overcome the shortcomings of the conventional technology is actually a technical problem that all sectors are desperately trying to solve.

In view of the lack of the above-mentioned conventional technology, the present invention provides an electronic package including: an insulating layer; an electronic component combined with a plurality of conductive bumps is embedded in the insulating layer, and a part of the surface of the conductive bump Exposed on the insulating layer; and the circuit structure is formed on a part of the surface of the insulating layer and the conductive bump exposed on the insulating layer and is electrically connected to the conductive bump.

The invention further provides a method for manufacturing an electronic package, comprising: disposing an electronic component combined with a plurality of conductive bumps on a carrier; forming an insulating layer on the carrier, so that the insulating layer covers the electronic component , And part of the surface of the conductive bump is exposed on the insulating layer; forming a circuit structure on the surface of the insulating layer and the conductive bump on the part of the insulating layer, and making the circuit structure electrically connected to the conductive bump ; And removing the carrier.

In the aforementioned electronic package and its manufacturing method, the electronic component has a phase The active surface and the non-active surface are coupled to the conductive bumps, so that the electronic component is electrically connected to the conductive bumps. For example, after removing the carrier, the non-active surface of the electronic component is exposed to the insulating layer; or, the non-active surface of the electronic component is combined with a heat sink.

In the aforementioned electronic package and its manufacturing method, after the carrier is removed, the electronic component is exposed to the insulating layer.

In the aforementioned electronic package and its manufacturing method, the conductive bumps are solder bumps.

In the aforementioned electronic package and its manufacturing method, the complex includes forming a plurality of conductive elements on the circuit structure.

In addition, in the aforementioned electronic package and its manufacturing method, the method further includes forming a plurality of conductive pillars in the insulating layer, and the conductive pillars are electrically connected to the circuit structure. For example, after removing the carrier, the end surface of the conductive pillar is exposed to the insulating layer. Further, the method includes connecting an electronic device to the end surface of the conductive post.

It can be seen from the above that the electronic package of the present invention and its manufacturing method mainly include first covering the electronic component and the conductive bump with the insulating layer, and then forming the circuit structure on the insulating layer, so the insulating layer does not need to flow Between the electronic component and the circuit structure, there is no void between the electronic component and the circuit structure, so compared with the conventional technology, the present invention can effectively improve the product yield.

Furthermore, the electronic package of the present invention only forms a circuit structure without using the board body of the conventional packaging substrate. Therefore, compared with the conventional technology, the overall thickness of the electronic package can be greatly reduced to meet the needs of light and thin .

1‧‧‧Semiconductor package

10‧‧‧Package substrate

10a‧‧‧Board

10b, 24, 24’‧‧‧ line structure

100,240‧‧‧ circuit layer

11‧‧‧Semiconductor components

11a, 21a‧‧‧action surface

11b, 21b‧‧‧non-acting surface

110,210‧‧‧electrode pad

12‧‧‧Solder bump

13‧‧‧Packing colloid

14‧‧‧Empty

2,3‧‧‧Electronic package

20‧‧‧Carrier

200‧‧‧Metal layer

21‧‧‧Electronic components

22‧‧‧conductive bump

22a‧‧‧Top surface

23‧‧‧Insulation

23a‧‧‧First surface

23b‧‧‧Second surface

241‧‧‧Conductor

242‧‧‧Dielectric layer

25‧‧‧Conducting element

26,26’‧‧‧Cooling parts

30‧‧‧conductive column

30a, 30b‧‧‧End

31‧‧‧Electronic device

32‧‧‧Connecting bump

Figure 1 is a schematic cross-sectional view of a conventional semiconductor package; and Figures 2A to 2E are cross-sectional schematic views of the manufacturing method of the first embodiment of the electronic package of the present invention; wherein, Figures 2E' and 2E" are Different embodiments of FIG. 2E; and FIGS. 3A to 3C are schematic cross-sectional views of the manufacturing method of the second embodiment of the electronic package of the present invention; wherein, FIG. 3C′ is another embodiment of FIG. 3C.

The following describes the implementation of the present invention by specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

It should be noted that the structure, ratio, size, etc. shown in the drawings of this specification are only used to match the content disclosed in the specification, for those who are familiar with this skill to understand and read, not to limit the implementation of the present invention The limited conditions do not have technical significance. Any modification of structure, change of proportional relationship or adjustment of size should still fall within the scope of the invention without affecting the efficacy and the purpose of the invention. The technical content disclosed by the invention can be covered. At the same time, the terms such as "upper", "first", "second" and "one" cited in this specification are only for the convenience of description, not to limit the scope of the invention, Changes or adjustments in the relative relationship are considered to be within the scope of the invention without substantial changes in the technical content.

Figures 2A to 2E are the first implementation of the electronic package 2 of the present invention A schematic cross-sectional view of an example manufacturing method.

As shown in FIG. 2A, an electronic component 21 incorporating a plurality of conductive bumps 22 is disposed on a carrier 20.

In this embodiment, a metal layer 200 is formed on the surface of the carrier 20. In this embodiment, the carrier 20 is a base material, such as a copper foil substrate or other plates, but there is no particular limitation. In this embodiment, the copper foil substrate is used as an example, and the metal layers 200 are provided on both sides.

Furthermore, the electronic element 21 is a semiconductor element, which is an active element, a passive element, or a combination of both, and the active element is, for example, a semiconductor chip, and the passive element is, for example, a resistor, a capacitor, and an inductor. For example, the electronic component 21 is a semiconductor wafer, which has an opposing active surface 21a and a non-active surface 21b, the active surface 21a has a plurality of electrode pads 210 to couple the conductive bumps 22, so that the conductive bumps 22 are electrically The electronic component 21 is connected to the electronic component 21, and the electronic component 21 is bonded to the metal layer 200 through a bonding layer (not shown) with its non-active surface 21b.

In addition, the conductive bump 22 is a solder bump.

As shown in FIG. 2B, an insulating layer 23 is formed on the metal layer 200 of the carrier 20 so that the insulating layer 23 covers the electronic component 21 and the conductive bumps 22.

In this embodiment, the insulating layer 23 defines opposite first surface 23a and second surface 23b, so that the second surface is bonded to the metal layer 200 of the carrier 20.

Furthermore, the insulating layer 23 is an epoxy encapsulant, which can be formed on the substrate by lamination or molding. On the carrier 20.

Moreover, the top surface 22a of the conductive bump 22 is exposed to the insulating layer 23. For example, the top surface 22a of the conductive bump 22 may be flush with the first surface 23a of the insulating layer 23 through a leveling process. Specifically, the leveling process can remove part of the material of the conductive bump 22 and part of the material of the insulating layer 23 by grinding.

As shown in FIGS. 2C to 2D, a circuit structure 24 is formed on the insulating layer 23 and the top surface 22a of the conductive bump 22, and the circuit structure 24 is electrically connected to the conductive bumps 22.

In this embodiment, the circuit structure 24 includes a circuit layer 240 disposed on the insulating layer 23 and the conductive bump 22, a plurality of conductors 241 disposed on the circuit layer 240, and a circuit covering the circuit The layer 240 and the dielectric layer 242 of the conductive bodies 241, and the circuit layer 240 is electrically connected to the conductive bumps 22, and exposes part of the surfaces of the conductive bodies 241 to the dielectric layer 242.

Furthermore, the material forming the circuit layer 240 is copper, and the conductor 241 is a copper pillar.

In addition, the dielectric layer 242 is formed on the insulating layer 23 by a casting method, a coating method or a pressing method, and the materials forming the dielectric layer 242 are a molding compound (Molding Compound) and a primer (Primer) , Or dielectric materials such as epoxy.

As shown in FIG. 2E, the carrier 20 and its metal layer 200 are removed so that the electronic component 21 is exposed to the insulating layer 23 to complete the electronic package 2 of the present invention.

In this embodiment, the non-active surface 21b of the electronic component 21 is exposed to The second surface 23b of the insulating layer 23 can form a plurality of conductive elements 25 such as solder balls on the conductor 241 of the circuit structure 24 for subsequent connection such as a circuit board, packaging structure or other structures (such as another Electronic device (figure omitted).

Furthermore, as shown in FIG. 2E', the circuit structure 24' formed on the insulating layer 23 may also have a plurality of circuit layers 240 and a plurality of dielectric layers 242.

Furthermore, as shown in FIG. 2E, a heat dissipating member 26 can be combined on the non-active surface 21b of the electronic component 21 and the second surface 23b of the insulating layer 23. In one embodiment, as in the 2A of this case The carrier used in the figure may be a metal plate, and only a part of the carrier is removed in the manufacturing process, and the carrier corresponding to the non-active surface 21b of the electronic component 21 is reserved as the heat dissipation member 26. The electronic of the present invention The manufacturing method of the package 2 is to first cover the electronic component 21 and the conductive bump 22 with the insulating layer 23, and then form the circuit structure 24 on the insulating layer 23, so the insulating layer 23 does not need to flow through the electrons Between the component 21 and the circuit structure 24. Therefore, when the electronic component 21 is of a large size or has a high pin count, no void will be generated between the electronic component 21 and the circuit structure 24, thus preventing the penetration of moisture The problem is that there will be no popcorn effect, so it can effectively improve the product yield.

Furthermore, the electronic package 2 of the present invention only forms the circuit structure 24 without making the board body of the conventional packaging substrate, so compared with the conventional technology, the overall thickness of the electronic package 2 can be greatly reduced to meet the requirements of lightness and thinness Demand.

3A to 3C are schematic cross-sectional views of the manufacturing method of the second embodiment of the electronic package 3 of the present invention. The difference between this embodiment and the first embodiment lies in the addition of conductive pillars, the other processes are approximately the same, so the following only describes the differences, The details are not repeated.

As shown in FIG. 3A, a plurality of conductive posts 30 and an electronic component 21 combined with a plurality of conductive bumps 22 are disposed on a carrier 20.

In this embodiment, the conductive pillar 30 is a copper pillar.

As shown in FIG. 3B, a process as shown in FIGS. 2B to 2D is performed to form the conductive pillars 30 in the insulating layer 23, and the conductive pillars 30 are electrically connected to the circuit layer 240 of the circuit structure 24.

In this embodiment, during the leveling process as shown in FIG. 2B, part of the material of the conductive pillar 30 may be removed so that one end surface 30a of the conductive pillar 30 is flush with the first surface 23a of the insulating layer 23 .

Furthermore, after the carrier 20 is removed, the other end surface 30b of the conductive pillar 30 is exposed on the second surface 23b of the insulating layer 23.

Furthermore, as shown in FIG. 3C, a plurality of conductive elements 25 such as solder balls can be formed on the conductor 241 of the circuit structure 24 for subsequent connection such as a circuit board, a packaging structure or other structures (such as another chip) The electronic device (figure omitted).

In addition, in the subsequent manufacturing process, as shown in FIG. 3C, an electronic device 31 can be connected to the end surface 30b of each conductive post 30 by the connecting bump 32, so that the electronic device 31 is electrically connected to each conductive post 30. For example, the electronic device 31 is a package, an active device, or a passive device.

It should be understood that, as shown in FIG. 3C', a heat dissipating member 26' may also be coupled to the non-active surface 21b of the electronic component 21. In one embodiment, the heat sink 26' may be a carrier (e.g., a metal plate) that remains at the non-active surface 21b of the electronic component 21.

The present invention provides an electronic package 2, 3, which includes: an insulating layer 23, an electronic component 21 having a plurality of conductive bumps 22, and a circuit structure 24.

The insulating layer 23 has a first surface 23a and a second surface 23b opposite to each other.

The electronic component 21 and the conductive bump 22 are embedded in the insulating layer 23, so that a part of the surface (top surface 22 a) of the conductive bump 22 is exposed on the first surface 23 a of the insulating layer 23.

The circuit structure 24 is formed on the first surface 23a of the insulating layer 23 and electrically connected to the conductive bump 22.

In one embodiment, the electronic component 21 has opposing active surfaces 21 a and non-active surfaces 21 b, and the active surfaces 21 a are combined with the conductive bumps 22.

In one embodiment, a heat sink 26, 26' is coupled to the non-active surface 21b of the electronic component 21.

In one embodiment, the electronic component 21 is exposed on the insulating layer 23. For example, the non-active surface 21b of the electronic component 21 is exposed on the second surface 23b of the insulating layer 23.

In one embodiment, the conductive bump 22 is a solder bump.

In one embodiment, the electronic packages 2 and 3 include a plurality of conductive elements 25 formed on the circuit structure 24.

In one embodiment, the electronic package 3 includes a plurality of conductive pillars 30 formed in the insulating layer 23, and the conductive pillars 30 are electrically connected to the circuit structure 24.

In one embodiment, the end surface 30b of the conductive pillar 30 is exposed to the insulation The second surface 23b of layer 23.

In one embodiment, the electronic package 3 includes an electronic device 31 connected to the end surface 30b of the conductive pillar 30.

In summary, the electronic package of the present invention and the manufacturing method thereof first cover the electronic component and the conductive bump with the insulating layer, and then form the circuit structure on the insulating layer, so the electronic component and There will be no voids between the circuit structures, which can effectively improve the product yield.

Furthermore, the electronic package of the present invention only forms a circuit structure, and does not need to make a board body of a conventional packaging substrate, so the overall thickness of the electronic package can be greatly reduced to meet the requirements of lightness and thinness.

The above embodiments are used to exemplify the principles and effects of the present invention, rather than to limit the present invention. Anyone who is familiar with this skill can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be as listed in the scope of patent application mentioned later.

2‧‧‧Electronic package

21‧‧‧Electronic components

21a‧‧‧action surface

21b‧‧‧non-acting surface

22‧‧‧conductive bump

23‧‧‧Insulation

23a‧‧‧First surface

23b‧‧‧Second surface

24‧‧‧ Line structure

241‧‧‧Conductor

25‧‧‧Conducting element

Claims (20)

An electronic package includes: an insulating layer; an electronic component combined with a plurality of conductive bumps is embedded in the insulating layer, and a part of the surface of the conductive bump is exposed to the insulating layer; and a circuit structure is The insulating layer and the conductive bump are exposed on a part of the surface of the insulating layer and are electrically connected to the conductive bump. The electronic package as described in item 1 of the patent application scope, wherein the electronic component has opposing active surfaces and non-active surfaces, and the active surface is bonded to the conductive bumps to make the electronic component electrically Connect the conductive bump. The electronic package as described in item 2 of the patent application scope, wherein the non-active surface of the electronic component is exposed to the insulating layer. The electronic package as described in item 2 of the patent application scope, wherein the non-active surface of the electronic component is combined with a heat sink. The electronic package as described in item 1 of the patent application scope, wherein the electronic component is exposed to the insulating layer. The electronic package as described in item 1 of the patent application range, wherein the conductive bump is a solder bump. The electronic package as described in item 1 of the patent application scope includes a plurality of conductive elements formed on the circuit structure. The electronic package as described in item 1 of the patent application scope includes a plurality of conductive pillars formed in the insulating layer, and the conductive pillars are electrically connected to the wire 路结构。 Road structure. The electronic package as described in item 8 of the patent application scope, wherein the end surface of the conductive pillar is exposed to the insulating layer. The electronic package as described in item 9 of the patent application scope includes an electronic device connected to the end surface of the conductive post. An electronic package manufacturing method includes: disposing an electronic component combined with a plurality of conductive bumps on a carrier; forming an insulating layer on the carrier, so that the insulating layer covers the electronic component, and allowing the Part of the surface of the conductive bump is exposed on the insulating layer; forming a circuit structure on the surface of the insulating layer and the conductive bump on the part of the insulating layer, and making the circuit structure electrically connected to the conductive bump; and removing The carrier. The method of manufacturing an electronic package as described in item 11 of the patent application scope, wherein the electronic component has opposite active surfaces and non-active surfaces, and the active surface is bonded to the conductive bumps to make the electronic component The conductive bump is electrically connected. The method for manufacturing an electronic package as described in item 12 of the patent application scope, wherein after removing the carrier, the non-active surface of the electronic component is exposed to the insulating layer. The method of manufacturing an electronic package as described in item 12 of the patent application scope, wherein a heat sink is incorporated on the non-active surface of the electronic component. For the manufacturing method of electronic packaging as described in item 11 of the patent scope, its In this case, after removing the carrier, the electronic component is exposed to the insulating layer. The method for manufacturing an electronic package as described in item 11 of the patent application scope, wherein the conductive bump is a solder bump. As described in the patent application item 11 of the manufacturing method of electronic packaging, complex includes forming a plurality of conductive elements on the circuit structure. According to the manufacturing method of the electronic package described in item 11 of the patent application scope, the method includes forming a plurality of conductive pillars in the insulating layer, and electrically connecting the conductive pillars to the circuit structure. The method for manufacturing an electronic package as described in item 18 of the patent application scope, wherein after removing the carrier, the end surface of the conductive post is exposed to the insulating layer. The method of manufacturing an electronic package as described in item 19 of the scope of patent application includes attaching an electronic device to the end surface of the conductive post.