CN111490025B - Electronic package, package substrate thereof and manufacturing method thereof - Google Patents

Electronic package, package substrate thereof and manufacturing method thereof Download PDF

Info

Publication number
CN111490025B
CN111490025B CN201910116194.4A CN201910116194A CN111490025B CN 111490025 B CN111490025 B CN 111490025B CN 201910116194 A CN201910116194 A CN 201910116194A CN 111490025 B CN111490025 B CN 111490025B
Authority
CN
China
Prior art keywords
build
layer
substrate body
package
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910116194.4A
Other languages
Chinese (zh)
Other versions
CN111490025A (en
Inventor
白裕呈
米轩皞
罗家麒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN111490025A publication Critical patent/CN111490025A/en
Application granted granted Critical
Publication of CN111490025B publication Critical patent/CN111490025B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

An electronic package, a package substrate and a manufacturing method thereof are provided, wherein a build-up part is formed on at least one side of a substrate body to ensure that the package substrate has a certain thickness, thereby avoiding the deformation problem of the package substrate in the transportation or packaging process.

Description

Electronic package, package substrate thereof and manufacturing method thereof
Technical Field
The present invention relates to an electronic package and a package substrate thereof, and more particularly, to an electronic package capable of preventing warpage, a package substrate thereof and a method for fabricating the same.
Background
With the rapid development of the electronic industry, many high-grade electronic products are gradually developed toward high integration directions such as light, thin, short, small, and the like, and with the evolution of the packaging technology, the packaging technology of the chip is more and more diversified, and the size or volume of the semiconductor packaging structure is also continuously reduced, so as to achieve the purpose of light, thin, short and small semiconductor packaging structure.
Fig. 1 is a cross-sectional view of a conventional semiconductor package 1. As shown in fig. 1, the semiconductor package 1 includes: the semiconductor package comprises a package substrate 1a, a semiconductor chip 19 bonded to the package substrate 1a by solder materials 13, and a molding compound (not shown) for encapsulating the semiconductor chip 19, wherein the package substrate 1a of the semiconductor package 1 is disposed on a circuit board 18 through the solder materials 13.
However, in recent years, as handheld electronic devices have been developed, the thinner the thickness of the package substrate 1a of the semiconductor package 1 becomes, the problem of warpage, bending or other deformation of the package substrate 1a during the packaging process or transportation occurs, and the solder materials 13', 13 ″ of the package substrate 1a cannot effectively bond the contacts 190 of the semiconductor chip 19 and the circuit board 18.
Therefore, how to overcome the problems in the prior art has become an issue to be solved.
Disclosure of Invention
In view of the above-mentioned shortcomings of the known technology, the present invention provides an electronic package, a package substrate thereof and a method for fabricating the same, which can avoid the problem of deformation of the package substrate during the transportation or packaging process.
The package substrate of the present invention includes: the substrate body is provided with a first side and a second side which are opposite, and comprises at least one dielectric layer and a circuit layer formed on the dielectric layer; and a build-up portion which is an insulator and is formed on the first side and/or the second side of the substrate body.
The invention also provides a manufacturing method of the packaging substrate, which comprises the following steps: providing a substrate body, wherein the substrate body is provided with a first side and a second side which are opposite to each other, and comprises at least one dielectric layer and a circuit layer formed on the dielectric layer; forming a build-up layer on the first side and/or the second side of the substrate body; and removing part of the material of the heightening layer to form at least one opening, so that the heightening layer with the at least one opening is used as the heightening part.
In the foregoing manufacturing method, the enhancement layer is formed on the substrate body in a pressing manner.
In the above-mentioned manufacturing method, the removing method of part of the raised layer is performed by laser method or sand blasting method.
In the foregoing package substrate and the method for fabricating the same, the material of the build-up portion is the same as the material of the dielectric layer.
In an embodiment, the package substrate and the method for fabricating the same, the substrate body defines a plurality of active regions, and the build-up layer is located between the active regions.
In an embodiment, the build-up portion is formed on the first side and the second side of the substrate body, and a thickness of the build-up portion on the first side of the substrate body is different from a thickness of the build-up portion on the second side of the substrate body.
In an embodiment, the build-up portion is formed on the first side and the second side of the substrate body, and a thickness of the build-up portion on the first side of the substrate body is equal to a thickness of the build-up portion on the second side of the substrate body.
In an embodiment, the build-up portion is formed on the first side and the second side of the substrate body, and a width of the build-up portion on the first side is the same as or different from a width of the build-up portion on the second side.
In the foregoing package substrate and the method for fabricating the same, the top of the build-up portion has an insulating protection layer.
In the package substrate and the method for manufacturing the same, the build-up portion is a frame structure.
In another aspect, the present invention provides an electronic package comprising: a package substrate as described above; and at least one electronic element arranged on the first side and/or the second side of the substrate body.
The invention also provides a manufacturing method of the electronic packaging piece, which comprises the following steps: providing a package substrate as described above; and arranging at least one electronic element on the first side and/or the second side of the substrate body.
In the electronic package and the method for manufacturing the same, the substrate body defines a plurality of active regions, and a plurality of electronic components with the same specification are disposed in a single active region.
In the electronic package and the method for manufacturing the same, the substrate body defines a plurality of active areas, and a plurality of electronic components with different specifications are disposed in a single active area.
In an embodiment, the electronic component is located in an area surrounded by the build-up portion.
The electronic package and the method for manufacturing the same further include a package layer formed on the first side and/or the second side of the substrate body to encapsulate the electronic component. For example, the thickness of the encapsulation layer is greater than or equal to the thickness of the build-up portion.
In the electronic package and the method for manufacturing the same, the thickness of the electronic element is the same as or different from the thickness of the enhanced portion.
Therefore, the electronic package, the package substrate thereof and the fabrication method thereof of the present invention mainly maintain a certain thickness of the package substrate through the design of the build-up portion, so compared with the prior art, the package substrate of the present invention can avoid the deformation problem such as warpage during the transportation or packaging process, thereby avoiding the decrease of the package yield of the electronic package.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional electronic package.
Fig. 2A to 2E are schematic cross-sectional views illustrating a method for manufacturing a package substrate and an electronic package according to the present invention.
Fig. 2C' is a schematic top view of fig. 2C.
Fig. 2E' is another embodiment of fig. 2E.
Fig. 3A and 3B are schematic cross-sectional views of other embodiments of the electronic package of the present invention.
Fig. 4A and 4B illustrate other embodiments of fig. 3A.
Description of the main component symbols
1 semiconductor package
1a package substrate
2, 2', 4a package substrate
3,3 ', 3a,3b,4, 4' electronic package
13, 13' solder material
18 circuit board
19 semiconductor chip
20 substrate body
20a first side
20b second side
21 elevated layer
22, 22', 42 ply-bonding section
23 second insulating protective layer
31a,31b,41 first electronic component
32 second electronic component
33 encapsulation layer
190 contact
200 dielectric layer
201 line layer
202,203 electric contact pad
210 opening
220 first insulating protective layer
230 open pore
310,320 conductive bump
311 solder material
A1, A2 region of action
D1, D2, D, H, H, H ', H', L1, L2, t, t1, t2, t1 ', t 2', R1 and R2 are thick
W1, W2, W1 ', W2' width.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the contents disclosed in the specification, and are not used for limiting the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, ratio relationship changes or size adjustments should still fall within the scope of the technical contents disclosed in the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "above", "first", "second" and "a" as used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship may be made without substantial technical changes.
Fig. 2A to 2C are schematic cross-sectional views illustrating a method for manufacturing the package substrate 2 according to the present invention.
In the present embodiment, the package substrate 2 is suitable for a double-sided molded electronic package 3, as shown in fig. 2E.
As shown in fig. 2A, a substrate body 20 having a first side 20a and a second side 20b opposite to each other is provided.
In the present embodiment, the substrate body 20 is mainly an insulating plate, a metal plate, or a semiconductor plate such as a wafer, a chip, a silicon material, a glass, etc. For example, the substrate body 20 is a circuit structure (not shown) having a core layer or a circuit structure (shown in fig. 2A) without a core layer, the circuit structure includes at least one dielectric layer 200 and a circuit layer 201, such as a redistribution layer (RDL), disposed on the dielectric layer 200, and the outermost circuit layer 201 has electrical contact pads 202, 203. Specifically, the circuit layer 201 is formed of copper, and the dielectric layer 200 is formed of a dielectric material such as Polyoxadiazole (PBO), Polyimide (PI), Prepreg (PP), or the like.
Alternatively, the substrate body may be a Silicon interposer (TSI) or a glass substrate having Through-Silicon vias (TSVs) and a wiring layer, such as a fan-out (fan out) RDL. Therefore, the embodiments of the substrate body are not limited to the above.
The thickness t of the substrate body 20 is about 60 to 75 micrometers (um) or less than 60 micrometers (the thickness of the electrical contact pad 202 is very thin relative to the thickness of the substrate body 20 and can be omitted).
As shown in fig. 2B, a raising layer 21 is formed on the first side 20a of the substrate body 20 to cover the electrical contact pads 202.
In the present embodiment, the material of the enhancement layer 21 includes an insulating material, such as a dielectric material, e.g., poly-p-xylylene (PBO), Polyimide (PI), prepreg (PP), etc., wherein the material forming the enhancement layer 21 may be the same as or different from the material forming the dielectric layer 200.
In addition, the thickness d of the height-increasing layer 21 is 5 to 25 μm (depending on the structural strength required of the substrate body 20).
As shown in fig. 2C, a plurality of openings 210 are formed in the elevated layer 21 by a patterning process (e.g., removing a portion of the material of the elevated layer 21 by using a laser or a sand blast), so that the elevated layer 21 forms an elevated portion 22, and a portion of the surface of the first side 20a of the substrate body 20 and the electrical contact pads 202 are exposed from the openings 210, so as to obtain the package substrate 2.
In the present embodiment, the layer-adding portion 22 is a closed ring-shaped frame structure, as shown in fig. 2C', which has no gap or interruption, and the substrate body 20 defines a plurality of active regions a1, a2 (the active regions a1, a2 correspond to the positions of the openings 210) to isolate the active regions a1, a2 from each other by the layer-adding portion 22 surrounding the edges of the active regions a1, a 2.
In addition, the layer-increasing portion 22 (the layer-increasing portion 21) can be formed on the substrate body 20 by pressing; alternatively, the build-up portion 22 can be bonded to the substrate body 20 by an adhesive layer or other methods. It should be understood that the fabrication method of forming the build-up portion 22 by pressing can save the cost.
In another embodiment, as shown in fig. 2D, the top of the build-up portion 22' includes a first insulating protection layer 220. For example, a first insulating protection layer 220 such as solder mask is formed on the original build-up portion 22, a second insulating protection layer 23 such as solder mask is formed on the second side 20b of the substrate body 20, and at least one opening 230 is formed in the second insulating protection layer 23, so that a portion of the surface of the second side 20b of the substrate body 20 and the electrical contact pad 203 are exposed out of the opening 230, thereby obtaining the package substrate 2'. Specifically, the thicknesses D1 and D2 of the package substrates 2 and 2' are less than 85 micrometers, so as to meet the requirement of thinning.
In addition, as shown in fig. 2E, in the subsequent process of manufacturing the electronic package 3, a plurality of first electronic components 31a,31b,41 may be disposed in the region surrounded by the build-up portions 22,22 'of the first side 20a of the substrate body 20, a second electronic component 32 may be disposed on the second side 20b of the substrate body 20 to electrically connect the electrical contact pads 202,203 and the circuit layer 201, and a package layer 33 may be formed on the first side 20a and the second side 20b of the substrate body 20 to cover the build-up portions 22, 22', the first electronic components 31a,31b,41 and the second electronic component 32.
The first electronic components 31a,31b,41 are combined on the first side 20a of the substrate body 20, and are active components, such as semiconductor chips, passive components, such as resistors, capacitors and inductors, or a combination thereof. For example, the first electronic component 31a,31b is an antenna-type semiconductor chip having an active surface and an inactive surface opposite to each other, the active surface is disposed on the electrical contact pad 202 in a flip-chip manner via a plurality of conductive bumps 310 to electrically connect to the circuit layer 201; alternatively, the first electronic component 31a,31b can be disposed on the first side 20a through the non-active surface, and the active surface is electrically connected to the circuit layer 201 through a plurality of bonding wires (not shown) by wire bonding; alternatively, the first electronic component 41 can be a passive component, which is disposed on the electrical contact pad 202 through a solder material 311 to electrically connect to the circuit layer 201. However, the way of electrically connecting the first electronic components 31a,31b,41 to the substrate body 20 is not limited to the above.
On the other hand, as shown in fig. 2E' and fig. 2C, the first electronic components 41 with the same specification, such as passive components with the same type, capacitance or resistance, can be disposed in the same active area a2, so as to provide a larger space area for disposing the build-up layer 22, thereby improving the rigidity or strength of the package substrate 2.
The second electronic component 32 is combined on the second side 20b of the substrate body 20 and is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, the second electronic component 32 is a semiconductor chip, and the active surface thereof is disposed on the electrical contact pad 203 in a flip-chip manner via a plurality of conductive bumps 320 to electrically connect to the circuit layer 201; alternatively, the second electronic component 32 can be electrically connected to the circuit layer 201 by wire bonding; alternatively, the second electronic element 32 may directly contact the circuit layer 201. However, the manner of electrically connecting the second electronic element 32 to the substrate body 20 is not limited to the above.
The package layer 33 is an insulating material, such as Polyimide (PI), dry film (dry film), and molding compound (molding compound) such as epoxy resin (epoxy), and can be formed on the substrate body 20 by pressing (laminating) or molding (molding). For example, the thickness H of the encapsulation layer 33 on the first side 20a of the substrate body 20 may be greater than the thicknesses L1, L2 of the build-up layers 22, 22', as shown in fig. 2E.
In other embodiments, the build-up portion may be disposed on the second side 20b of the substrate body 20 (e.g., the electronic package 3A shown in fig. 3A) as required. Specifically, the thickness t1 of the build-up layer 22 'on the first side 20a of the substrate body 20 may be the same or different from the thickness t2 of the build-up layer 22' on the second side 20 b. Furthermore, as shown in fig. 3A, the thickness h of the encapsulation layer 33 on the respective two sides of the substrate body 20 may be equal to the thicknesses t1, t2 of the build-up portion 22 ', i.e., the upper surface of the encapsulation layer 33 is flush with the upper surface of the build-up portion 22'; alternatively, the width W1 of the build-up layer 22 'on the first side 20a of the substrate body 20 may be different (as shown in fig. 3A) from the width W2 of the build-up layer 22' on the second side 20 b; alternatively, the width W1 'of the thickened portion 42 on the first side 20a is the same as the width W2' of the thickened portion 42 on the second side 20b (as shown in fig. 4A).
In another embodiment, the build-up portion may be disposed in an open region (e.g., a region where no electronic device is disposed) of the surface of the substrate body 20. Specifically, build-up section 22' of second side 20b as shown in FIG. 3A.
In another embodiment, the build-up layers 22, 22' are only disposed on the side of the substrate body 20 where the distribution area of the circuit layer 201 is smaller. Specifically, as shown in fig. 3B, in the electronic package 3B, the second side 20B of the substrate body 20 only needs to be provided with one chip (the second electronic component 32), so the second side 20B of the substrate body 20 has more space to form the build-up portion 22 ', and the build-up portion 22' is not provided on the first side 20 a.
Therefore, when the package substrate 2,2 'and the electronic package 3, 3', 3a,3b are to be thinned to less than 75 μm, the thickness of the package substrate 2,2 'is maintained at a certain thickness D1, D2 by forming the build-up portion 22, 22' on the substrate body 20, so that the problem of deformation such as warpage of the package substrate 2,2 'during transportation or packaging process can be avoided, and the reduction of the package yield of the electronic package 3, 3', 3a,3b can be effectively avoided.
In addition, as shown in fig. 4A and 4B of the electronic package 4,4 ', the thickness t1 ', t2 ' of the enhanced portion 42 may be lower than the thickness R1 of the first electronic component 31a,31B,41 and the thickness R2 of the second electronic component 32, so as to reduce the thickness H ', H ' of the package layer 33 and facilitate the thinning of the package substrate 4A, and the surface of the package layer 33 may be flush with the first electronic component 31a or the second electronic component 32, as shown in fig. 4B, to expose the first electronic component 31a or the second electronic component 32.
The present invention also provides a package substrate 2, 2', 4a, comprising: a substrate body 20 and at least one build-up portion 22, 22', 42.
The substrate body 20 has a first side 20a and a second side 20b opposite to each other, and includes at least one dielectric layer 200 and a circuit layer 201 disposed on the dielectric layer 200.
The build-up portions 22,22 ', 42 are formed on the first side 20a and/or the second side 20b of the substrate body 20, wherein the build-up portions 22, 22', 42 are insulators.
In one embodiment, the material of the build-up portions 22, 22', 42 is the same as the material of the dielectric layer 200.
In one embodiment, the first side 20a of the substrate body 20 defines a plurality of active areas a1, a2, and the build-up layers 22, 22', 42 are located between the active areas a1, a 2.
In one embodiment, the build-up portions 22 ', 42 are formed on the first side 20a and the second side 20b of the substrate body 20, and the thicknesses t1, t1 ' of the build-up portions 22 ', 42 on the first side 20a of the substrate body 20 are the same as or different from the thicknesses t2, t2 ' of the build-up portions 22 ', 42 on the second side 20b of the substrate body 20.
In one embodiment, referring to fig. 3A and 4A, the added-layer portions 22 ', 42 are formed on the first side 20a and the second side 20b of the substrate body 20, and the width W1 of the added-layer portion 22 ' on the first side 20a is different from the width W2 of the added-layer portion 22 ' on the second side 20 b; alternatively, the width W1 'of the raised portion 42 on the first side 20a is the same as the width W2' of the raised portion 42 on the second side 20 b.
In one embodiment, the build-up sections 22', 42 have an insulating protective layer 220 on top.
The present invention also provides an electronic package 3,3 ', 3a,3b,4, 4' comprising: the package substrate 2, 2', 4a,4b, at least one first electronic component 31a,31b,41 and at least one second electronic component 32.
The first electronic components 31a,31b,41 are disposed on the first side 20a of the substrate body 20.
The second electronic component 32 is disposed on the second side 20b of the substrate body 20.
In one embodiment of the electronic package 3', the first side 20a of the substrate body 20 defines a plurality of active areas a1, a2, and a plurality of first electronic components 41 with the same specification are disposed in a single active area a 2.
In one embodiment of the electronic package 3,3a,3b,4, 4', the first side 20a of the substrate body 20 defines a plurality of active areas a1, a2, and a plurality of first electronic components 31b,41 with different specifications are disposed in a single active area a 2.
In one embodiment, the first electronic component 31a,31b,41 or the second electronic component 32 is located in the region surrounded by the build-up portion 22, 22', 42.
In one embodiment, the thickness t1 ', t 2' of the build-up portion 42 is different from the thickness R1 of the first electronic component 31a,31b,41 and the thickness R2 of the second electronic component 32.
In an embodiment, the electronic package 3,3 ', 3a,3b,4, 4' further includes a package layer 33 formed on the first side 20a and/or the second side 20b of the substrate body 20 to encapsulate the first electronic component 31a,31b,41 or the second electronic component 32. For example, the thicknesses H, H 'of the encapsulation layer 33 are different from the thicknesses L1, L2, t1, t2, t 1', t2 'of the build-up layers 22', 42; alternatively, the thickness h of the encapsulation layer 33 on the respective two sides of the substrate body 20 may be the same as the thicknesses t1, t2 of the build-up portion 22'.
In summary, the electronic package, the package substrate thereof and the method for fabricating the same of the present invention mainly use the design of the build-up portion to keep the package substrate with a certain thickness, so as to avoid the problem of warpage of the package substrate during the transportation or packaging process, thereby avoiding the decrease of the package yield of the electronic package.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims (30)

1. A package substrate, comprising:
the substrate body is provided with a first side and a second side which are opposite, and comprises at least one dielectric layer and a circuit layer formed on the dielectric layer; and
the reinforced part is an insulator and is formed on the first side and the second side of the substrate body, wherein the top of the reinforced part is provided with a first insulating protective layer, and the first insulating protective layer does not exceed the side surface of the reinforced part;
the width of the thickened part on the first side is the same as that of the thickened part on the second side, and the second side of the substrate body is provided with a second insulating protection layer.
2. The package substrate of claim 1, wherein the build-up portion is formed of a same material as the dielectric layer.
3. The package substrate of claim 1, wherein the substrate body defines a plurality of active regions, and the build-up layer is located between the active regions.
4. The package substrate of claim 1, wherein a thickness of the build-up portion on the first side is different from a thickness of the build-up portion on the second side.
5. The package substrate of claim 1, wherein a thickness of the build-up portion on the first side is the same as a thickness of the build-up portion on the second side.
6. The package substrate of claim 1, wherein the build-up portion is a frame structure.
7. An electronic package, comprising:
a package substrate according to claim 1; and
at least one electronic element is arranged on the first side and/or the second side of the substrate body.
8. The electronic package of claim 7, wherein the substrate body defines a plurality of active areas, and a plurality of electronic components with the same specification are disposed in a single active area.
9. The electronic package of claim 7, wherein the substrate body defines a plurality of active areas, and a plurality of electronic components with different specifications are disposed in a single active area.
10. The electronic package of claim 7, wherein the electronic component is located within an area bounded by the build-up layer.
11. The electronic package according to claim 7, further comprising an encapsulation layer formed on the first side and/or the second side of the substrate body to encapsulate the electronic component.
12. The electronic package of claim 11, wherein the thickness of the encapsulation layer is greater than or equal to the thickness of the build-up portion.
13. The electronic package of claim 7, wherein the thickness of the electronic component is the same as the thickness of the build-up layer.
14. The electronic package of claim 7, wherein a thickness of the electronic component is different from a thickness of the build-up layer.
15. A method for manufacturing a package substrate is characterized by comprising the following steps:
providing a substrate body which is provided with a first side and a second side which are opposite, and comprises at least one dielectric layer and a circuit layer formed on the dielectric layer;
forming a build-up layer on the first side and the second side of the substrate body; and
removing part of the material of the heightening layer to form at least one opening, so that the heightening layer with the at least one opening is used as a heightening part, wherein the heightening part is formed on the first side and the second side of the substrate body, the top of the heightening part is provided with a first insulating protection layer, the first insulating protection layer does not exceed the side surface of the heightening part, the width of the heightening part on the first side is the same as that of the heightening part on the second side, and the second side of the substrate body is provided with a second insulating protection layer.
16. The method of claim 15, wherein the material of the build-up portion is the same as the material of the dielectric layer.
17. The method of claim 15, wherein the substrate body defines a plurality of active regions, and the build-up layer is located between the active regions.
18. The method of claim 15, wherein a thickness of the build-up portion on the first side is different from a thickness of the build-up portion on the second side.
19. The method of claim 15, wherein the thickness of the build-up portion on the first side is the same as the thickness of the build-up portion on the second side of the substrate body.
20. The method of claim 15, wherein the build-up portion is a frame structure.
21. The method of claim 15, wherein the enhancement layer is formed on the substrate body by pressing.
22. The method of claim 15, wherein the step of removing the enhancement layer is performed by laser or sand blasting.
23. A method of fabricating an electronic package, the method comprising:
providing a package substrate according to claim 1; and
at least one electronic element is arranged on the first side and/or the second side of the substrate body.
24. The method of claim 23, wherein the substrate body defines a plurality of active areas, and a plurality of electronic components with the same specification are disposed in a single active area.
25. The method of claim 23, wherein the substrate body defines a plurality of active areas, and a plurality of electronic components with different specifications are disposed in a single active area.
26. The method of claim 23, wherein the electronic component is located in a region surrounded by the build-up layer.
27. The method of claim 23, further comprising forming an encapsulation layer on the first side and/or the second side of the substrate body to encapsulate the electronic component.
28. The method of claim 27, wherein the thickness of the encapsulation layer is greater than or equal to the thickness of the build-up portion.
29. The method of claim 23, wherein the thickness of the electronic component is the same as the thickness of the build-up layer.
30. The method of claim 23, wherein the thickness of the electronic component is different from the thickness of the build-up layer.
CN201910116194.4A 2019-01-29 2019-02-15 Electronic package, package substrate thereof and manufacturing method thereof Active CN111490025B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW108103305 2019-01-29
TW108103305A TWI691041B (en) 2019-01-29 2019-01-29 Electronic package and package substrate thereof and method for manufacturing same

Publications (2)

Publication Number Publication Date
CN111490025A CN111490025A (en) 2020-08-04
CN111490025B true CN111490025B (en) 2022-09-09

Family

ID=71134378

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910116194.4A Active CN111490025B (en) 2019-01-29 2019-02-15 Electronic package, package substrate thereof and manufacturing method thereof

Country Status (2)

Country Link
CN (1) CN111490025B (en)
TW (1) TWI691041B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112038242A (en) * 2020-09-10 2020-12-04 华进半导体封装先导技术研发中心有限公司 Rewiring fan-out packaging method and structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101179062A (en) * 2002-05-27 2008-05-14 日本电气株式会社 Semiconductor device mounting board and semiconductor package
CN105323948A (en) * 2014-07-31 2016-02-10 恒劲科技股份有限公司 Interposer substrate and method of manufacturing the same
WO2018116477A1 (en) * 2016-12-22 2018-06-28 三井金属鉱業株式会社 Method for manufacturing multilayer wiring board

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4400802B2 (en) * 1999-08-23 2010-01-20 大日本印刷株式会社 Lead frame, manufacturing method thereof, and semiconductor device
JP4427874B2 (en) * 2000-07-06 2010-03-10 住友ベークライト株式会社 Multilayer wiring board manufacturing method and multilayer wiring board
US20040038442A1 (en) * 2002-08-26 2004-02-26 Kinsman Larry D. Optically interactive device packages and methods of assembly
JP2006059863A (en) * 2004-08-17 2006-03-02 Cmk Corp Package substrate and its manufacturing method
TWI315657B (en) * 2005-06-07 2009-10-01 Phoenix Prec Technology Corp Reverse build-up structure of circuit board
US20070120213A1 (en) * 2005-11-28 2007-05-31 Hiew Siew S Wire under dam package and method for packaging image-sensor
TWI281737B (en) * 2005-12-13 2007-05-21 Via Tech Inc Chip package and coreless package substrate thereof
TWI452661B (en) * 2007-01-30 2014-09-11 Package structure with circuit directly connected to chip
TWI384606B (en) * 2008-05-30 2013-02-01 Unimicron Technology Corp Package structure having semiconductor component embedded therein and fabrication method thereof
TWI421982B (en) * 2008-11-21 2014-01-01 Advanpack Solutions Pte Ltd Semiconductor substrate and manufacturing method thereof
TW201316462A (en) * 2011-10-13 2013-04-16 矽品精密工業股份有限公司 Package structure and fabrication method thereof
TWI490988B (en) * 2012-03-21 2015-07-01 Chipmos Technologies Inc Semiconductor package structure
US9312193B2 (en) * 2012-11-09 2016-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Stress relief structures in package assemblies
TWI581387B (en) * 2014-09-11 2017-05-01 矽品精密工業股份有限公司 Package structure and method of manufacture
US10177060B2 (en) * 2016-10-21 2019-01-08 Powertech Technology Inc. Chip package structure and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101179062A (en) * 2002-05-27 2008-05-14 日本电气株式会社 Semiconductor device mounting board and semiconductor package
CN105323948A (en) * 2014-07-31 2016-02-10 恒劲科技股份有限公司 Interposer substrate and method of manufacturing the same
WO2018116477A1 (en) * 2016-12-22 2018-06-28 三井金属鉱業株式会社 Method for manufacturing multilayer wiring board

Also Published As

Publication number Publication date
TW202029448A (en) 2020-08-01
TWI691041B (en) 2020-04-11
CN111490025A (en) 2020-08-04

Similar Documents

Publication Publication Date Title
US10424563B2 (en) Semiconductor package assembly and method for forming the same
US20190043819A1 (en) Electronic package having redistribution structure
US11081415B2 (en) Method for manufacturing electronic package
TWI622153B (en) System-in-package and method for fabricating the same
TWI728936B (en) Electronic packaging and manufacturing method thereof
CN110931450B (en) Electronic package and manufacturing method thereof
CN107403785B (en) Electronic package and manufacturing method thereof
CN110797293A (en) Package-on-package structure, method for fabricating the same and package structure
CN114121869A (en) Electronic package and manufacturing method thereof
CN111883506B (en) Electronic package, bearing substrate thereof and manufacturing method
CN107958844B (en) Packaging structure and manufacturing method thereof
CN113410215B (en) Semiconductor packaging structure and preparation method thereof
TWI712149B (en) Electronic package and method for fabricating the same
CN114628340A (en) Electronic package and manufacturing method thereof
CN111490025B (en) Electronic package, package substrate thereof and manufacturing method thereof
CN112054005B (en) Electronic package and manufacturing method thereof
CN114203686A (en) Electronic package and manufacturing method thereof
CN111883505A (en) Electronic package, bearing substrate thereof and manufacturing method
CN118039572A (en) Electronic package and method for manufacturing the same
CN116682802A (en) Electronic package and method for manufacturing the same
CN115527951A (en) Electronic package and manufacturing method thereof
CN112530901A (en) Electronic package and manufacturing method thereof
TW202115855A (en) Electronic package and method for manufacturing the same
TWI815639B (en) Electronic package and manufacturing method thereof
TWI839645B (en) Electronic package and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant