TW201316462A - Package structure and fabrication method thereof - Google Patents
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- TW201316462A TW201316462A TW100137117A TW100137117A TW201316462A TW 201316462 A TW201316462 A TW 201316462A TW 100137117 A TW100137117 A TW 100137117A TW 100137117 A TW100137117 A TW 100137117A TW 201316462 A TW201316462 A TW 201316462A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
本發明係有關於一種封裝件及其製法，尤指一種球柵陣列之封裝件及其製法。The present invention relates to a package and a method of manufacturing the same, and more particularly to a package of a ball grid array and a method of fabricating the same.
覆晶式球柵陣列(Flip Chip Ball Grid Array，簡稱FCBGA)半導體封裝件係為一種具有覆晶之球柵陣列之封裝結構，以使至少一半導體晶片的作用面(active surface)可藉由複數導電凸塊(bump)而電性連接至基板(substrate)之一表面上，並於該半導體晶片與基板之間填充底充材料(underfill)，以令該底充材料包覆於各該導電凸塊之間，而增強該等導電凸塊強度，並可支撐該半導體晶片的重量，同時於該基板之另一表面上植設複數可作為輸入/輸出(I/O)端之銲球(Solder Ball)；此設計不但可大幅縮減封裝件體積，以使半導體晶片與基板之比例更趨接近，同時，亦減去習知銲線(wire)設計，而可降低阻抗並提昇電性，因此已成為新世代半導體晶片與電子元件之主流封裝技術。A Flip Chip Ball Grid Array (FCBGA) semiconductor package is a package structure having a flip chip ball grid array such that an active surface of at least one semiconductor wafer can be made up of a plurality of active surfaces a conductive bump is electrically connected to one surface of the substrate, and an underfill is filled between the semiconductor wafer and the substrate, so that the underfill material is coated on each of the conductive bumps. Between the blocks, the strength of the conductive bumps is enhanced, and the weight of the semiconductor wafer can be supported, and a plurality of solder balls can be implanted on the other surface of the substrate as an input/output (I/O) end (Solder) Ball); This design not only greatly reduces the size of the package, but also makes the ratio of the semiconductor wafer to the substrate closer. At the same time, it also reduces the conventional wire design, which can reduce the impedance and improve the electrical properties. Become the mainstream packaging technology for new generation semiconductor wafers and electronic components.
然而，前述之用於覆晶式球柵陣列半導體封裝件中的基板容易在覆晶作業進行導電凸塊銲接之前，因基板厚度過薄，導致有翹曲(warpage)現象，從而影響半導體晶片之導電凸塊與基板之有效接著；再者，經迴銲(reflow)作業使導電凸塊銲接於基板後，基板之翹曲亦將導致該等導電凸塊之裂損(crack)，造成電性接著不良，而影響產品品質，且隨著封裝件的尺寸越來越大，翹曲的問題也越來越嚴重。However, the foregoing substrate used in the flip-chip ball grid array semiconductor package is prone to warpage before the conductive bump soldering in the flip chip operation, thereby causing warpage, thereby affecting the semiconductor wafer. The conductive bumps and the substrate are effectively followed; further, after the conductive bumps are soldered to the substrate by reflow operation, the warpage of the substrate will also cause cracks of the conductive bumps, resulting in electrical properties. Then it is bad, which affects the quality of the product, and as the size of the package becomes larger, the problem of warpage becomes more and more serious.
請參閱第1A與1A’圖，係習知例如第6,020,221、7,288,431與7,423,331號美國專利的覆晶式球柵陣列半導體封裝件之剖視圖，其中，第1A’圖係為第1A的俯視圖。Referring to Figures 1A and 1A', there are shown cross-sectional views of a flip-chip ball grid array semiconductor package of U.S. Patent Nos. 6,020,221, 7,288,431 and 7,423,331, wherein the first AA is a plan view of the first aspect.
如第1A與1A’圖所示，其係先於基板10之一表面上黏置加固件(stiffener)12，再於該基板10之表面上覆晶接置半導體晶片11，藉由該加固件12以固持該基板10，且避免該基板10發生翹曲問題，以使該半導體晶片11得以平穩地覆晶接置於該基板10之表面上，並得於迴銲製程後，減少該基板10翹曲。As shown in FIGS. 1A and 1A', a stiffener 12 is adhered to a surface of the substrate 10, and a semiconductor wafer 11 is flip-chip bonded to the surface of the substrate 10, by using the stiffener. 12 to hold the substrate 10 and avoid the problem of warpage of the substrate 10, so that the semiconductor wafer 11 can be smoothly flip-chip bonded to the surface of the substrate 10, and after the reflow process, the substrate 10 is reduced. Warping.
惟，前述方式必須預留基板周圍空間來黏合加固件，使得基板上的可用面積減少，進而壓縮被動元件佈局的空間，且導致半導體晶片的尺寸受到限制。However, in the foregoing manner, the space around the substrate must be reserved to adhere the reinforcement, so that the available area on the substrate is reduced, thereby compressing the space of the passive component layout, and the size of the semiconductor wafer is limited.
因此，如何避免上述習知技術中之種種問題，俾防止封裝件翹曲，且可彈性調整被動元件的佈局及半導體晶片的尺寸，實已成為目前亟欲解決的課題。Therefore, how to avoid the various problems in the above-mentioned prior art, to prevent the package from warping, and to elastically adjust the layout of the passive component and the size of the semiconductor wafer has become a problem to be solved at present.
有鑒於上述習知技術之缺失，本發明提供一種封裝件，係包括：具有相對之第一表面與第二表面的基板，且該第一表面上具有複數第一電性接點；接置於該第一表面上並與該基板電性連接的電子元件；形成於該第一表面上的封裝膠體，且包覆該電子元件；以及設置於該基板之第一表面上且電性連接至該第一電性接點的半導體晶片。In view of the above-mentioned shortcomings of the prior art, the present invention provides a package comprising: a substrate having a first surface and a second surface opposite thereto, and having a plurality of first electrical contacts on the first surface; An electronic component electrically connected to the substrate on the first surface; an encapsulant formed on the first surface, and covering the electronic component; and disposed on the first surface of the substrate and electrically connected to the A semiconductor wafer of a first electrical contact.
本發明復提供一種封裝件之製法，係包括：接置電子元件於一基板之第一表面上，其中，該第一表面上具有複數第一電性接點；於該第一表面上模壓形成包覆該電子元件的封裝膠體；以及接置一半導體晶片於該基板之第一表面上，並令該第一電性接點與半導體晶片電性連接。The invention provides a method for manufacturing a package, comprising: connecting an electronic component on a first surface of a substrate, wherein the first surface has a plurality of first electrical contacts; and molding on the first surface Encapsulating the encapsulant of the electronic component; and attaching a semiconductor wafer to the first surface of the substrate, and electrically connecting the first electrical contact to the semiconductor wafer.
由上可知，因為本發明之封裝件係先於基板上接置電子元件，再模壓形成包覆該電子元件的封裝膠體，該封裝膠體係可增進整體結構之剛性，以減輕翹曲現象，且電子元件係位於封裝膠體中，而不影響電子元件的佈局空間，也不會讓半導體晶片的尺寸受到限制，俾使電子元件的佈局與半導體晶片的尺寸設計更具有彈性；此外，該封裝膠體之材質為高分子材料，因而可輕易調整其熱膨脹係數(CTE)來因應各種不同封裝件的翹曲問題。As can be seen from the above, since the package of the present invention is connected to the electronic component before the substrate, and then molded to form the encapsulant covering the electronic component, the encapsulant system can improve the rigidity of the overall structure to reduce the warpage, and The electronic component is located in the encapsulant without affecting the layout space of the electronic component, and does not limit the size of the semiconductor wafer, so that the layout of the electronic component and the size design of the semiconductor wafer are more flexible; further, the encapsulant is The material is made of polymer material, so the coefficient of thermal expansion (CTE) can be easily adjusted to cope with the warpage of various packages.
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如「上」、「中心」及「一」等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "center" and "one" as used in the description are for convenience of description and are not intended to limit the scope of the invention. Adjustments, where there is no material change, are considered to be within the scope of the invention.
請參閱第2A至2D圖，係本發明之封裝件及其製法的剖視圖，其中，第2D’-1、2D’-2與2D’-3圖係第2D圖的俯視圖的不同實施態樣。Referring to Figures 2A through 2D, there are shown cross-sectional views of a package of the present invention and a method of manufacturing the same, wherein the second D'-1, 2D'-2 and 2D'-3 are different embodiments of the top view of Fig. 2D.
首先，如第2A圖所示，提供一具有相對之第一表面20a與第二表面20b的基板20，該第一表面20a與第二表面20b上分別具有複數第一電性接點21a與複數第二電性接點21b，並利用表面黏著技術(surface mount technology，簡稱SMT)於該第一表面20a上接置例如被動元件的電子元件22。First, as shown in FIG. 2A, a substrate 20 having an opposite first surface 20a and a second surface 20b is provided. The first surface 20a and the second surface 20b respectively have a plurality of first electrical contacts 21a and a plurality The second electrical contact 21b is connected to the electronic component 22 such as a passive component on the first surface 20a by surface mount technology (SMT).
如第2B圖所示，於該第一表面20a上模壓(molding)形成包覆該電子元件22的封裝膠體(encapsulant)23。As shown in FIG. 2B, an encapsulant 23 covering the electronic component 22 is formed on the first surface 20a.
如第2C圖所示，於該等第一電性接點21a上電性連接半導體晶片24，於本實施例中，該半導體晶片24係覆晶接置於該等第一電性接點21a上，但不以此為限。As shown in FIG. 2C, the semiconductor wafer 24 is electrically connected to the first electrical contacts 21a. In the embodiment, the semiconductor wafer 24 is overlying the first electrical contacts 21a. Up, but not limited to this.
如第2D圖所示，於該半導體晶片24與第一表面20a之間填入底充材料25，並可於各該第二電性接點21b上接置有銲球26或銲針。As shown in FIG. 2D, an underfill material 25 is filled between the semiconductor wafer 24 and the first surface 20a, and solder balls 26 or solder pins are attached to the second electrical contacts 21b.
由第2D’-1、2D’-2與2D’-3圖可知，該封裝膠體23係構成至少一具有中心開口230的環形體231，且該半導體晶片24係位於該中心開口230中。例如，該封裝膠體23係包括一具有中心開口230的環形體231，且該中心開口230係呈矩形，如第2D，-1圖所示；或者，該封裝膠體23係包括一具有中心開口230的環形體231，且該中心開口230係呈八角形，如第2D’-2圖所示；或者，該封裝膠體23係構成複數該環形體231，各該環形體231之中心開口230係呈矩形，並構成連接該等環形體231的條形體232，如第2D’-3圖所示。此外，該環形體231可為連續或分段之形式。As can be seen from the 2D'-1, 2D'-2 and 2D'-3 diagrams, the encapsulant 23 constitutes at least one annular body 231 having a central opening 230 in which the semiconductor wafer 24 is located. For example, the encapsulant 23 includes an annular body 231 having a central opening 230, and the central opening 230 is rectangular, as shown in FIG. 2D, -1; or the encapsulant 23 includes a central opening 230. The annular body 231, and the central opening 230 is octagonal, as shown in FIG. 2D'-2; or the encapsulant 23 is a plurality of the annular body 231, and the central opening 230 of each of the annular bodies 231 is Rectangular and forming a strip 232 connecting the annular bodies 231 as shown in Fig. 2D'-3. Furthermore, the annular body 231 can be in the form of a continuous or segmented form.
根據前述之製法，本發明復揭露一種封裝件，係包括：基板20，係具有相對之第一表面20a與第二表面20b，且該第一表面20a上具有複數第一電性接點21a；電子元件22，係接置於該第一表面20a上；封裝膠體23，係形成於該第一表面20a上，且包覆該電子元件22；以及半導體晶片24，係電性連接至該等第一電性接點21a。According to the foregoing method, the present invention recloses a package comprising: a substrate 20 having a first surface 20a and a second surface 20b opposite thereto, and having a plurality of first electrical contacts 21a on the first surface 20a; The electronic component 22 is electrically connected to the first surface 20a; the encapsulant 23 is formed on the first surface 20a and covers the electronic component 22; and the semiconductor wafer 24 is electrically connected to the first An electrical contact 21a.
於前述之封裝件中，該第二表面20b上並可具有複數第二電性接點21b，且於各該第二電性接點21b上可接置有銲球26或銲針。In the foregoing package, the second surface 20b may have a plurality of second electrical contacts 21b, and solder balls 26 or solder pins may be disposed on the second electrical contacts 21b.
於本實施例之封裝件中，該半導體晶片24係可覆晶接置於該等第一電性接點21a上，並於該半導體晶片24與第一表面20a之間可填入有底充材料25。In the package of the embodiment, the semiconductor wafer 24 is flip-chip bonded to the first electrical contacts 21a, and the underfill can be filled between the semiconductor wafer 24 and the first surface 20a. Material 25.
依上述之封裝件中，該封裝膠體23係構成至少一具有中心開口230的環形體231，且該半導體晶片24係位於該中心開口230中。In the above package, the encapsulant 23 constitutes at least one annular body 231 having a central opening 230, and the semiconductor wafer 24 is located in the central opening 230.
於本發明之封裝件中，該封裝膠體23係可構成複數該環形體231，以及連接該等環形體231之間的條形體232，又該中心開口230係可呈矩形或八角形。In the package of the present invention, the encapsulant 23 can constitute a plurality of the annular bodies 231, and the strips 232 connecting the annular bodies 231, and the central opening 230 can be rectangular or octagonal.
綜上所述，相較於習知技術，由於本發明之封裝件係先於基板上接置例如為被動元件的電子元件，再模壓形成包覆該電子元件的封裝膠體，該封裝膠體係可增進整體結構之剛性，以減輕基板翹曲現象，且該電子元件係位於封裝膠體中，所以不會影響電子元件的佈局空間，也不會讓半導體晶片的尺寸受到限制，俾使電子元件的佈局與半導體晶片的尺寸設計更具有彈性；此外，該封裝膠體之材質為高分子材料，因而可輕易調整其熱膨脹係數來因應各種不同封裝件的翹曲問題。In summary, compared with the prior art, since the package of the present invention is connected to an electronic component such as a passive component on a substrate, and then molded to form an encapsulant covering the electronic component, the encapsulant system can be The rigidity of the overall structure is improved to reduce the warpage of the substrate, and the electronic component is located in the encapsulant, so that the layout space of the electronic component is not affected, and the size of the semiconductor wafer is not limited, so that the layout of the electronic component is made. The size of the semiconductor wafer is more flexible; in addition, the material of the encapsulant is a polymer material, so that the thermal expansion coefficient can be easily adjusted to cope with the warpage of various packages.
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
10．．．基板10. . . Substrate
11,24．．．半導體晶片11,24. . . Semiconductor wafer
12．．．加固件12. . . Firmware
20．．．基板20. . . Substrate
20a．．．第一表面20a. . . First surface
20b．．．第二表面20b. . . Second surface
21a．．．第一電性接點21a. . . First electrical contact
21b．．．第二電性接點21b. . . Second electrical contact
22．．．電子元件twenty two. . . Electronic component
23．．．封裝膠體twenty three. . . Encapsulant
230．．．中心開口230. . . Center opening
231．．．環形體231. . . Ring body
232．．．條形體232. . . Strip
25．．．底充材料25. . . Bottom filling material
26．．．銲球26. . . Solder ball
第1A與1A’圖係習知之覆晶式球柵陣列半導體封裝件之剖視圖，其中，第1A’圖係為第1A的俯視圖；以及1A and 1A' are cross-sectional views of a conventional flip chip type ball grid array semiconductor package, wherein the first A' is a plan view of the first A;
第2A至2D圖係本發明之封裝件及其製法的剖視圖，其中，第2D’-1、2D’-2與2D’-3圖係第2D圖的俯視圖的不同實施態樣。2A to 2D are cross-sectional views showing a package of the present invention and a method of manufacturing the same, in which the second D'-1, 2D'-2 and 2D'-3 are different views of the plan view of the 2D.
20．．．基板20. . . Substrate
20a．．．第一表面20a. . . First surface
20b．．．第二表面20b. . . Second surface
21a．．．第一電性接點21a. . . First electrical contact
21b．．．第二電性接點21b. . . Second electrical contact
22．．．電子元件twenty two. . . Electronic component
23．．．封裝膠體twenty three. . . Encapsulant
230．．．中心開口230. . . Center opening
24．．．半導體晶片twenty four. . . Semiconductor wafer
25．．．底充材料25. . . Bottom filling material
26．．．銲球26. . . Solder ball
Claims (16)
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| TW100137117A TW201316462A (en) | 2011-10-13 | 2011-10-13 | Package structure and fabrication method thereof |
| CN2011103494156A CN103050449A (en) | 2011-10-13 | 2011-10-31 | Package and manufacturing method thereof |
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| TW100137117A TW201316462A (en) | 2011-10-13 | 2011-10-13 | Package structure and fabrication method thereof |
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| TW201316462A true TW201316462A (en) | 2013-04-16 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI614851B (en) * | 2015-03-03 | 2018-02-11 | 英特爾公司 | Electronic package that includes multi-layer stiffener |
| CN108689382A (en) * | 2014-05-30 | 2018-10-23 | 日月光半导体制造股份有限公司 | Micro electronmechanical sensing device further encapsulating structure and manufacturing process |
| WO2019075720A1 (en) * | 2017-10-20 | 2019-04-25 | 华为技术有限公司 | Chip package structure and packaging method |
| US10622314B2 (en) | 2017-12-07 | 2020-04-14 | Mediatek Inc. | Chip package structure |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI691041B (en) * | 2019-01-29 | 2020-04-11 | 矽品精密工業股份有限公司 | Electronic package and package substrate thereof and method for manufacturing same |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6020221A (en) * | 1996-12-12 | 2000-02-01 | Lsi Logic Corporation | Process for manufacturing a semiconductor device having a stiffener member |
| US6876553B2 (en) * | 2002-03-21 | 2005-04-05 | Broadcom Corporation | Enhanced die-up ball grid array package with two substrates |
| CN1992239A (en) * | 2005-12-26 | 2007-07-04 | 力成科技股份有限公司 | Ball grid array packaging structure |
| TW200741902A (en) * | 2006-04-17 | 2007-11-01 | Siliconware Precision Industries Co Ltd | Semiconductor package and, chip carrier thereof and method for fabricating the same |
| US8008133B2 (en) * | 2008-02-11 | 2011-08-30 | Globalfoundries Inc. | Chip package with channel stiffener frame |
-
2011
- 2011-10-13 TW TW100137117A patent/TW201316462A/en unknown
- 2011-10-31 CN CN2011103494156A patent/CN103050449A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108689382A (en) * | 2014-05-30 | 2018-10-23 | 日月光半导体制造股份有限公司 | Micro electronmechanical sensing device further encapsulating structure and manufacturing process |
| TWI614851B (en) * | 2015-03-03 | 2018-02-11 | 英特爾公司 | Electronic package that includes multi-layer stiffener |
| WO2019075720A1 (en) * | 2017-10-20 | 2019-04-25 | 华为技术有限公司 | Chip package structure and packaging method |
| US11309227B2 (en) | 2017-10-20 | 2022-04-19 | Huawei Technologies Co., Ltd. | Chip package structure having a package substrate disposed around a die |
| US10622314B2 (en) | 2017-12-07 | 2020-04-14 | Mediatek Inc. | Chip package structure |
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| CN103050449A (en) | 2013-04-17 |
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