TWI736736B - Electronic package and method of manufacture - Google Patents

Abstract

The invention provides an electronic package and a method for manufacturing the same, the method comprising: forming a packaging layer on a carrier structure having first and second electronic elements formed on two sides thereof for covering the first electronic element, and forming a reinforced member having an adjusting layer for covering the second electronic element with the adjusting layer, thereby adjusting the shape of the reinforced member and the amount of the adjusting layer to adjust the extent of warpage of the final package structure.

Description

Electronic package and its manufacturing method

The present invention relates to a semiconductor packaging technology, especially a multi-chip electronic package and its manufacturing method.

With the vigorous development of the electronics industry, electronic products are gradually moving towards the trend of multi-function and high performance. In order to meet the packaging requirements of miniaturization of electronic packages, the technology of Chip Scale Package (CSP) has been developed.

FIGS. 1A to 1E are schematic cross-sectional views of the manufacturing method of the semiconductor package 1 of the conventional wafer-level packaging.

As shown in FIG. 1A, a thermal release tape 100 is formed on a carrier 10.

Next, a plurality of semiconductor chips 11 are placed on the thermal release adhesive layer 100. The semiconductor chips 11 have opposite active surfaces 11a and non-active surfaces 11b. Each active surface 11a has a plurality of electrode pads 110, and Each of the acting surfaces 11 a is adhered to the thermal release adhesive layer 100.

As shown in FIG. 1B, an encapsulant 14 is formed on the thermal release adhesive layer 100 to cover the semiconductor chip 11.

As shown in FIG. 1C, the encapsulant 14 is baked to harden the thermal release adhesive layer 100 and the thermal release adhesive layer 100 and the carrier 10 are removed, and the active surface 11a of the semiconductor chip 11 is exposed outside. .

As shown in FIG. 1D, a circuit structure 16 is formed on the active surface 11a of the encapsulant 14 and the semiconductor chip 11, so that the circuit structure 16 is electrically connected to the electrode pad 110. Then, an insulating protection layer 18 is formed on the circuit structure 16, and the insulating protection layer 18 exposes part of the surface of the circuit structure 16 for bonding conductive elements 17 such as solder balls.

As shown in FIG. 1E, the singulation process is performed along the cutting path L shown in FIG. 1D to obtain a plurality of semiconductor packages 1 of the CSP package structure, which are electrically connected to the circuit board (Mother Board).

However, the conventional semiconductor package 1 only has the semiconductor chip 11 on one side, which limits the function and performance of the semiconductor package 1. In order to meet the requirements of the multi-function and high-efficiency of the terminal product, the cut-to-sing process is adopted. At this time, a plurality of semiconductor chips 11 are formed on the same plane (as shown in FIG. 1E), so that the plane area of the overall package structure is too large, and it is difficult to reduce the volume of the end product.

Furthermore, as shown in Figure 1F, although the industry has developed another semiconductor package 1', electronic components (semiconductor chips 11 or passive components 12) are arranged on and under the circuit structure 16 to strengthen the end product The function and performance of the circuit structure 16, but because the number of electronic components connected to the upper and lower sides of the circuit structure 16 is different, and the size of the electronic components is also different, so the upper and lower sides of the circuit structure 16 are packaged The thickness t1, t2 and volume of the colloids 14, 15 are also different, which causes the semiconductor package 1'to appear asymmetrical In this state, warpage occurs, and it cannot be effectively installed on the circuit board (such as a flexible board) of a terminal product (such as a mobile phone).

On the other hand, when the semiconductor package 1'is manufactured, since the entire set of molds are used to simultaneously form the encapsulation bodies 14,15, the thicknesses t1, t2 of the encapsulation bodies 14,15 cannot be controlled, so it is difficult to change the semiconductor package 1 'The degree of warpage.

Therefore, how to overcome various problems in the conventional technology has become an urgent issue to be solved at present.

In view of the deficiencies of the above-mentioned conventional technology, the present invention provides an electronic package, which includes: a supporting structure having a first side and a second side opposite to each other; and a first electronic component disposed on the first side of the supporting structure An encapsulation layer, which covers the first electronic component; a second electronic component, which is arranged on the second side of the carrying structure; a control layer which covers the second electronic component; and a strengthening member which is arranged on the At the regulatory level.

The present invention also provides a method for manufacturing an electronic package, which includes: providing a package structure and a reinforcing member including a control layer, wherein the package structure includes a supporting structure with a first side and a second side opposite to each other , A first electronic component arranged on the first side, an encapsulation layer covering the first electronic component, and a second electronic component arranged on the second side; and the reinforcing member is arranged on the first side of the supporting structure On both sides, and make the control layer cover the second electronic component.

The aforementioned manufacturing method further includes forming a stress part on the second side of the load-bearing structure before arranging the reinforcing member on the second side of the load-bearing structure. In one embodiment, the stress part is correspondingly located on the cutting path of the single cutting process

In the aforementioned electronic package and its manufacturing method, part of the surface of the first electronic component is exposed with the package layer.

In the aforementioned electronic package and its manufacturing method, the reinforcement is made of a material with a thermal expansion coefficient of less than 20.

In the aforementioned electronic package and its manufacturing method, the control layer is an insulating material.

In the aforementioned electronic package and its manufacturing method, the thickness of the package layer is equal to the sum of the thickness of the reinforcing member and the thickness of the control layer.

The aforementioned electronic package and its manufacturing method further include forming a plurality of conductive elements on the packaging layer, and the conductive elements are extended to the first side of the supporting structure to be electrically connected to the supporting structure.

It can be seen from the above that the electronic package of the present invention and its manufacturing method are mainly produced by first manufacturing the package structure, and then arranging the reinforcing member and the control layer on the second side of the supporting structure, so that the simulation can be learned in advance. The estimated warpage of the package assembly is used to adjust the shape of the reinforcement and the amount of the control layer. Therefore, compared with the entire set of molds in the prior art, the upper and lower sides of the package are formed at the same time. The reinforcement of the present invention is manufactured The molds of the packaging layer are mutually independent jigs, so the thickness and volume of the strengthening member and the thickness and volume of the control layer can be controlled, and the degree of warpage of the final structure of the electronic packaging can be adjusted.

1,1’‧‧‧Semiconductor package

10‧‧‧Carrier

100‧‧‧Thermal release adhesive layer

11‧‧‧Semiconductor chip

11a,21a,22a‧‧‧action surface

11b,21b,22b‧‧‧Non-acting surface

110‧‧‧electrode pad

12‧‧‧Passive components

14,15‧‧‧Packaging gel

16‧‧‧Line structure

17,27‧‧‧Conductive element

18‧‧‧Insulation protection layer

2‧‧‧Electronic package

2a‧‧‧Packaging structure

20‧‧‧Bearing structure

20a‧‧‧First side

20b‧‧‧Second side

200‧‧‧Line layer

201‧‧‧Insulation layer

21‧‧‧The first electronic component

210,220‧‧‧Conductive bump

22‧‧‧Second electronic component

23‧‧‧Reinforcement

24‧‧‧Stress Department

25‧‧‧Encapsulation layer

25b‧‧‧Outer surface

26‧‧‧Control layer

d,h1,h2,t,t1,t2‧‧‧Thickness

L,S‧‧‧cutting path

Figures 1A to 1E are cross-sectional schematic diagrams of the manufacturing method of a conventional semiconductor package; Figure 1F is a cross-sectional schematic diagram of another conventional semiconductor package; and Figures 2A to 2E are the manufacturing method of the electronic package of the present invention Profile of Schematic diagram; wherein, the 2D' picture is another embodiment of the 2D picture.

The following specific examples illustrate the implementation of the present invention. Those familiar with the art can easily understand the other advantages and effects of the present invention from the contents disclosed in this specification.

It should be noted that the structure, ratio, size, etc. shown in the drawings in this manual are only used to match the content disclosed in the manual for the understanding and reading of those who are familiar with the art, and are not intended to limit the implementation of the present invention. Therefore, it does not have any technical significance. Any structural modification, proportional relationship change or size adjustment should still fall within the original The technical content disclosed by the invention can be covered. At the same time, the terms "on", "first", "second" and "one" cited in this specification are only for ease of description and are not used to limit the scope of the present invention. The change or adjustment of the relative relationship shall be regarded as the scope of the implementation of the present invention without substantial changes to the technical content.

Please refer to FIGS. 2A to 2E, which are schematic cross-sectional views of the manufacturing method of the electronic package 2 of the present invention.

As shown in FIG. 2A, a package structure 2a and a reinforcing member 23 are provided, wherein the package structure 2a includes a carrier structure 20, at least one first electronic component 21, at least one second electronic component 22, and one An encapsulation layer 25, and a regulating layer 26 is formed on the reinforcing member 23.

The supporting structure 20 has a first side 20a and a second side 20b opposite to each other. In this embodiment, the bearing structure 20 has, for example, a core layer and A package substrate of the circuit part or a coreless package substrate with a circuit part, the circuit part of which has at least one insulating layer 201 and a circuit layer 200 disposed on the insulating layer 201, the circuit layer 200, for example Fan out (fan out) redistribution layer (RDL), and solder mask layers (not shown) can be formed on the first side 20a and the second side 20b as required. For example, the material for forming the circuit layer 200 is copper, and the material for forming the insulating layer 201 is such as polybenzoxazole (PBO), polyimide (PI), and prepreg. (Prepreg, PP for short) and other dielectric materials. It should be understood that the carrying structure can also be other carrying units capable of carrying electronic components such as chips, such as leadframes or silicon interposers, and is not limited to the above.

The first electronic component 21 is combined on the first side 20 a of the supporting structure 20. In this embodiment, the first electronic component 21 is an active component, a passive component, or a combination of both, and the active component is a semiconductor chip, and the passive component is a resistor, a capacitor, and an inductor. For example, if the first electronic component 21 is a semiconductor chip, which has an opposite active surface 21a and a non-active surface 21b, the first electronic component 21 has its active surface 21a arranged in a flip-chip manner by a plurality of conductive bumps 210. On the circuit layer 200 and electrically connected to the circuit layer 200; alternatively, the first electronic component 21 may be provided with the non-acting surface 21b on the first side 20a and the active surface 21a can be made by multiple bonding wires (figure omitted ) The circuit layer 200 is electrically connected by wire bonding. However, the manner in which the first electronic component 21 is electrically connected to the supporting structure 20 is not limited to the above.

The second electronic component 22 is combined on the second side 20b of the supporting structure 20. In this embodiment, the second electronic component 22 is an active component, a passive component, or a combination of the two, etc., wherein the active component is a semiconductor chip, and the passive component is a resistor, a capacitor, and an inductor. For example, if the second electronic component 22 is a semiconductor chip, which has an opposite active surface 22a and a non-active surface 22b, the second electronic component 22 has its active surface 22a formed by a plurality of conductive bumps 220 made of solder material. Flip-chip is provided on the circuit layer 200 and electrically connected to the circuit layer 200; alternatively, the second electronic component 22 can be electrically connected to the circuit layer 200 by wire bonding through a plurality of bonding wires (not shown); or , The second electronic component 22 can directly contact the circuit layer 200. However, the manner in which the second electronic component 22 is electrically connected to the supporting structure 20 is not limited to the above.

On the other hand, the active surface 21a of the first electronic component 21 and the active surface 22a of the second electronic component 22 are arranged in a face-to-face manner.

The encapsulation layer 25 is formed on the first side 20 a of the supporting structure 20 to cover the first electronic components 21. In this embodiment, the encapsulation layer 25 is made of insulating material, such as polyimide (PI), dry film, encapsulant such as epoxy resin, or molding compound ), which can be formed on the first side 20a of the supporting structure 20 by lamination or molding.

The strengthening member 23 is made of a material with a low coefficient of thermal expansion (CTE), for example, a material with a CTE of less than 20, preferably a material with a CTE of less than 10, such as glass, wafers, silicon plates, etc. .

The control layer 26 is an insulating material, and its type is polyimide (PI), dry film, epoxy resin, encapsulation material or semi-dry material. In this embodiment, the material of the control layer 26 and the material of the encapsulation layer 25 may be the same or different.

As shown in FIG. 2B, the reinforcing member 23 bonds the control layer 26 to the second side 20 b of the supporting structure 20 by lamination, so that the control layer 26 covers the second electronic component 22.

In this embodiment, the reinforcing member 23 is not electrically connected to the supporting structure 20, the first electronic component 21 and the second electronic component 22.

As shown in Figure 2C, a leveling process is performed to remove part of the material of the encapsulation layer 25 and part of the material of the first electronic component 21, so that the non-acting surface 21b of the first electronic component 21 and the encapsulation layer 25 The outer surface 25b is coplanar (flush).

In the present embodiment, the leveling process is leveled at one time by cutting; it is also possible to first remove part of the material of the packaging layer 25 by etching or grinding, and then remove the first electronic component 21 by grinding. Part of the material of the non-acting surface 21 b makes the non-acting surface 21 b of the first electronic component 21 flush with the outer surface 25 b of the encapsulation layer 25.

As shown in FIG. 2D, a plurality of conductive elements 27 are formed on the encapsulation layer 25 and extend to the first side 20a of the supporting structure 20 to electrically connect the circuit layer 200 for subsequent processes for connecting other electronic devices (Such as a package, a circuit board, or a chip, etc.), and the conductive element 27 is electrically connected to the circuit layer 200 of the carrying structure 20.

In this embodiment, the material for forming the conductive element 27 is, for example, copper material, solder material or other conductive materials.

Furthermore, to fabricate the conductive element 27, a through hole (not shown in the figure) is formed on the outer surface 25b of the encapsulation layer 25 to expose the circuit layer 200, and then the conductive elements 27 are formed in the through hole to contact the circuit layer 200. .

As shown in Fig. 2E, the cutting process is performed along the cutting path S shown in Fig. 2D.

In this embodiment, at least one pair of stress portions 24 (such as a concave shape or other structures) corresponding to the cutting path S can be formed on the second side 20b of the supporting structure 20 of the package assembly 2a shown in FIG. 2A. Shape) to relieve the stress of the overall structure warping caused by the first molding (ie, forming the encapsulation layer 25 on the first side 20a of the supporting structure 20), so as to improve the reliability in the subsequent manufacturing process. On the other hand, when the stress portion 24 is concave, it can be used as a half-cut cutting path to facilitate the alignment of a cutting tool (such as a laser or a knife) used in the cutting process. It should be understood that, as shown in FIG. 2D', in the package structure 2a shown in FIG. 2A, the stress portion 24 is not formed on the second side 20b of the supporting structure 20.

Therefore, the manufacturing method of the present invention is to first fabricate the package structure 2a (or the package layer 25), and then perform a pressing process on the second side 20b of the carrier structure 20, so that it can be simulated in advance (the package layer 25 is known The thickness h1 and volume of the package structure 2a are obtained (considering the thickness h2 and volume of the package layer 25 after the leveling process) to adjust the shape of the strengthening member 23 and the control layer 26 Therefore, compared with the entire set of molds in the prior art that simultaneously form the upper and lower encapsulation gels, the reinforcing member 23 of the present invention and the mold for making the encapsulation layer 25 are independent fixtures, so that the thickness of the reinforcing member 23 can be controlled d and volume (or shape) and the thickness t and volume of the control layer (such as the package The thickness h2 of the layer 25 is equal to the sum of the thickness d of the strengthening member 23 and the thickness t of the control layer), which can adjust the warpage of the final structure of the electronic package 2. For example, it is easy to convert a 12-inch wafer (12 The degree of warpage of "wafer) is controlled within the allowable range (such as +/-3.5mm).

Furthermore, when the number of the first electronic components 21 and the second electronic components 22 connected to the first side 20a and the second side 20b of the supporting structure 20 is different, and the first electronic components 21 and the second electronic components When the size of 22 is also different, by adjusting the shape of the reinforcing member 23 and the amount of the regulating layer 26, the electronic package 2 is prevented from being warped due to the asymmetric state. Therefore, the electronic package 2 It can be effectively installed on the circuit board (such as soft board substrate) of terminal products (such as mobile phones).

The present invention also provides an electronic package 2, which includes: a supporting structure 20, at least one first electronic component 21, an encapsulation layer 25, at least one second electronic component 22, a control layer 26, and a reinforcing member 23.

The supporting structure 20 has a first side 20 a and a second side 20 b opposite to each other and a circuit layer 200.

The first electronic component 21 is combined on the first side 20 a of the supporting structure 20 and electrically connected to the circuit layer 200.

The packaging layer 25 is formed on the first side 20 a of the supporting structure 20 to cover the first electronic component 21.

The second electronic component 22 is disposed on the second side 20 b of the supporting structure 20 and electrically connected to the circuit layer 200.

The control layer 26 is an insulating material formed on the second side 20 b of the supporting structure 20 to cover the second electronic component 22.

The reinforcing member 23 is formed on the regulating layer 26, and the reinforcing member is made of a material with a thermal expansion coefficient of less than 20.

In one embodiment, a part of the surface (inactive surface 21b) of the first electronic component 21 is exposed outside the outer surface 25b of the encapsulation layer 25.

In one embodiment, the thickness h2 of the encapsulation layer 25 is equal to the sum of the thickness d of the strengthening member 23 and the thickness t of the control layer (h2=d+t).

In one embodiment, the electronic package 2 includes a plurality of conductive elements 27, which are formed on the package layer 25 and extend to the first side 20a of the supporting structure 20 to electrically connect the circuit layer 200.

In summary, the electronic package of the present invention and its manufacturing method are controlled by the design of the strengthening member and the control layer, and by adjusting the thickness and volume of the strengthening member and the thickness and volume of the control layer. The degree of warpage of the final structure of the electronic package.

The above-mentioned embodiments are used to exemplify the principles and effects of the present invention, but not to limit the present invention. Anyone familiar with this technique can modify the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

2‧‧‧Electronic package

20‧‧‧Bearing structure

20a‧‧‧First side

20b‧‧‧Second side

200‧‧‧Line layer

21‧‧‧The first electronic component

22‧‧‧Second electronic component

23‧‧‧Reinforcement

25‧‧‧Encapsulation layer

26‧‧‧Control layer

27‧‧‧Conductive element

d,h2,t‧‧‧thickness

Claims (12)

An electronic package includes: a carrying structure having a first side and a second side opposite to each other; a first electronic component arranged on the first side of the carrying structure; an encapsulation layer covering the first electronic Element; a plurality of conductive elements are arranged in the encapsulation layer with one end exposed outside the encapsulation layer, and the other end extends to the first side of the carrying structure to electrically connect the carrying structure; the second electronic component is arranged on the carrying structure On the second side of the structure; the regulating layer, which covers the second electronic component; and the strengthening member, which is arranged on the regulating layer, wherein the thickness and volume of the packaging layer are considered to control the thickness and the strengthening member The volume and the thickness and volume of the control layer. According to the electronic package described in claim 1, wherein a part of the surface of the first electronic component exposes the encapsulation layer. The electronic package described in item 1 of the scope of patent application, wherein the reinforcing member is made of a material with a thermal expansion coefficient of less than 20. According to the electronic package described in item 1 of the scope of patent application, the control layer is an insulating material. The electronic package described in item 1 of the scope of patent application, wherein the thickness of the encapsulation layer is equal to the sum of the thickness of the reinforcing member and the thickness of the control layer. A method for manufacturing an electronic package includes: providing a package structure and a reinforcing member including a control layer, which Wherein, the package structure includes a supporting structure with opposite first and second sides, a first electronic component arranged on the first side, an encapsulation layer covering the first electronic component, and a carrier structure arranged on the first side. The second electronic component on both sides; adjust the amount of the control layer, wherein the thickness and volume of the encapsulation layer are considered to control the thickness and volume of the strengthening member and the thickness and volume of the control layer; and the strengthening member The control layer is bonded to the second side of the supporting structure by pressing, and the control layer covers the second electronic element; and a plurality of conductive elements are formed in the encapsulation layer to make one end of the conductive element The encapsulation layer is exposed, and the other end of the conductive element is extended to the first side of the supporting structure to be electrically connected to the supporting structure. According to the method for manufacturing an electronic package as described in item 6 of the scope of the patent application, a part of the surface of the first electronic component is exposed outside the package layer. The method for manufacturing an electronic package as described in item 6 of the scope of patent application, wherein the reinforcing member is made of a material with a thermal expansion coefficient of less than 20. The manufacturing method of the electronic package as described in item 6 of the scope of patent application, wherein the control layer is an insulating material. The method for manufacturing an electronic package as described in item 6 of the scope of patent application, wherein the thickness of the encapsulation layer is equal to the sum of the thickness of the reinforcing member and the thickness of the control layer. For example, the manufacturing method of the electronic package described in item 6 of the scope of patent application includes forming the application before the reinforcement is placed on the second side of the supporting structure. The force part is on the second side of the bearing structure. According to the method for manufacturing an electronic package described in item 11 of the scope of patent application, the stress part is correspondingly located on the cutting path of the singulation process.

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