TW201933563A - Electronic package and method of manufacture - Google Patents

Abstract

The invention provides an electronic package and a method for manufacturing the same, the method comprising: forming a packaging layer on a carrier structure having first and second electronic elements formed on two sides thereof for covering the first electronic element, and forming a reinforced member having an adjusting layer for covering the second electronic element with the adjusting layer, thereby adjusting the shape of the reinforced member and the amount of the adjusting layer to adjust the extent of warpage of the final package structure.

Description

Electronic package and manufacturing method thereof

The invention relates to a semiconductor packaging technology, in particular to a multi-chip electronic package and a method for manufacturing the same.

With the vigorous development of the electronics industry, electronic products are gradually moving towards the trend of multifunctional and high performance. In order to meet the packaging needs of miniaturization of electronic packages, the technology of Chip Scale Package (CSP) has been developed.

1A to 1E are schematic cross-sectional views of a conventional method for manufacturing a semiconductor package 1 of a wafer-level package.

As shown in FIG. 1A, a thermal release tape 100 is formed on a carrier 10.

Next, a plurality of semiconductor wafers 11 are placed on the thermal release adhesive layer 100. The semiconductor wafers 11 have opposite active surfaces 11a and non-active surfaces 11b, and each of the active surfaces 11a has a plurality of electrode pads 110, and Each of the active surfaces 11 a is adhered to the thermal release adhesive layer 100.

As shown in FIG. 1B, an encapsulant 14 is formed on the thermal release adhesive layer 100 to cover the semiconductor wafer 11.

As shown in FIG. 1C, the encapsulant 14 is baked to harden the thermal release adhesive layer 100 and remove the thermal release adhesive layer 100 and the carrier 10, and the active surface 11a of the semiconductor wafer 11 is exposed outside. .

As shown in FIG. 1D, a circuit structure 16 is formed on the active surface 11 a of the packaging gel 14 and the semiconductor wafer 11, so that the circuit structure 16 is electrically connected to the electrode pad 110. Next, an insulating protection layer 18 is formed on the circuit structure 16, and a part of the surface of the circuit structure 16 is exposed from the insulating protection layer 18 for bonding the conductive element 17 such as a solder ball.

As shown in FIG. 1E, a singulation process is performed along the cutting path L as shown in FIG. 1D to obtain a plurality of semiconductor packages 1 with a CSP package structure, which are electrically connected to a mother board.

However, it is known that the semiconductor package 1 only has the semiconductor chip 11 on one side, so that the function and efficiency of the semiconductor package 1 are limited, and in order to meet the requirements of multi-function and high efficiency of the end product, a single-cut process At this time, a plurality of semiconductor wafers 11 are formed on the same plane (as shown in FIG. 1E), so that the plane area of the overall package structure is too large, so it is difficult to reduce the volume of the end product.

Furthermore, as shown in Figure 1F, although the industry has developed another semiconductor package 1 ', electronic components (semiconductor wafer 11 or passive component 12) are arranged above and below the circuit structure 16 to strengthen end products. Functions and performance, but because the number of electronic components connected above and below the circuit structure 16 is different, and the size of these electronic components is also different, the package above and below the circuit structure 16 The thicknesses t1, t2 and volume of the colloids 14, 15 are also different, so that the semiconductor package 1 'appears asymmetrical. In some cases, warpage occurs, and it cannot be effectively installed on a circuit board (such as a flexible board) of a terminal product (such as a mobile phone).

On the other hand, when the semiconductor package 1 ′ is manufactured, the packaging colloids 14 and 15 are simultaneously formed by using a whole set of molds, so the thickness t1 and t2 of the packaging colloids 14 and 15 cannot be adjusted, and it is difficult to change the semiconductor package 1 'The degree of warping.

Therefore, how to overcome the various problems in the conventional technology has become an urgent problem to be solved.

In view of the lack of the above-mentioned conventional technology, the present invention provides an electronic package including: a supporting structure having a first side and a second side opposite to each other; and a first electronic component provided on the first side of the supporting structure An encapsulation layer that covers the first electronic component, a second electronic component that is provided on the second side of the carrier structure, a control layer that covers the second electronic component, and a reinforcement member that is provided on the On the regulatory layer.

The invention also provides a method for manufacturing an electronic package, which includes: providing a package structure and a reinforcing member including a regulating layer, wherein the package structure includes a bearing structure with opposite first and second sides A first electronic component provided on the first side, a packaging layer covering the first electronic component, and a second electronic component provided on the second side; and the reinforcement member is provided on the first side of the bearing structure. On both sides, the second electronic component is covered by the control layer.

In the foregoing manufacturing method, the method further includes forming a stress portion on the second side of the load-bearing structure before the reinforcement member is provided on the second side of the load-bearing structure. In one embodiment, the stress portion is located on the cutting path of the cutting process.

In the aforementioned electronic package and its manufacturing method, part of the surface of the first electronic component is exposed to the packaging layer.

In the aforementioned electronic package and its manufacturing method, the reinforcing member is made of a material having a thermal expansion coefficient of less than 20.

In the aforementioned electronic package and its manufacturing method, the control layer is an insulating material.

In the aforementioned electronic package and its manufacturing method, the thickness of the packaging layer is equal to the sum of the thickness of the reinforcing member and the thickness of the control layer.

In the aforementioned electronic package and its manufacturing method, the method further includes forming a plurality of conductive elements on the packaging layer, and the conductive elements extend to the first side of the supporting structure to electrically connect the supporting structure.

It can be known from the above that the electronic package and the manufacturing method thereof of the present invention mainly include firstly manufacturing the packaging structure, and then setting the reinforcing member and the regulating layer on the second side of the bearing structure, so that the simulation can be known in advance. The estimated warpage of the packaging structure to adjust the shape of the reinforcement and the amount of the control layer. Therefore, compared with the conventional set of molds, the upper and lower packaging colloids are simultaneously formed. The molds of the packaging layer are independent jigs to each other, so the thickness and volume of the reinforcement member and the thickness and volume of the control layer can be controlled, and the degree of warpage of the final structure of the electronic package can be adjusted.

1,1’‧‧‧ semiconductor package

10‧‧‧ Carrier

100‧‧‧ Heat release coating

11‧‧‧Semiconductor wafer

11a, 21a, 22a‧‧‧ surface

11b, 21b, 22b ‧‧‧ non-active surface

110‧‧‧electrode pad

12‧‧‧ Passive components

14, 15‧‧‧ encapsulated colloid

16‧‧‧ Line Structure

17,27‧‧‧ conductive elements

18‧‧‧Insulation protective layer

2‧‧‧electronic package

2a‧‧‧Packaging Structure

20‧‧‧ bearing structure

20a‧‧‧first side

20b‧‧‧Second side

200‧‧‧ Line layer

201‧‧‧ Insulation

21‧‧‧The first electronic component

210,220‧‧‧Conductive bumps

22‧‧‧Second electronic component

23‧‧‧ Reinforcement

24‧‧‧ Stress Department

25‧‧‧Encapsulation Layer

25b‧‧‧outer surface

26‧‧‧Regulatory layer

d, h1, h2, t, t1, t2‧‧‧thickness

L, S‧‧‧cut path

Figures 1A to 1E are schematic cross-sectional views of a conventional method for manufacturing semiconductor packages; Figure 1F is a schematic cross-sectional view of another conventional semiconductor package; and Figures 2A to 2E are methods of manufacturing an electronic package according to the present invention. Profile Schematic diagram; wherein, the 2D 'diagram is another embodiment of the 2D diagram.

The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

It should be noted that the structures, proportions, sizes, etc. shown in the drawings in this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. The limited conditions are not technically significant. Any modification of the structure, change of the proportional relationship, or adjustment of the size should still fall within the scope of this invention without affecting the effects and goals that can be achieved by the present invention. The technical content disclosed by the invention can be covered. At the same time, the terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of description, and are not intended to limit the scope of the present invention. Changes or adjustments in their relative relationships shall be considered to be the scope of the present invention without substantial changes in the technical content.

Please refer to FIGS. 2A to 2E, which are schematic cross-sectional views of a method for manufacturing the electronic package 2 according to the present invention.

As shown in FIG. 2A, a packaging structure 2a and a reinforcing member 23 are provided, wherein the packaging structure 2a includes a carrying structure 20, at least one first electronic component 21, at least one second electronic component 22, and a The encapsulation layer 25 is formed on the reinforcing member 23.

The supporting structure 20 has a first side 20a and a second side 20b opposite to each other. In this embodiment, the supporting structure 20 has, for example, a core layer and A packaging substrate (substrate) of a circuit part or a coreless packaging substrate having a circuit part, the circuit part has at least one insulating layer 201 and a circuit layer 200 provided on the insulating layer 201. The circuit layer 200 is, for example, Fan out redistribution layer (RDL), and a solder resist layer (not shown) can be formed on the first side 20a and the second side 20b as required. For example, the material forming the circuit layer 200 is copper, and the material forming the insulating layer 201 is, for example, polybenzoxazole (PBO), polyimide (PI), or prepreg. (Prepreg, PP for short) and other dielectric materials. It should be understood that the supporting structure may also be other supporting units for supporting electronic components such as wafers, such as lead frames or silicon interposers, and are not limited to the above.

The first electronic component 21 is coupled to the first side 20 a of the supporting structure 20. In this embodiment, the first electronic component 21 is an active component, a passive component, or a combination thereof, and the active component is a semiconductor wafer, for example, and the passive component is a resistor, a capacitor, or an inductor. For example, if the first electronic component 21 is a semiconductor wafer and has opposite active surfaces 21a and non-active surfaces 21b, the first electronic component 21 is provided on its active surface 21a by a plurality of conductive bumps 210 in a flip-chip manner. The circuit layer 200 is electrically connected to the circuit layer 200; or, the first electronic component 21 can be provided with the non-active surface 21b on the first side 20a and the active surface 21a can be provided by a plurality of bonding wires (not shown) ) The wiring layer 200 is electrically connected in a wired manner. However, the manner in which the first electronic component 21 is electrically connected to the carrier structure 20 is not limited to the above.

The second electronic component 22 is coupled to the second side 20 b of the supporting structure 20. In this embodiment, the second electronic component 22 is an active component, a passive component, or a combination of the two. The active component is, for example, a semiconductor wafer, and the passive component is, for example, a resistor, a capacitor, and an inductor. For example, if the second electronic component 22 is a semiconductor wafer and has opposite active surfaces 22a and non-active surfaces 22b, the second electronic component 22 uses its active surface 22a by a plurality of conductive bumps 220 such as solder material to A flip-chip method is provided on the circuit layer 200 and is electrically connected to the circuit layer 200; or, the second electronic component 22 may be electrically connected to the circuit layer 200 by a plurality of bonding wires (not shown); or The second electronic component 22 can directly contact the circuit layer 200. However, the manner in which the second electronic component 22 is electrically connected to the carrier structure 20 is not limited to the above.

On the other hand, the active surface 21a of the first electronic component 21 and the active surface 22a of the second electronic component 22 are disposed face to face.

The packaging layer 25 is formed on the first side 20 a of the supporting structure 20 to cover the first electronic components 21. In this embodiment, the encapsulation layer 25 is an insulating material, such as polyimide (PI), dry film, encapsulation gel such as epoxy, or a molding compound. ), Which can be formed on the first side 20a of the supporting structure 20 by lamination or molding.

The reinforcing member 23 is made of a material with a low coefficient of thermal expansion (CTE), for example, a material with a CTE of less than 20, preferably a material with a CTE of less than 10, such as glass, wafer, silicon plate, etc .

The regulating layer 26 is an insulating material, and its type is polyimide (PI), a dry film, an epoxy resin, a packaging material or a semi-dry material. In this embodiment, the material of the regulating layer 26 and the packaging layer 25 may be the same or different.

As shown in FIG. 2B, the reinforcing member 23 bonds the regulating layer 26 to the second side 20 b of the supporting structure 20 in a lamination manner, so that the regulating layer 26 covers the second electronic component 22.

In this embodiment, the reinforcing member 23 is not electrically connected to the supporting structure 20, the first electronic component 21 and the second electronic component 22.

As shown in FIG. 2C, a leveling process is performed to remove part of the material of the packaging layer 25 and part of the material of the first electronic component 21, so that the non-active surface 21b of the first electronic component 21 and the packaging layer 25 The outer surface 25b is coplanar (flat).

In this embodiment, the leveling process is performed by one-time leveling by cutting. Alternatively, part of the material of the packaging layer 25 may be removed by etching or grinding, and then the first electronic component 21 may be removed by grinding. The material of the non-active surface 21 b is such that the non-active surface 21 b of the first electronic component 21 is flush with the outer surface 25 b of the packaging layer 25.

As shown in FIG. 2D, a plurality of conductive elements 27 are formed on the encapsulation layer 25 and extend to the first side 20a of the carrier structure 20 to electrically connect the circuit layer 200 for subsequent processes to connect other electronic devices. (Such as a package, a circuit board, or a chip), and the conductive element 27 is electrically connected to the circuit layer 200 of the carrier structure 20.

In this embodiment, the material for forming the conductive element 27 is, for example, a copper material, a solder material, or other conductive material.

Furthermore, the conductive element 27 is formed by forming a through hole (not shown) to expose the circuit layer 200 on the outer surface 25b of the encapsulation layer 25, and then forming the conductive elements 27 in the through hole to contact the circuit layer 200. .

As shown in FIG. 2E, the cutting process is performed along the cutting path S shown in FIG. 2D.

In this embodiment, at least one pair of stress portions 24 (such as a concave shape or other structure) corresponding to the cutting path S may be selectively formed on the second side 20b of the carrier structure 20 of the packaging structure 2a shown in FIG. 2A. Shape) to release the stress of the overall structure caused by the first molding (that is, the packaging layer 25 is formed on the first side 20a of the carrier structure 20), so as to improve the reliability in subsequent processes. On the other hand, when the stress portion 24 is concave, it can be used as a half-cut cutting path to facilitate alignment of a cutting tool (such as a laser or a cutter) used in the cutting process. It should be understood that, as shown in FIG. 2D ′, in the packaging structure 2 a shown in FIG. 2A, the stress portion 24 is not formed on the second side 20 b of the bearing structure 20.

Therefore, the manufacturing method of the present invention is to first manufacture the packaging structure 2a (or the packaging layer 25), and then perform a compression bonding process on the second side 20b of the carrier structure 20, so it can be simulated in advance (the packaging layer 25 is known Thickness h1 and volume) to know the estimated warpage of the packaging structure 2a (considering the thickness h2 and volume of the packaging layer 25 after the leveling process) to adjust the shape of the reinforcing member 23 and the regulation layer 26 The amount of use, compared to the conventional set of molds at the same time to form the upper and lower packaging gel, the reinforcement member 23 of the present invention and the mold making the packaging layer 25 are independent jigs from each other, so the thickness of the reinforcement member 23 can be controlled d and volume (or shape) and the thickness of the control layer t and volume (such as the package The thickness h2 of the layer 25 is equal to the sum of the thickness d of the reinforcement member 23 and the thickness t of the control layer), so that the degree of warpage of the final structure of the electronic package 2 can be adjusted. For example, it is easy to convert a 12-inch wafer (12 "Wafer) is controlled within the allowable range (such as +/- 3.5mm).

Furthermore, when the number of the first electronic components 21 and the second electronic components 22 connected to the first side 20a and the second side 20b of the carrying structure 20 is different, and the first electronic components 21 and the second electronic components are different When the size of 22 is also different, the shape of the reinforcing member 23 and the amount of the regulating layer 26 are adjusted to prevent the electronic package 2 from appearing asymmetric and warping, so the electronic package 2 Can be effectively set on circuit boards (such as flexible board substrates) of end products (such as mobile phones).

The present invention also provides an electronic package 2 including: a carrier structure 20, at least a first electronic component 21, a packaging layer 25, at least a second electronic component 22, a control layer 26, and a reinforcing member 23.

The supporting structure 20 has a first side 20 a and a second side 20 b opposite to each other, and a circuit layer 200.

The first electronic component 21 is coupled to the first side 20 a of the supporting structure 20 and is electrically connected to the circuit layer 200.

The packaging layer 25 is formed on the first side 20 a of the supporting structure 20 to cover the first electronic component 21.

The second electronic component 22 is disposed on the second side 20 b of the supporting structure 20 and is electrically connected to the circuit layer 200.

The regulating layer 26 is an insulating material, which is formed on the second side 20 b of the supporting structure 20 to cover the second electronic component 22.

The reinforcing member 23 is formed on the control layer 26, and the reinforcing member is made of a material having a thermal expansion coefficient of less than 20.

In one embodiment, a part of the surface (non-active surface 21 b) of the first electronic component 21 is exposed to the outer surface 25 b of the packaging layer 25.

In one embodiment, the thickness h2 of the encapsulation layer 25 is equal to the sum of the thickness d of the reinforcing member 23 and the thickness t of the control layer (h2 = d + t).

In one embodiment, the electronic package 2 includes a plurality of conductive elements 27 formed on the packaging layer 25 and extending to the first side 20 a of the carrier structure 20 to electrically connect the circuit layer 200.

In summary, the electronic package and its manufacturing method of the present invention are controlled by the design of the reinforcing member and the regulating layer, and by adjusting the thickness and volume of the reinforcing member and the thickness and volume of the regulating layer. The degree of warpage of the final structure of the electronic package.

The above embodiments are used to exemplify the principle of the present invention and its effects, but not to limit the present invention. Anyone skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application described later.

Claims (14)

An electronic package includes: a supporting structure having first and second sides opposite to each other; a first electronic component provided on the first side of the supporting structure; and a packaging layer covering the first electronic component Components; a second electronic component provided on the second side of the load-bearing structure; a control layer covering the second electronic component; and a reinforcing member provided on the control layer. The electronic package according to item 1 of the scope of patent application, wherein a part of the surface of the first electronic component is exposed to the packaging layer. The electronic package according to item 1 of the scope of patent application, wherein the reinforcing member is made of a material having a thermal expansion coefficient of less than 20. The electronic package according to item 1 of the scope of patent application, wherein the control layer is an insulating material. The electronic package according to item 1 of the scope of the patent application, wherein the thickness of the packaging layer is equal to the sum of the thickness of the reinforcing member and the thickness of the control layer. The electronic package described in item 1 of the scope of the patent application, which includes a plurality of conductive elements, is formed on the packaging layer and extends to the first side of the carrier structure to electrically connect the carrier structure. A method for manufacturing an electronic package includes: providing a package structure and a reinforcing member including a control layer, wherein the package structure includes a bearing structure with opposite first and second sides, and is provided in the package. A first electronic component on a first side, covering the first electric component A packaging layer of the sub-component and a second electronic component provided on the second side; and the reinforcing member is provided on the second side of the bearing structure, and the control layer covers the second electronic component. According to the method for manufacturing an electronic package described in item 7 of the scope of patent application, wherein a part of the surface of the first electronic component exposes the packaging layer. According to the method for manufacturing an electronic package described in item 7 of the scope of patent application, wherein the reinforcing member is made of a material having a thermal expansion coefficient of less than 20. According to the method for manufacturing an electronic package described in item 7 of the scope of patent application, wherein the control layer is an insulating material. According to the method for manufacturing an electronic package described in item 7 of the scope of the patent application, wherein the thickness of the packaging layer is equal to the sum of the thickness of the reinforcing member and the thickness of the control layer. According to the manufacturing method of the electronic package described in item 7 of the scope of the patent application, the method further includes forming a plurality of conductive elements on the packaging layer, and the conductive elements extend to the first side of the carrying structure to electrically connect the carrying structure. According to the manufacturing method of the electronic package described in item 7 of the scope of patent application, the method further includes forming a stress portion on the second side of the load-bearing structure before the reinforcement member is provided on the second side of the load-bearing structure. According to the manufacturing method of the electronic package described in item 13 of the scope of the patent application, wherein the stress portion is located on the cutting path of the singulation process.