TWI389296B - Stackable package and method for making the same and semiconductor package - Google Patents

Description

Stackable package structure, manufacturing method thereof and semiconductor package structure

The present invention relates to a package structure and a method of fabricating the same, and more particularly to a stackable package structure having a lead frame, a method of fabricating the same, and a stacked semiconductor package structure.

Referring to Figure 1, a cross-sectional view of a first stackable package structure is shown. The first stackable package structure 1 includes a substrate 11, a wafer 12, a plurality of wires 13, a gel 14 and a plurality of solder balls 15. The substrate 11 includes a first surface 111 , a second surface 112 , a plurality of through holes 113 , and a plurality of electrical connection points 114 . The through holes 113 extend through the substrate 11 , and the electrical connection points 114 are located at the periphery of the first surface 111 of the substrate 11 and are exposed on the first surface 111 . The wafer 12 is located on the first surface 111 of the substrate 11. The wires 13 are electrically connected to the substrate 11 and the wafer 12. The encapsulant 14 covers a portion of the substrate 11, the wafer 12, and the wires 13. The solder balls 15 are located on the second surface 112 of the substrate 11.

The disadvantages of the first stackable package structure 1 are as follows. The electrical connection points 114 are located on the periphery of the first surface 111 of the substrate 11, so that the distribution of the electrical connection points 114 does not conform to the distribution of the solder balls of a standard memory, and the stack cannot be stacked. A standard memory is at the top of the conventional first stackable package structure 1.

Referring to Figure 2, a cross-sectional view of a conventional second stackable package structure is shown. The second stackable package structure 2 includes a first substrate 21, a first wafer 22, a primer 23, a dielectric layer 24, a second substrate 25, a plurality of wires 26, and a gel. 27 and a plurality of solder balls 28. The first substrate 21 has a first surface 211 and a second surface 212. The first wafer 22 is located on the first substrate 21 and includes a plurality of first bumps 221 . The primer 23 covers the first bumps 221 of the first wafer 22 . The dielectric layer 24 is on the first wafer 22. The second substrate 25 is disposed on the dielectric layer 24 and includes a first surface 251 , a second surface 252 , and a plurality of electrical connection points 253 . The first surface 251 contacts the dielectric layer 24 . Electrical connection points 253 are located on the second surface 252. The wires 26 are electrically connected to the second substrate 25 and the first substrate 21. The encapsulant 27 covers the first surface 211 of the first substrate 21, the first wafer 22, the dielectric layer 24, the first surface 251 of the second substrate 25, and the wires 26, and the first surface is exposed. The electrical connection point 253 of the two substrates 25 is obtained. The solder balls 28 are located on the second surface 212 of the first substrate 21.

The disadvantages of the conventional second stackable package structure 2 are as follows. Although the stackable package structure 2 can be stacked by a standard memory, an additional dielectric layer 24 is disposed between the first wafer 22 and the second substrate 25 to make the stackable. The thickness of the package structure 2 is increased and the cost is increased.

Therefore, it is necessary to provide a stackable package structure, a method of fabricating the same, and a semiconductor package structure to solve the above problems.

The invention provides a stackable package structure comprising a substrate, a wafer, a lead frame and a gel. The substrate has an upper surface, a lower surface and at least one first bonding pad, the first bonding pad being located on the upper surface. The wafer is located on an upper surface of the substrate and is electrically connected to the substrate. The lead frame is attached to the upper surface of the substrate. The lead frame includes a plurality of pins and a plurality of electrical connection points. The pins are connected to the electrical connection points, and each of the pins includes a first portion and a first portion. a second portion and an intermediate portion, the first portion is electrically connected to the first bonding pad, the second portion is connected to the electrical connection point, the intermediate portion is connected to the first portion and the second portion, and the second portion is The intermediate portion defines an accommodating space for accommodating the wafer. The encapsulant covers the upper surface of the substrate, the wafer and the lead frame, and exposes the electrical connection points.

The invention further provides a stackable package structure comprising a gel body, a lead frame, a wafer and a substrate. The sealing body has a bonding surface, the bonding surface exposing a plurality of electrical connection points, the electrical connection points comprising a plurality of first electrical connection points and a plurality of second electrical connection points, and the first electrical The sexual connection points are located at the periphery of the second electrical connection points. The lead frame is located in the seal body, the lead frame includes a plurality of pins and the electrical connection points, each of the pins includes a first portion, a second portion and an intermediate portion, the second portion is connected to the lead portion An electrical connection point, the middle portion is connected to the first portion and the second portion, the second portion and the intermediate portion define an accommodating space, and the pins comprise a plurality of first pins and a plurality of second portions Pins, the first pins are connected to the first electrical connection points, the second pins are connected to the second electrical connection points, and each of the second pins is passed through two adjacent ones A gap between electrical connections. The wafer is located in the accommodating space. The substrate has a first surface, a second surface, and at least one first pad. The first pad is located on the first surface, and the first surface of the substrate is used to carry the wafer, the lead frame and the The sealing body is electrically connected to the substrate, and the first pad of the substrate is electrically connected to the electrical connection points through the first portion of the pins.

The present invention further provides a method for fabricating a stackable package structure, comprising the steps of: (a) providing a substrate having an upper surface, a lower surface, and at least one first bonding pad, the first bonding pad being located The upper surface; (b) a wafer is disposed on the upper surface of the substrate, the wafer is electrically connected to the substrate; (c) a lead frame is provided, the lead frame includes a plurality of pins and a plurality of electrical connection points The pins are connected to the electrical connection points, each of the pins includes a first portion, a second portion and an intermediate portion, the second portion is connected to the electrical connection point, and the intermediate portion is connected to the first portion And the second portion, the second portion and the intermediate portion define an accommodating space for accommodating the wafer; (d) attaching the lead frame to the upper surface of the substrate, so that the first portion of each pin is electrically Connecting the first bonding pad, and the wafer is located in the accommodating space; and (e) forming a gel to cover the upper surface of the substrate, the wafer and the lead frame, and exposing the electrical connection points.

The present invention further provides a semiconductor package structure including a stackable package structure and at least one upper package structure. The stackable package structure includes a substrate, a wafer, a lead frame and a gel. The substrate has an upper surface, a lower surface and at least one first bonding pad, the first bonding pad being located on the upper surface. The wafer is located on an upper surface of the substrate and is electrically connected to the substrate. The lead frame is attached to the upper surface of the substrate. The lead frame includes a plurality of pins and a plurality of electrical connection points. The pins are connected to the electrical connection points, and each of the pins includes a first portion and a first portion. a second portion and an intermediate portion, the first portion is electrically connected to the first bonding pad, the second portion is connected to the electrical connection point, the intermediate portion is connected to the first portion and the second portion, and the second portion is The intermediate portion defines an accommodating space for accommodating the wafer. The encapsulant covers the upper surface of the substrate, the wafer and the lead frame, and exposes the electrical connection points. The upper package structure is located on the stackable package structure and electrically connected to the stackable package structure.

Thereby, the lead frame allows the distribution of the electrical connection points to conform to the distribution of solder balls of a standard memory, and the standard memory is stacked on top of the stackable package structure of the present invention. Moreover, the leadframe avoids the use of additional dielectric layers and reduces the overall thickness of the stackable package structure of the present invention. Moreover, the lead frame provides a high line-dense bonding surface on the upper surface of the encapsulant for stacking the package structure in any of the aspects. In addition, by using a standard square mold to form the sealant, the electrical connection points can be revealed without the need to develop a mold of a special shape, thereby reducing manufacturing costs.

Referring to Figures 3 through 11, there are shown schematic views of a method of fabricating a first embodiment of the stackable package structure of the present invention. Referring to FIG. 3, a substrate 31 is provided. The substrate 31 has an upper surface 311 (ie, a first surface), a lower surface 312 (ie, a second surface), at least one first bonding pad 313, and a plurality of second bonding pads 314. The first pad 313 and the second pads 314 are located on the upper surface 311 (ie, the first surface). Referring to FIG. 4, at least one solder (Solder Paste) 32 is disposed on the first pad 313 of the substrate 31. Preferably, the solder 32 is disposed on the first pad 313 of the substrate 31 by using a Dipping Solder Paste or a printing process.

Referring to FIG. 5, a wafer is disposed on the upper surface 311 (ie, the first surface) of the substrate 31, and the wafer is electrically connected to the substrate 31. In the present embodiment, the wafer is a wire wafer 33 that is electrically connected to the second pad 314 of the substrate 31 through a plurality of wires 331 and attached to the substrate 31 by an adhesive layer 332. . However, in other applications, referring to FIG. 6, the wafer system can be a flip chip 34 including an upper surface 341 (ie, a back surface), a lower surface 342 (ie, an active surface), and a plurality of bumps 343. The bump 343 is located on the lower surface 342 (ie, the active surface), and the flip chip 34 is electrically connected to the second pad 314 of the substrate 31 through the bumps 343 .

Referring to FIGS. 7-9, a lead frame 35 is provided. The lead frame 35 includes a plurality of pins 351, a plurality of electrical connection points 352, and a bezel 354. In this embodiment, the electrical connection point 352 includes a plurality of first electrical connection points 352A and a plurality of second electrical connection points 352B. However, in other embodiments, the electrical connection points 352 are further The at least one third electrical connection point 352C (FIG. 15) is included, wherein the first electrical connection points 352A and the second electrical connection points 352B are directly above the wire bonding die 33, and the at least one third The electrical connection points 352C are located at opposite positions outside the wire bonding die 33.

The pins 351 are connected to the electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C). Each of the leads 351 includes a first portion 3511, a second portion 3512, and a middle portion 3513. The second portion 3512 is connected to the electrical connection point 352 (the first electrical connection point 352A and the second electrical connection point). 352B and a third electrical connection point 352C), the intermediate portion 3513 connects the first portion 3511 and the second portion 3512. Preferably, the lead frame 35 is made of copper. In this embodiment, the first portion 3511 is parallel to the second portion 3512 and has a height difference, and the intermediate portion 3513 has an angle with the first portion 3511 and the second portion 3512, respectively. The foot 351 has two bends, and the second portion 3512 and the intermediate portion 3513 define an accommodation space 353. In this embodiment, there is a spacing between each two adjacent electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C), and each An electrical connection point 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C) includes a body 3521 and a plating layer 3522. The body 3521 is connected to the pin 351. The second portion 3512, the plating layer 3522 is located on the body 3521, and the material of the plating layer 3522 can be, but not limited to, nickel gold. In this embodiment, the frame 354 is used to connect and fix the pins 351.

Then, preferably, the electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C) are adhered by a tape (not shown) and the tape The second portion 3512 of the pin 351 is fixed to the pins 351 until a colloid 36 (Fig. 10) is formed and then removed. Next, the lead frame 35 is attached to the upper surface 311 of the substrate 31 (ie, the first surface), so that the first portion 3511 of each of the leads 351 is electrically connected to the first pad 313, and the wire bonding die 33 is located at the corresponding surface. Set space 353. In the present embodiment, the lead frame 35 is attached to the upper surface 311 (ie, the first surface) of the substrate 31 through the solder 32 by Surface Mount Technology (SMT).

However, in other embodiments, a spacer wafer 38 (FIG. 16) may be placed on the wire wafer 33, and the lead frame 35 may be attached to the upper surface 311 (ie, the first surface) of the substrate 31 so that The spacer wafer 38 supports the pins 351. Alternatively, a Low Modules Film 39 (FIG. 17) may be formed by using a Dispensing or Printing method to coat the wire wafer 33 and the wires 331, and then attach the lead frame. 35 is on the upper surface 311 of the substrate 31 (ie, the first surface) such that the low-flow film 39 supports the pins 351. Referring to FIG. 10, a glue 36 is formed to cover the upper surface 311 (ie, the first surface) of the substrate 31, the solder 32, the wire wafer 33, and the lead frame 35, and the electrical connection points 352 are exposed ( A plating layer 3522 of the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C). Preferably, the electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B and the third electrical connection point 352C) and the upper surface 361 of the encapsulant 36 (ie, the bonding surface) ) Qi Ping. Preferably, a singulation process is then performed to form a plurality of stackable package structures 3A. The singulation process is a cutting or stamping process to remove the bezel 354 such that the side edges 362 of the encapsulant 36, the sides 3514 of the pins 351, and the sides 315 of the substrate 31 are aligned ( Figure 11). Referring to FIG. 11, a plurality of first solder balls 37 are formed on the lower surface 312 (ie, the second surface) of the substrate 31 while forming the stackable package structure 3 of the present invention.

Referring to FIG. 12, a schematic diagram of the stackable package structure 3 stacked on an upper package structure 4 is shown. In this embodiment, the upper package structure 4 is a ball grid array package (Ball Grid Array Package), which includes a plurality of second solder balls 41, each of which is correspondingly and electrically connected. Each of the electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C) of the lead frame 35 is directly contacted. However, in other applications, the upper package structure 4 is not limited to a ball grid array package structure, and the package structure 3 may also stack more than two upper package structures 7 , and the upper package structures 7 are side by side. As shown in Figure 13.

Referring again to Figure 11, a cross-sectional view of a first embodiment of a stackable package structure of the present invention is shown. The stackable package structure 3 includes a substrate 31, at least one solder (Solder Paste) 32, a wafer, a lead frame 35, a gel 36, and a plurality of first solder balls 37. The substrate 31 has an upper surface 311 , a lower surface 312 , at least one first bonding pad 313 , and a plurality of second bonding pads 314 . The first bonding pads 313 and the second bonding pads 314 are located on the upper surface 311 .

The solder 32 is located on the first pad 313 of the substrate 31. The wafer is located on the upper surface 311 of the substrate 31 and electrically connected to the substrate 31. In the present embodiment, the wafer is a wire wafer 33 that is electrically connected to the second pad 314 of the substrate 31 through a plurality of wires 331 and attached to the substrate 31 by an adhesive layer 332. .

The lead frame 35 is attached to the upper surface 311 of the substrate 31. The lead frame 35 includes a plurality of pins 351 and a plurality of electrical connection points 352. In this embodiment, the electrical connection point 352 includes a plurality of first electrical connection points 352A and a plurality of second electrical connection points 352B. However, in other embodiments, the electrical connection points 352 are further The at least one third electrical connection point 352C (FIG. 15) is included, wherein the first electrical connection points 352A and the second electrical connection points 352B are directly above the wire bonding die 33, and the at least one third The electrical connection points 352C are located at opposite positions outside the wire bonding die 33.

The pins 351 are connected to the electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C), and each pin 351 includes a first portion 3511. a second portion 3512 and a middle portion 3513, the first portion 3511 is electrically connected to the first pad 313 through the solder 32, and the second portion 3512 is connected to the electrical connection point 352 (the first electrical connection point) 352A, a second electrical connection point 352B and a third electrical connection point 352C), the intermediate portion 3513 connects the first portion 3511 and the second portion 3512. Preferably, the lead frame 35 is made of copper. In this embodiment, the first portion 3511 is parallel to the second portion 3512 and has a height difference, and the intermediate portion 3513 has an angle with the first portion 3511 and the second portion 3512, respectively. The leg 351 has two bends, and the second portion 3512 and the intermediate portion 3513 define an accommodating space 353 for accommodating the wire wafer 33. In this embodiment, there is a spacing between each two adjacent electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C), and each An electrical connection point 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C) includes a body 3521 and a plating layer 3522. The body 3521 is connected to the pin 351. The second portion 3512, the plating layer 3522 is located on the body 3521, and the material of the plating layer 3522 can be, but not limited to, nickel gold.

The sealing body 36 covers the upper surface 311 of the substrate 31, the solder 32, the wire bonding die 33 and the lead frame 35, and exposes the electrical connection points 352 (the first electrical connection point 352A, the second electrical property) Connection point 352B and third electrical connection point 352C). Preferably, the electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C) are flush with the upper surface 361 of the encapsulant 36, and The side edges 362 of the encapsulant 36, the side edges 3514 of the pins 351, and the side edges 315 of the substrate 31 are aligned. The first solder balls 37 are located on the lower surface 312 of the substrate 31.

Referring again to Figure 11, a cross-sectional view of a first embodiment of a stackable package structure of the present invention is shown. The stackable package structure 3 includes a glue body 36, a lead frame 35, a wafer, a substrate 31, at least one solder (Solder Paste) 32, and a plurality of first solder balls 37.

The encapsulant 36 has an upper surface 361 (ie, a bonding surface) that exposes a plurality of electrical connection points 352 that include a plurality of first electrical connection points 352A And a plurality of second electrical connection points 352B, and the first electrical connection points 352A are located at the periphery of the second electrical connection points 352B (as shown in FIGS. 8 and 9). That is, the first electrical connection points 352A surround the second electrical connection points 352B. In this embodiment, the first electrical connection points 352A and the second electrical connection points 352B are located directly above the wire bonding die 33. In other embodiments, the electrical connection point 352 further includes at least one third electrical connection point 352C (FIG. 15), and the at least one third electrical connection point 352C is located outside the wire bonding die 33. position.

In this embodiment, there is a spacing between each two adjacent electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C), and each An electrical connection point 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C) includes a body 3521 and a plating layer 3522. The plating layer 3522 is located on the body 3521. The material of the plating layer 3522 may be, but not limited to, nickel gold. Preferably, the first electrical connection points 352A and the second electrical connection points 352B are located in a central region of the upper surface 361 (ie, the bonding surface), and the electrical connection points 352 (first electrical The sexual connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C) are flush with an upper surface 361 (ie, the bonding surface) of the encapsulant 36.

The lead frame 35 is located in the encapsulant 36. Referring to FIG. 8 and FIG. 9 , the lead frame 35 includes a plurality of pins 351 , the first electrical connection points 352A and the second electrical connection points 352B. Each of the leads 351 includes a first portion 3511, a second portion 3512, and a middle portion 3513. The second portion 3512 is connected to the electrical connection point 352 (the first electrical connection point 352A and the second electrical connection point). 352B and a third electrical connection point 352C), the intermediate portion 3513 is connected to the first portion 3511 and the second portion 3512, the second portion 3512 and the intermediate portion 3513 define an accommodating space 353, and the pins The 351 includes a plurality of first pins 351A and a plurality of second pins 351B. The first pins 351A are connected to the first electrical connection points 352A, and the second pins 351B are connected to the second electrical terminals. Connection point 352B.

Preferably, the lead frame 35 is made of copper. In this embodiment, the first portion 3511 is parallel to the second portion 3512 and has a height difference, and the intermediate portion 3513 has an angle with the first portion 3511 and the second portion 3512, respectively. The foot 351 has two bends, and the second portion 3512 and the intermediate portion 3513 define an accommodation space 353. In this embodiment, the second portion 3512 of the pins 351 is connected to the electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C). Body 3521. In addition, each of the second pins 351B passes through a gap between two adjacent first electrical connection points 352A.

The wafer is located in the accommodating space 353. In the present embodiment, the wafer is a wire wafer 33 and is attached to the substrate 31 by an adhesive layer 332. The substrate 31 has an upper surface 311 (ie, a first surface), a lower surface 312 (ie, a second surface), at least one first bonding pad 313, and a plurality of second bonding pads 314, the first bonding pad 313 and the like The second pad 314 is located on the upper surface 311 (ie, the first surface). The upper surface 311 (ie, the first surface) of the substrate 31 carries the wafer, the lead frame 35, and the encapsulant 36. The first pad 313 of the substrate 31 is electrically connected to the first electrical connection point 352 through the solder 32 and the first portion 3511 of the pins 351 (the first electrical connection point 352A and the second electrical connection point 352B). And a third electrical connection point 352C). The second pad 314 of the substrate 31 is electrically connected to the wire bonding die 33 through a plurality of wires 331. Preferably, the side 362 of the encapsulant 36, the side 3514 of the pins 351 and the side 315 of the substrate 31 are aligned. The first solder balls 37 are located on the lower surface 312 (ie, the second surface) of the substrate 31.

Referring to FIG. 12, the stackable package structure 3 further includes at least one upper package structure 4 disposed on an upper surface 361 (ie, a bonding surface) of the sealant 36, and electrically connected to the same. The physical connection point 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C). The upper package structure 4 is a Ball Grid Array Package, which includes a plurality of external contacts (eg, the second solder balls 41), and each external contact (eg, the second solder ball 41) is Correspondingly and electrically connected and directly contacting each electrical connection point 352 of the lead frame 35 (first electrical connection point 352A, second electrical connection point 352B and third electrical connection point 352C). However, in other applications, the upper package structure 4 is not limited to a ball grid array package structure, and the package structure 3 may also stack more than two upper package structures 7 , and the upper package structures 7 are side by side. As shown in Figure 13.

Referring again to Figure 12, a cross-sectional view of a semiconductor package structure of the present invention is shown. The semiconductor package structure 6 includes a stackable package structure and at least one upper package structure 4. The stackable package structure is the same as the first embodiment of the stackable package structure 3 of the present invention. The upper package structure 4 is located on the stackable package structure 3 and electrically connected to the stackable package structure 3.

Referring to Figure 14, a cross-sectional view of a second embodiment of the stackable package structure of the present invention is shown. The stackable package structure 5 of the present embodiment is substantially the same as the stackable package structure 3 (FIG. 11) of the first embodiment, wherein the same components are given the same reference numerals. The difference between this embodiment and the first embodiment is that the structure of the wafer is different. In this embodiment, the wafer is a flip chip 34 including an upper surface 341 (ie, a back surface), a lower surface 342 (ie, an active surface), and a plurality of bumps 343. The lower surface 342 (ie, the active surface), and the flip chip 34 is electrically connected to the second pad 314 of the substrate 31 through the bumps 343.

Referring to Figure 15, a cross-sectional view of a third embodiment of the stackable package structure of the present invention is shown. The stackable package structure 8 of the present embodiment is substantially the same as the stackable package structure 3 (FIG. 11) of the first embodiment, wherein the same components are given the same reference numerals. The difference between the present embodiment and the first embodiment is that the electrical connection point 352 of the package structure 8 further includes at least one third electrical connection point 352C, and the at least one third electrical connection point 352C is located on the wire bonding die 33. Relative position outside.

Referring to Figure 16, there is shown a cross-sectional view of a fourth embodiment of the stackable package structure of the present invention. The stackable package structure 9 of the present embodiment is substantially the same as the stackable package structure 3 (FIG. 11) of the first embodiment, wherein the same components are given the same reference numerals. The difference between this embodiment and the first embodiment is that the package structure 9 further includes a spacer wafer 38 on the wire bonding die 33 for supporting the pins 351.

Referring to Figure 17, there is shown a cross-sectional view of a fifth embodiment of the stackable package structure of the present invention. The stackable package structure 10 of the present embodiment is substantially the same as the stackable package structure 3 (FIG. 11) of the first embodiment, wherein the same components are given the same reference numerals. The difference between this embodiment and the first embodiment is that the package structure 10 further includes a Low Modules Film 39 which covers the wire wafer 33 for supporting the pins 351.

Thereby, the lead frame 35 allows the distribution of the electrical connection points 352 to conform to the distribution of the solder balls of a standard memory, and the standard memory is stacked in the stackable package structure 3, 5 of the present invention. The top. Moreover, the leadframe 35 avoids the use of additional dielectric layers 24 (Fig. 2) while reducing the overall thickness of the stackable package structures 3, 5 of the present invention. Moreover, the lead frame 35 provides a high line-dense bonding surface on the upper surface 361 of the encapsulant 36 for stacking the package structure 4 in any of the aspects. In addition, by using a standard square mold to form the sealant 36, the electrical connection points 352 can be revealed without the need to develop a specially shaped mold, thereby reducing manufacturing costs.

However, the above embodiments are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims.

1. . . The first stackable package structure

2. . . The second stackable package structure

3. . . First embodiment of the stackable package structure of the present invention

3A. . . Stackable package structure

4. . . Upper package structure

5. . . Second embodiment of the stackable package structure of the present invention

6. . . Semiconductor package structure of the invention

7. . . Upper package structure

8. . . Third embodiment of the stackable package structure of the present invention

9. . . Fourth embodiment of the stackable package structure of the present invention

10. . . Fifth embodiment of the stackable package structure of the present invention

11. . . Substrate

12. . . Wafer

13. . . wire

14. . . Sealant

15. . . Solder ball

twenty one. . . First substrate

twenty two. . . First wafer

twenty three. . . Primer

twenty four. . . Dielectric layer

25. . . Second substrate

26. . . wire

27. . . Sealant

28. . . Solder ball

31. . . Substrate

32. . . solder

33. . . Wire wafer

34. . . Flip chip

35. . . Lead frame

36. . . Sealant

37. . . First solder ball

38. . . Separate wafer

39. . . Low mold flow film

41. . . Second solder ball

111. . . First surface

112. . . Second surface

113. . . Through hole

114. . . Electrical connection point

211. . . First surface

212. . . Second surface

221. . . First bump

251. . . First surface

252. . . Second surface

253. . . Electrical connection point

311. . . Upper surface

312. . . lower surface

313. . . First pad

314. . . Second pad

315. . . Side

331. . . wire

332. . . Adhesive layer

341. . . Upper surface

342. . . lower surface

343. . . Bump

351. . . Pin

351A. . . First pin

351B. . . Second pin

352. . . Electrical connection point

352A. . . First electrical connection point

352B. . . Second electrical connection point

352C. . . Third electrical connection point

353. . . Housing space

354. . . frame

361. . . Upper surface

362. . . Side

3511. . . first part

3512. . . the second part

3513. . . Middle part

3514. . . Side

3521. . . Ontology

3522. . . Plating

1 shows a schematic cross-sectional view showing a conventional first stackable package structure;

2 is a cross-sectional view showing a conventional second stackable package structure;

3 to 11 are schematic views showing a manufacturing method of a first embodiment of the stackable package structure of the present invention;

12 is a schematic view showing a stacked package structure of a first embodiment of the stackable package structure of the present invention;

13 is a schematic view showing the stacking of two upper package structures in the first embodiment of the stackable package structure of the present invention;

Figure 14 is a cross-sectional view showing a second embodiment of the stackable package structure of the present invention;

Figure 15 is a cross-sectional view showing a third embodiment of the stackable package structure of the present invention;

Figure 16 is a cross-sectional view showing a fourth embodiment of the stackable package structure of the present invention;

Figure 17 is a cross-sectional view showing a fifth embodiment of the stackable package structure of the present invention.

3. . . First embodiment of the stackable package structure of the present invention

31. . . Substrate

32. . . solder

33. . . Wire wafer

35. . . Lead frame

36. . . Sealant

37. . . First solder ball

311. . . Upper surface

312. . . lower surface

313. . . First pad

314. . . Second pad

315. . . Side

331. . . wire

332. . . Adhesive layer

351. . . Pin

351A. . . First pin

352. . . Electrical connection point

352A. . . First electrical connection point

352B. . . Second electrical connection point

353. . . Housing space

361. . . Upper surface

362. . . Side

3511. . . first part

3512. . . the second part

3513. . . Middle part

3514. . . Side

3521. . . Ontology

3522. . . Plating

Claims (58)

A stackable package structure comprising: a substrate having an upper surface, a lower surface, and at least one first bonding pad, the first bonding pad being located on the upper surface; a wafer on the upper surface of the substrate, and electrically Connected to the substrate; a lead frame attached to the upper surface of the substrate, the lead frame includes a plurality of pins and a plurality of electrical connection points, the pins are connected to the electrical connection points, each pin The first portion is electrically connected to the first bonding pad, the second portion is connected to the electrical connection point, and the intermediate portion is connected to the first portion and the second portion a portion, the second portion and the intermediate portion define an accommodating space for accommodating the wafer; and a gel covering the upper surface of the substrate, the wafer and the lead frame, and exposing the electrical connection points . The package structure of claim 1, wherein the substrate further comprises a plurality of second pads, the second pads being located on the upper surface. The package structure of claim 2, wherein the wafer includes an active surface, a back surface, and a plurality of bumps, the bumps are located on the active surface, and the wafer is electrically connected to the substrate through the bumps The second pads. The package structure of claim 2, wherein the wafer is electrically connected to the second pads of the substrate through a plurality of wires, and the wafer is attached to the substrate by an adhesive layer. The package structure of claim 1, wherein each two adjacent electrical connection points There is a gap between them. The package structure of claim 1, wherein each of the electrical connection points comprises a body and a plating layer, the body is connected to the second portion of the pin, and the plating layer is located on the body. The package structure of claim 6, wherein the material of the plating layer is nickel gold. The package structure of claim 1, wherein the electrical connection points comprise a plurality of first electrical connection points and a plurality of second electrical connection points, the first electrical connection points and the second electrical connections The dot system is located directly above the wafer. The package structure of claim 8, wherein the electrical connection points further comprise at least one third electrical connection point, the at least one third electrical connection point being located The relative position outside the wafer. Such as the package structure of claim 1, The electrical connection points are flush with the upper surface of one of the encapsulants. The package structure of claim 1, wherein the side edges of the encapsulant, the sides of the pins, and the sides of the substrate are aligned. The package structure of claim 1, further comprising at least one solder (Solder Paste) between the first pad of the substrate and the first portion of the pin. The package structure of claim 1, further comprising a plurality of first solder balls on a lower surface of the substrate. The package structure of claim 1 further comprising a spacer wafer on the wafer for supporting the pins. The package structure of claim 1 further includes a low mold flow film (Low) Modules Film), which covers the wafer to support the pins. A method for manufacturing a stackable package structure, comprising: (a) providing a substrate having an upper surface, a lower surface, and at least one first bonding pad, the first bonding pad being located on the upper surface; (b) Providing a wafer on an upper surface of the substrate, the wafer is electrically connected to the substrate; (c) providing a lead frame, the lead frame comprising a plurality of pins and a plurality of electrical connection points, the pins connecting the An isoelectric connection point, each of the pins includes a first portion, a second portion and an intermediate portion, the second portion is connected to the electrical connection point, and the intermediate portion is connected to the first portion and the second portion, The second portion and the intermediate portion define an accommodating space for accommodating the wafer; (d) attaching the lead frame to the upper surface of the substrate, so that the first portion of each pin is electrically connected to the first bonding pad, And the wafer is located in the accommodating space; and (e) forming a gel to cover the upper surface of the substrate, the wafer and the lead frame, and exposing the electrical connection points. The method of claim 16, wherein in the step (a), the substrate further comprises a plurality of second pads located on the upper surface. The method of claim 17, wherein in the step (b), the wafer comprises an active surface, a back surface and a plurality of bumps, the bumps are located on the active surface, and the wafer is electrically transmitted through the bumps The second pads are connected to the substrate. The method of claim 17, wherein in the step (b), the wafer system is transparent A plurality of wires are electrically connected to the second pads of the substrate, and the wafer is attached to the substrate by an adhesive layer. The method of claim 16, wherein the step (b) further comprises the step of providing a separate wafer on the wafer. The method of claim 16, wherein after the step (b), further comprising the step of forming a low mold film to coat the wafer, the low mold film utilizing a spray or printing The (Printing) method is formed. The method of claim 16, wherein the step (c) further comprises the step of providing a tape to adhere the electrical connection points and the second portion of the pins, and after the step (e), further comprising A step of removing the tape. The method of claim 16, wherein in the step (c), there is a spacing between each of the two adjacent electrical connection points. The method of claim 16, wherein in the step (c), each of the electrical connection points comprises a body and a plating layer, the body is connected to the second portion of the pin, and the plating layer is located on the body. The method of claim 24, wherein in the step (c), the material of the plating layer is nickel gold. The method of claim 16, wherein in the step (c), the electrical connection point comprises a plurality of first electrical connection points and a plurality of second electrical connection points, the first electrical connection points and the The second electrical connection point is located directly above the wafer. The method of claim 26, wherein the electrical connection points further comprise at least one third electrical connection point, wherein the at least one third electrical connection point is located in the crystal The relative position of the film. The method of claim 16, wherein in the step (c), the electrical connection point is flush with an upper surface of the encapsulant. The method of claim 16, wherein the step (a) further comprises the step of providing at least one solder on the first pad of the substrate, wherein the lead frame utilizes a surface in the step (d) A surface mount technology (SMT) is attached to the upper surface of the substrate through the solder. The method of claim 29, wherein the solder is disposed on the first pad of the substrate using a Dipping Solder Paste or a printing process. The method of claim 16, wherein the step (e) further comprises the step of performing a singulation process to form a plurality of stackable package structures. The method of claim 31, wherein the singulation process is a cutting or stamping process. The method of claim 32, wherein the sides of the encapsulant, the sides of the pins, and the sides of the substrate are aligned. The method of claim 16, wherein after the step (e), the step of forming a plurality of first solder balls on the lower surface of the substrate is further included. The method of claim 16, wherein after the step (e), the step of stacking at least one upper package structure is further included. The method of claim 35, wherein at least two upper package structures are stacked, the upper package structures being side by side. The method of claim 35, wherein the upper package structure is a ball grid array The package structure (Ball Grid Array Package). The method of claim 35, wherein the upper package structure comprises a plurality of second solder balls, each of the second solder balls corresponding to and electrically connected to each electrical connection point of the lead frame. The method of claim 38, wherein each of the second solder balls is in direct contact with each electrical connection point of the lead frame. A semiconductor package structure comprising: a stackable package structure, comprising: a substrate having an upper surface, a lower surface, and at least one first bonding pad, the first bonding pad being located on the upper surface; a wafer located at the An upper surface of the substrate and electrically connected to the substrate; a lead frame attached to the upper surface of the substrate, the lead frame comprising a plurality of pins and a plurality of electrical connection points, the pins connecting the electrical properties a connecting point, each of the pins includes a first portion, a second portion and an intermediate portion, the first portion is electrically connected to the first bonding pad, and the second portion is connected to the electrical connection point, the intermediate portion is connected The first portion and the second portion, the second portion and the intermediate portion define an accommodating space for accommodating the wafer; and a gel covering the upper surface of the substrate, the wafer and the lead frame, and And exposing the electrical connection points; and at least one upper package structure on the stackable package structure and electrically connected to the stackable package structure. The package structure of claim 40, wherein the substrate further comprises a plurality of second Solder pads, the second pads are located on the upper surface. The package structure of claim 41, wherein the wafer includes an active surface, a back surface, and a plurality of bumps, the bumps are located on the active surface, and the wafer is electrically connected to the substrate through the bumps The second pads. The package structure of claim 41, wherein the wafer is electrically connected to the second pads of the substrate through a plurality of wires, and the wafer is attached to the substrate by an adhesive layer. The package structure of claim 40, wherein each of the two adjacent electrical connection points has a spacing therebetween. The package structure of claim 40, wherein each of the electrical connection points comprises a body and a plating layer, the body is connected to the second portion of the pin, and the plating layer is located on the body. The package structure of claim 45, wherein the material of the plating layer is nickel gold. The package structure of claim 40, wherein the electrical connection points comprise a plurality of first electrical connection points and a plurality of second electrical connection points, the first electrical connection points and the second electrical connections The dot system is located directly above the wafer. The package structure of claim 47, wherein the electrical connection points further comprise at least one third electrical connection point, the at least one third electrical connection point being located at a relative position outside the wafer. The package structure of claim 40, wherein the electrical connection points are flush with an upper surface of the encapsulant. The package structure of claim 40, wherein the side of the sealant, the lead The sides of the foot are aligned with the sides of the substrate. The package structure of claim 40, wherein the stackable package structure further comprises at least one solder (Solder Paste) between the first pad of the substrate and the first portion of the pin. The package structure of claim 40, wherein the stackable package structure further comprises a plurality of first solder balls on a lower surface of the substrate. The package structure of claim 40, wherein the stackable package structure further comprises a spacer wafer on the wafer for supporting the pins. The package structure of claim 40, wherein the stackable package structure further comprises a Low Modules Film that encapsulates the wafer to support the pins. The package structure of claim 40 includes at least two upper package structures, which are side by side. The package structure of claim 40, wherein the upper package structure is a Ball Grid Array Package. The package structure of claim 40, wherein the upper package structure comprises a plurality of second solder balls, each of the second solder balls corresponding to and electrically connected to each electrical connection point of the lead frame. The package structure of claim 57, wherein each of the second solder balls directly contacts each of the electrical connection points of the lead frame.