TWI389296B - Stackable package and method for making the same and semiconductor package - Google Patents

Stackable package and method for making the same and semiconductor package Download PDF

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Publication number
TWI389296B
TWI389296B TW98121299A TW98121299A TWI389296B TW I389296 B TWI389296 B TW I389296B TW 98121299 A TW98121299 A TW 98121299A TW 98121299 A TW98121299 A TW 98121299A TW I389296 B TWI389296 B TW I389296B
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electrical connection
package structure
substrate
wafer
connection points
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TW98121299A
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TW201101458A (en
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Chi Chih Chu
Cheng Yi Weng
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Advanced Semiconductor Eng
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Description

可堆疊式封裝結構及其製造方法及半導體封裝結構Stackable package structure, manufacturing method thereof and semiconductor package structure

本發明係關於一種封裝結構及其製造方法，詳言之，係關於一種具有導線架之可堆疊式封裝結構及其製造方法及堆疊後之半導體封裝結構。The present invention relates to a package structure and a method of fabricating the same, and more particularly to a stackable package structure having a lead frame, a method of fabricating the same, and a stacked semiconductor package structure.

參考圖1，顯示習知第一種可堆疊式封裝結構之剖面示意圖。該習知第一種可堆疊式封裝結構1包括一基板11、一晶片12、複數條導線13、一封膠體14及複數個銲球15。該基板11包括一第一表面111、一第二表面112、複數個穿導孔113及複數個電性連接點114。該等穿導孔113係貫穿該基板11，該等電性連接點114係位於該基板11之第一表面111之外圍，且顯露於該第一表面111。該晶片12位於該基板11之第一表面111。該等導線13係電性連接該基板11及該晶片12。該封膠體14係包覆部分該基板11、該晶片12及該等導線13。該等銲球15係位於該基板11之第二表面112。Referring to Figure 1, a cross-sectional view of a first stackable package structure is shown. The first stackable package structure 1 includes a substrate 11, a wafer 12, a plurality of wires 13, a gel 14 and a plurality of solder balls 15. The substrate 11 includes a first surface 111 , a second surface 112 , a plurality of through holes 113 , and a plurality of electrical connection points 114 . The through holes 113 extend through the substrate 11 , and the electrical connection points 114 are located at the periphery of the first surface 111 of the substrate 11 and are exposed on the first surface 111 . The wafer 12 is located on the first surface 111 of the substrate 11. The wires 13 are electrically connected to the substrate 11 and the wafer 12. The encapsulant 14 covers a portion of the substrate 11, the wafer 12, and the wires 13. The solder balls 15 are located on the second surface 112 of the substrate 11.

該習知第一種可堆疊式封裝結構1之缺點如下。該等電性連接點114係位於該基板11之第一表面111之外圍，使得該等電性連接點114之分佈不符合一標準記憶體(Standard Memory)之銲球之分佈，而無法堆疊該標準記憶體(Standard Memory)於該習知第一種可堆疊式封裝結構1之頂端。The disadvantages of the first stackable package structure 1 are as follows. The electrical connection points 114 are located on the periphery of the first surface 111 of the substrate 11, so that the distribution of the electrical connection points 114 does not conform to the distribution of the solder balls of a standard memory, and the stack cannot be stacked. A standard memory is at the top of the conventional first stackable package structure 1.

參考圖2，顯示習知第二種可堆疊式封裝結構之剖面示意圖。該習知第二種可堆疊式封裝結構2包括一第一基板21、一第一晶片22、一底膠23、一介電層24、一第二基板25、複數條導線26、一封膠體27及複數個銲球28。該第一基板21具有一第一表面211及一第二表面212。該第一晶片22位於該第一基板21上，且包括複數個第一凸塊221。該底膠23係包覆該第一晶片22之該等第一凸塊221。該介電層24係位於該第一晶片22上。該第二基板25係位於該介電層24上，且包括第一表面251、一第二表面252及複數個電性連接點253，該第一表面251係接觸該介電層24，該等電性連接點253係位於該第二表面252。該等導線26係電性連接該第二基板25及該第一基板21。該封膠體27係包覆該第一基板21之第一表面211、該第一晶片22、該介電層24、該第二基板25之第一表面251及該等導線26，且顯露該第二基板25之電性連接點253。該等銲球28係位於該第一基板21之第二表面212。Referring to Figure 2, a cross-sectional view of a conventional second stackable package structure is shown. The second stackable package structure 2 includes a first substrate 21, a first wafer 22, a primer 23, a dielectric layer 24, a second substrate 25, a plurality of wires 26, and a gel. 27 and a plurality of solder balls 28. The first substrate 21 has a first surface 211 and a second surface 212. The first wafer 22 is located on the first substrate 21 and includes a plurality of first bumps 221 . The primer 23 covers the first bumps 221 of the first wafer 22 . The dielectric layer 24 is on the first wafer 22. The second substrate 25 is disposed on the dielectric layer 24 and includes a first surface 251 , a second surface 252 , and a plurality of electrical connection points 253 . The first surface 251 contacts the dielectric layer 24 . Electrical connection points 253 are located on the second surface 252. The wires 26 are electrically connected to the second substrate 25 and the first substrate 21. The encapsulant 27 covers the first surface 211 of the first substrate 21, the first wafer 22, the dielectric layer 24, the first surface 251 of the second substrate 25, and the wires 26, and the first surface is exposed. The electrical connection point 253 of the two substrates 25 is obtained. The solder balls 28 are located on the second surface 212 of the first substrate 21.

該習知第二種可堆疊式封裝結構2之缺點如下。該可堆疊式封裝結構2雖然可供一標準記憶體(Standard Memory)堆疊，但需額外使用一介電層24置於該第一晶片22及該第二基板25之間，而使該可堆疊式封裝結構2之厚度增加，並提高成本。The disadvantages of the conventional second stackable package structure 2 are as follows. Although the stackable package structure 2 can be stacked by a standard memory, an additional dielectric layer 24 is disposed between the first wafer 22 and the second substrate 25 to make the stackable. The thickness of the package structure 2 is increased and the cost is increased.

因此，有必要提供一種可堆疊式封裝結構及其製造方法及半導體封裝結構，以解決上述問題。Therefore, it is necessary to provide a stackable package structure, a method of fabricating the same, and a semiconductor package structure to solve the above problems.

本發明提供一種可堆疊式封裝結構，其包括一基板、一晶片、一導線架及一封膠體。該基板具有一上表面、一下表面及至少一第一銲墊，該第一銲墊係位於該上表面。該晶片位於該基板之上表面，且電性連接至該基板。該導線架附著於該基板之上表面，該導線架包括複數個引腳及複數個電性連接點，該等引腳連接該等電性連接點，每一引腳包括一第一部分、一第二部分及一中間部分，該第一部分係電性連接該第一銲墊，該第二部分係連接該電性連接點，該中間部分連接該第一部分及該第二部分，該第二部分及該中間部分定義出一容置空間以容置該晶片。該封膠體包覆該基板之上表面、該晶片及該導線架，且顯露該等電性連接點。The invention provides a stackable package structure comprising a substrate, a wafer, a lead frame and a gel. The substrate has an upper surface, a lower surface and at least one first bonding pad, the first bonding pad being located on the upper surface. The wafer is located on an upper surface of the substrate and is electrically connected to the substrate. The lead frame is attached to the upper surface of the substrate. The lead frame includes a plurality of pins and a plurality of electrical connection points. The pins are connected to the electrical connection points, and each of the pins includes a first portion and a first portion. a second portion and an intermediate portion, the first portion is electrically connected to the first bonding pad, the second portion is connected to the electrical connection point, the intermediate portion is connected to the first portion and the second portion, and the second portion is The intermediate portion defines an accommodating space for accommodating the wafer. The encapsulant covers the upper surface of the substrate, the wafer and the lead frame, and exposes the electrical connection points.

本發明另提供一種可堆疊式封裝結構，其包括一封膠體、一導線架、一晶片及一基板。該封膠體具有一接合表面，該接合表面顯露複數個電性連接點，該等電性連接點包括複數個第一電性連接點及複數個第二電性連接點，且該等第一電性連接點位於該等第二電性連接點之外圍。該導線架位於該封膠體內，該導線架包括複數個引腳及該等電性連接點，每一引腳包括一第一部分、一第二部分及一中間部分，該第二部分係連接該電性連接點，該中間部分連接該第一部分及該第二部分，該第二部分及該中間部分定義出一容置空間，且該等引腳包括複數個第一引腳及複數個第二引腳，該等第一引腳連接該等第一電性連接點，該等第二引腳連接該等第二電性連接點，每一第二引腳係穿過二個相鄰之第一電性連接點之間隙。該晶片位於該容置空間內。該基板具有一第一表面、一第二表面及至少一第一銲墊，該第一銲墊係位於該第一表面，該基板之第一表面係用以承載該晶片、該導線架及該封膠體，該晶片電性連接至該基板，且該基板之第一銲墊透過該等引腳之第一部分電性連接至該等電性連接點。The invention further provides a stackable package structure comprising a gel body, a lead frame, a wafer and a substrate. The sealing body has a bonding surface, the bonding surface exposing a plurality of electrical connection points, the electrical connection points comprising a plurality of first electrical connection points and a plurality of second electrical connection points, and the first electrical The sexual connection points are located at the periphery of the second electrical connection points. The lead frame is located in the seal body, the lead frame includes a plurality of pins and the electrical connection points, each of the pins includes a first portion, a second portion and an intermediate portion, the second portion is connected to the lead portion An electrical connection point, the middle portion is connected to the first portion and the second portion, the second portion and the intermediate portion define an accommodating space, and the pins comprise a plurality of first pins and a plurality of second portions Pins, the first pins are connected to the first electrical connection points, the second pins are connected to the second electrical connection points, and each of the second pins is passed through two adjacent ones A gap between electrical connections. The wafer is located in the accommodating space. The substrate has a first surface, a second surface, and at least one first pad. The first pad is located on the first surface, and the first surface of the substrate is used to carry the wafer, the lead frame and the The sealing body is electrically connected to the substrate, and the first pad of the substrate is electrically connected to the electrical connection points through the first portion of the pins.

本發明更提供一種可堆疊式封裝結構之製造方法，其包括以下步驟：(a)提供一基板，該基板具有一上表面、一下表面及至少一第一銲墊，該第一銲墊係位於該上表面；(b)設置一晶片於該基板之上表面，該晶片係電性連接至該基板；(c)提供一導線架，該導線架包括複數個引腳及複數個電性連接點，該等引腳連接該等電性連接點，每一引腳包括一第一部分、一第二部分及一中間部分，該第二部分係連接該電性連接點，該中間部分連接該第一部分及該第二部分，該第二部分及該中間部分定義出一容置空間以容置該晶片；(d)附著該導線架於該基板之上表面，使每一引腳之第一部分電性連接該第一銲墊，且該晶片位於該容置空間內；及(e)形成一封膠體，以覆蓋該基板之上表面、該晶片及該導線架，且顯露該等電性連接點。The present invention further provides a method for fabricating a stackable package structure, comprising the steps of: (a) providing a substrate having an upper surface, a lower surface, and at least one first bonding pad, the first bonding pad being located The upper surface; (b) a wafer is disposed on the upper surface of the substrate, the wafer is electrically connected to the substrate; (c) a lead frame is provided, the lead frame includes a plurality of pins and a plurality of electrical connection points The pins are connected to the electrical connection points, each of the pins includes a first portion, a second portion and an intermediate portion, the second portion is connected to the electrical connection point, and the intermediate portion is connected to the first portion And the second portion, the second portion and the intermediate portion define an accommodating space for accommodating the wafer; (d) attaching the lead frame to the upper surface of the substrate, so that the first portion of each pin is electrically Connecting the first bonding pad, and the wafer is located in the accommodating space; and (e) forming a gel to cover the upper surface of the substrate, the wafer and the lead frame, and exposing the electrical connection points.

本發明再提供一種半導體封裝結構，其包括一可堆疊式封裝結構及至少一上封裝結構。該可堆疊式封裝結構包括一基板、一晶片、一導線架及一封膠體。該基板具有一上表面、一下表面及至少一第一銲墊，該第一銲墊係位於該上表面。該晶片位於該基板之上表面，且電性連接至該基板。該導線架附著於該基板之上表面，該導線架包括複數個引腳及複數個電性連接點，該等引腳連接該等電性連接點，每一引腳包括一第一部分、一第二部分及一中間部分，該第一部分係電性連接該第一銲墊，該第二部分係連接該電性連接點，該中間部分連接該第一部分及該第二部分，該第二部分及該中間部分定義出一容置空間以容置該晶片。該封膠體包覆該基板之上表面、該晶片及該導線架，且顯露該等電性連接點。該上封裝結構係位於該可堆疊式封裝結構上，且電性連接至該可堆疊式封裝結構。The present invention further provides a semiconductor package structure including a stackable package structure and at least one upper package structure. The stackable package structure includes a substrate, a wafer, a lead frame and a gel. The substrate has an upper surface, a lower surface and at least one first bonding pad, the first bonding pad being located on the upper surface. The wafer is located on an upper surface of the substrate and is electrically connected to the substrate. The lead frame is attached to the upper surface of the substrate. The lead frame includes a plurality of pins and a plurality of electrical connection points. The pins are connected to the electrical connection points, and each of the pins includes a first portion and a first portion. a second portion and an intermediate portion, the first portion is electrically connected to the first bonding pad, the second portion is connected to the electrical connection point, the intermediate portion is connected to the first portion and the second portion, and the second portion is The intermediate portion defines an accommodating space for accommodating the wafer. The encapsulant covers the upper surface of the substrate, the wafer and the lead frame, and exposes the electrical connection points. The upper package structure is located on the stackable package structure and electrically connected to the stackable package structure.

藉此，該導線架使該等電性連接點之分佈符合一標準記憶體(Standard Memory)之銲球之分佈，而得以堆疊該標準記憶體於本發明可堆疊式封裝結構之頂端。再者，該導線架可避免使用額外之介電層，而減少本發明可堆疊式封裝結構之總厚度。並且，該導線架於該封膠體之上表面提供一高線路密集度之接合表面，以供堆疊任一種態樣之上封裝結構。此外，使用一標準四方形之模具以形成該封膠體，即可顯露該等電性連接點，而不需研發特殊形狀之模具，故可降低製造成本。Thereby, the lead frame allows the distribution of the electrical connection points to conform to the distribution of solder balls of a standard memory, and the standard memory is stacked on top of the stackable package structure of the present invention. Moreover, the leadframe avoids the use of additional dielectric layers and reduces the overall thickness of the stackable package structure of the present invention. Moreover, the lead frame provides a high line-dense bonding surface on the upper surface of the encapsulant for stacking the package structure in any of the aspects. In addition, by using a standard square mold to form the sealant, the electrical connection points can be revealed without the need to develop a mold of a special shape, thereby reducing manufacturing costs.

參考圖3至圖11，顯示本發明可堆疊式封裝結構之第一實施例之製造方法之示意圖。參考圖3，提供一基板31，該基板31具有一上表面311(即第一表面)、一下表面312(即第二表面)、至少一第一銲墊313及複數個第二銲墊314，該第一銲墊313及該等第二銲墊314係位於該上表面311(即第一表面)。參考圖4，設置至少一銲料(Solder Paste)32於該基板31之第一銲墊313上。較佳地，該銲料32係利用沾錫(Dipping Solder Paste)或印刷製程設置於該基板31之第一銲墊313上。Referring to Figures 3 through 11, there are shown schematic views of a method of fabricating a first embodiment of the stackable package structure of the present invention. Referring to FIG. 3, a substrate 31 is provided. The substrate 31 has an upper surface 311 (ie, a first surface), a lower surface 312 (ie, a second surface), at least one first bonding pad 313, and a plurality of second bonding pads 314. The first pad 313 and the second pads 314 are located on the upper surface 311 (ie, the first surface). Referring to FIG. 4, at least one solder (Solder Paste) 32 is disposed on the first pad 313 of the substrate 31. Preferably, the solder 32 is disposed on the first pad 313 of the substrate 31 by using a Dipping Solder Paste or a printing process.

參考圖5，設置一晶片於該基板31之上表面311(即第一表面)，該晶片係電性連接至該基板31。在本實施例中，該晶片係為一打線晶片33，該打線晶片33係透過複數條導線331電性連接至該基板31之第二銲墊314，且利用一黏著層332附著於該基板31。然而，在其他應用中，參考圖6，該晶片係可為一覆晶晶片34，其包括一上表面341(即背面)、一下表面342(即主動面)及複數個凸塊343，該等凸塊343係位於該下表面342(即主動面)，且該覆晶晶片34係透過該等凸塊343電性連接至該基板31之第二銲墊314。Referring to FIG. 5, a wafer is disposed on the upper surface 311 (ie, the first surface) of the substrate 31, and the wafer is electrically connected to the substrate 31. In the present embodiment, the wafer is a wire wafer 33 that is electrically connected to the second pad 314 of the substrate 31 through a plurality of wires 331 and attached to the substrate 31 by an adhesive layer 332. . However, in other applications, referring to FIG. 6, the wafer system can be a flip chip 34 including an upper surface 341 (ie, a back surface), a lower surface 342 (ie, an active surface), and a plurality of bumps 343. The bump 343 is located on the lower surface 342 (ie, the active surface), and the flip chip 34 is electrically connected to the second pad 314 of the substrate 31 through the bumps 343 .

參考圖7至圖9，提供一導線架35，該導線架35包括複數個引腳351、複數個電性連接點352及一邊框354。在本實施例中，該等電性連接點352包括複數個第一電性連接點352A及複數個第二電性連接點352B，然而，在其他實施例中，該等電性連接點352更包括至少一第三電性連接點352C(圖15)，其中該等第一電性連接點352A及該等第二電性連接點352B係位於該打線晶片33之正上方，該至少一第三電性連接點352C係位於該打線晶片33外之相對位置。Referring to FIGS. 7-9, a lead frame 35 is provided. The lead frame 35 includes a plurality of pins 351, a plurality of electrical connection points 352, and a bezel 354. In this embodiment, the electrical connection point 352 includes a plurality of first electrical connection points 352A and a plurality of second electrical connection points 352B. However, in other embodiments, the electrical connection points 352 are further The at least one third electrical connection point 352C (FIG. 15) is included, wherein the first electrical connection points 352A and the second electrical connection points 352B are directly above the wire bonding die 33, and the at least one third The electrical connection points 352C are located at opposite positions outside the wire bonding die 33.

該等引腳351連接該等電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)。每一引腳351包括一第一部分3511、一第二部分3512及一中間部分3513，該第二部分3512係連接該電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)，該中間部分3513連接該第一部分3511及該第二部分3512。較佳地，該導線架35之材質係為銅。在本實施例中，該第一部分3511與該第二部分3512平行，且具有一高度差，而該中間部分3513分別與該第一部分3511及該第二部分3512間具有一夾角，使每一引腳351具有二個彎折處，該第二部分3512及該中間部分3513定義出一容置空間353。在本實施例中，每二個相鄰之電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)之間具有一間距，且每一電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)包括一本體3521及一電鍍層3522，該本體3521連接該引腳351之第二部分3512，該電鍍層3522位於該本體3521上，且該電鍍層3522之材質係可為但不限定於鎳金。在本實施例中，該邊框354係用以連接並固定該等引腳351。The pins 351 are connected to the electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C). Each of the leads 351 includes a first portion 3511, a second portion 3512, and a middle portion 3513. The second portion 3512 is connected to the electrical connection point 352 (the first electrical connection point 352A and the second electrical connection point). 352B and a third electrical connection point 352C), the intermediate portion 3513 connects the first portion 3511 and the second portion 3512. Preferably, the lead frame 35 is made of copper. In this embodiment, the first portion 3511 is parallel to the second portion 3512 and has a height difference, and the intermediate portion 3513 has an angle with the first portion 3511 and the second portion 3512, respectively. The foot 351 has two bends, and the second portion 3512 and the intermediate portion 3513 define an accommodation space 353. In this embodiment, there is a spacing between each two adjacent electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C), and each An electrical connection point 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C) includes a body 3521 and a plating layer 3522. The body 3521 is connected to the pin 351. The second portion 3512, the plating layer 3522 is located on the body 3521, and the material of the plating layer 3522 can be, but not limited to, nickel gold. In this embodiment, the frame 354 is used to connect and fix the pins 351.

接著，較佳地，利用一膠帶(圖中未示)黏著該等電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)及該等引腳351之第二部分3512，以固定該等引腳351，直到形成一封膠體36(圖10)後再予以除移。接著，附著該導線架35於該基板31之上表面311(即第一表面)，使每一引腳351之第一部分3511電性連接該第一銲墊313，且該打線晶片33位於該容置空間353內。在本實施例中，該導線架35係利用表面黏著技術(Surface Mount Technology,SMT)透過該銲料32附著於該基板31之上表面311(即第一表面)。Then, preferably, the electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C) are adhered by a tape (not shown) and the tape The second portion 3512 of the pin 351 is fixed to the pins 351 until a colloid 36 (Fig. 10) is formed and then removed. Next, the lead frame 35 is attached to the upper surface 311 of the substrate 31 (ie, the first surface), so that the first portion 3511 of each of the leads 351 is electrically connected to the first pad 313, and the wire bonding die 33 is located at the corresponding surface. Set space 353. In the present embodiment, the lead frame 35 is attached to the upper surface 311 (ie, the first surface) of the substrate 31 through the solder 32 by Surface Mount Technology (SMT).

然而，在其他實施例中，係可先於該打線晶片33上放置一分隔晶片38(圖16)，再附著該導線架35於該基板31之上表面311(即第一表面)，以使該分隔晶片38支撐該等引腳351。或者，係可先利用噴流(Dispensing)或印刷(Printing)方式形成一低模流薄膜(Low Modules Film)39(圖17)以包覆該打線晶片33及該等導線331，再附著該導線架35於該基板31之上表面311(即第一表面)，以使該低模流薄膜39支撐該等引腳351。參考圖10，形成一封膠體36，以覆蓋該基板31之上表面311(即第一表面)、該銲料32、該打線晶片33及該導線架35，且顯露該等電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)之電鍍層3522。較佳地，該等電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)與該封膠體36之一上表面361(即接合表面)齊平。較佳地，接著進行單體化(Singulation)製程，以形成複數個可堆疊式封裝結構3A。該單體化製程係為切割或衝壓製程，以移除該邊框354，而使該封膠體36之側邊362、該等引腳351之側邊3514及該基板31之側邊315切齊(圖11)。參考圖11，形成複數個第一銲球37於該基板31之下表面312(即第二表面)，同時形成本發明可堆疊式封裝結構3。However, in other embodiments, a spacer wafer 38 (FIG. 16) may be placed on the wire wafer 33, and the lead frame 35 may be attached to the upper surface 311 (ie, the first surface) of the substrate 31 so that The spacer wafer 38 supports the pins 351. Alternatively, a Low Modules Film 39 (FIG. 17) may be formed by using a Dispensing or Printing method to coat the wire wafer 33 and the wires 331, and then attach the lead frame. 35 is on the upper surface 311 of the substrate 31 (ie, the first surface) such that the low-flow film 39 supports the pins 351. Referring to FIG. 10, a glue 36 is formed to cover the upper surface 311 (ie, the first surface) of the substrate 31, the solder 32, the wire wafer 33, and the lead frame 35, and the electrical connection points 352 are exposed ( A plating layer 3522 of the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C). Preferably, the electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B and the third electrical connection point 352C) and the upper surface 361 of the encapsulant 36 (ie, the bonding surface) ) Qi Ping. Preferably, a singulation process is then performed to form a plurality of stackable package structures 3A. The singulation process is a cutting or stamping process to remove the bezel 354 such that the side edges 362 of the encapsulant 36, the sides 3514 of the pins 351, and the sides 315 of the substrate 31 are aligned ( Figure 11). Referring to FIG. 11, a plurality of first solder balls 37 are formed on the lower surface 312 (ie, the second surface) of the substrate 31 while forming the stackable package structure 3 of the present invention.

參考圖12，顯示該可堆疊式封裝結構3堆疊一上封裝結構4之示意圖。在本實施例中，該上封裝結構4係為一球柵陣列封裝結構(Ball Grid Array Package)，其包括複數個第二銲球41，每一第二銲球41係對應且電性連接並直接接觸該導線架35之每一電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)。然而，在其他應用中，該上封裝結構4係不限定為一球柵陣列封裝結構，且該封裝結構3亦可堆疊二個以上之上封裝結構7，該等上封裝結構7係為並排，如圖13所示。Referring to FIG. 12, a schematic diagram of the stackable package structure 3 stacked on an upper package structure 4 is shown. In this embodiment, the upper package structure 4 is a ball grid array package (Ball Grid Array Package), which includes a plurality of second solder balls 41, each of which is correspondingly and electrically connected. Each of the electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C) of the lead frame 35 is directly contacted. However, in other applications, the upper package structure 4 is not limited to a ball grid array package structure, and the package structure 3 may also stack more than two upper package structures 7 , and the upper package structures 7 are side by side. As shown in Figure 13.

再參考圖11，顯示本發明可堆疊式封裝結構之第一實施例之剖面示意圖。該可堆疊式封裝結構3包括一基板31、至少一銲料(Solder Paste)32、一晶片、一導線架35、一封膠體36及複數個第一銲球37。該基板31具有一上表面311、一下表面312、至少一第一銲墊313及複數個第二銲墊314，該第一銲墊313及該等第二銲墊314係位於該上表面311。Referring again to Figure 11, a cross-sectional view of a first embodiment of a stackable package structure of the present invention is shown. The stackable package structure 3 includes a substrate 31, at least one solder (Solder Paste) 32, a wafer, a lead frame 35, a gel 36, and a plurality of first solder balls 37. The substrate 31 has an upper surface 311 , a lower surface 312 , at least one first bonding pad 313 , and a plurality of second bonding pads 314 . The first bonding pads 313 and the second bonding pads 314 are located on the upper surface 311 .

該銲料32位於該基板31之第一銲墊313上。該晶片位於該基板31之上表面311，且電性連接至該基板31。在本實施例中，該晶片係為一打線晶片33，該打線晶片33係透過複數條導線331電性連接至該基板31之第二銲墊314，且利用一黏著層332附著於該基板31。The solder 32 is located on the first pad 313 of the substrate 31. The wafer is located on the upper surface 311 of the substrate 31 and electrically connected to the substrate 31. In the present embodiment, the wafer is a wire wafer 33 that is electrically connected to the second pad 314 of the substrate 31 through a plurality of wires 331 and attached to the substrate 31 by an adhesive layer 332. .

該導線架35附著於該基板31之上表面311，該導線架35包括複數個引腳351及複數個電性連接點352。在本實施例中，該等電性連接點352包括複數個第一電性連接點352A及複數個第二電性連接點352B，然而，在其他實施例中，該等電性連接點352更包括至少一第三電性連接點352C(圖15)，其中該等第一電性連接點352A及該等第二電性連接點352B係位於該打線晶片33之正上方，該至少一第三電性連接點352C係位於該打線晶片33外之相對位置。The lead frame 35 is attached to the upper surface 311 of the substrate 31. The lead frame 35 includes a plurality of pins 351 and a plurality of electrical connection points 352. In this embodiment, the electrical connection point 352 includes a plurality of first electrical connection points 352A and a plurality of second electrical connection points 352B. However, in other embodiments, the electrical connection points 352 are further The at least one third electrical connection point 352C (FIG. 15) is included, wherein the first electrical connection points 352A and the second electrical connection points 352B are directly above the wire bonding die 33, and the at least one third The electrical connection points 352C are located at opposite positions outside the wire bonding die 33.

該等引腳351連接該等電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)，每一引腳351包括一第一部分3511、一第二部分3512及一中間部分3513，該第一部分3511係透過該銲料32電性連接該第一銲墊313，該第二部分3512係連接該電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)，該中間部分3513連接該第一部分3511及該第二部分3512。較佳地，該導線架35之材質係為銅。在本實施例中，該第一部分3511與該第二部分3512平行，且具有一高度差，而該中間部分3513分別與該第一部分3511及該第二部分3512間具有一夾角，使每一引腳351具有二個彎折處，該第二部分3512及該中間部分3513定義出一容置空間353以容置該打線晶片33。在本實施例中，每二個相鄰之電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)之間具有一間距，且每一電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)包括一本體3521及一電鍍層3522，該本體3521連接該引腳351之第二部分3512，該電鍍層3522位於該本體3521上，且該電鍍層3522之材質係可為但不限定於鎳金。The pins 351 are connected to the electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C), and each pin 351 includes a first portion 3511. a second portion 3512 and a middle portion 3513, the first portion 3511 is electrically connected to the first pad 313 through the solder 32, and the second portion 3512 is connected to the electrical connection point 352 (the first electrical connection point) 352A, a second electrical connection point 352B and a third electrical connection point 352C), the intermediate portion 3513 connects the first portion 3511 and the second portion 3512. Preferably, the lead frame 35 is made of copper. In this embodiment, the first portion 3511 is parallel to the second portion 3512 and has a height difference, and the intermediate portion 3513 has an angle with the first portion 3511 and the second portion 3512, respectively. The leg 351 has two bends, and the second portion 3512 and the intermediate portion 3513 define an accommodating space 353 for accommodating the wire wafer 33. In this embodiment, there is a spacing between each two adjacent electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C), and each An electrical connection point 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C) includes a body 3521 and a plating layer 3522. The body 3521 is connected to the pin 351. The second portion 3512, the plating layer 3522 is located on the body 3521, and the material of the plating layer 3522 can be, but not limited to, nickel gold.

該封膠體36包覆該基板31之上表面311、該銲料32、該打線晶片33及該導線架35，且顯露該等電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)。較佳地，該等電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)與該封膠體36之一上表面361齊平，且該封膠體36之側邊362、該等引腳351之側邊3514及該基板31之側邊315切齊。該等第一銲球37位於該基板31之下表面312。The sealing body 36 covers the upper surface 311 of the substrate 31, the solder 32, the wire bonding die 33 and the lead frame 35, and exposes the electrical connection points 352 (the first electrical connection point 352A, the second electrical property) Connection point 352B and third electrical connection point 352C). Preferably, the electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C) are flush with the upper surface 361 of the encapsulant 36, and The side edges 362 of the encapsulant 36, the side edges 3514 of the pins 351, and the side edges 315 of the substrate 31 are aligned. The first solder balls 37 are located on the lower surface 312 of the substrate 31.

又參考圖11，顯示本發明可堆疊式封裝結構之第一實施例之剖面示意圖。該可堆疊式封裝結構3包括一封膠體36、一導線架35、一晶片、一基板31、至少一銲料(Solder Paste)32及複數個第一銲球37。Referring again to Figure 11, a cross-sectional view of a first embodiment of a stackable package structure of the present invention is shown. The stackable package structure 3 includes a glue body 36, a lead frame 35, a wafer, a substrate 31, at least one solder (Solder Paste) 32, and a plurality of first solder balls 37.

該封膠體36具有一上表面361(即接合表面)，該上表面361(即接合表面)顯露複數個電性連接點352，該等電性連接點352包括複數個第一電性連接點352A及複數個第二電性連接點352B，且該等第一電性連接點352A位於該等第二電性連接點352B之外圍(如圖8及圖9所示)。亦即該等第一電性連接點352A包圍該等第二電性連接點352B。在本實施例中，該等第一電性連接點352A及該等第二電性連接點352B係位於該打線晶片33之正上方。然而，在其他實施例中，該等電性連接點352更包括至少一第三電性連接點352C(圖15)，該至少一第三電性連接點352C係位於該打線晶片33外之相對位置。The encapsulant 36 has an upper surface 361 (ie, a bonding surface) that exposes a plurality of electrical connection points 352 that include a plurality of first electrical connection points 352A And a plurality of second electrical connection points 352B, and the first electrical connection points 352A are located at the periphery of the second electrical connection points 352B (as shown in FIGS. 8 and 9). That is, the first electrical connection points 352A surround the second electrical connection points 352B. In this embodiment, the first electrical connection points 352A and the second electrical connection points 352B are located directly above the wire bonding die 33. In other embodiments, the electrical connection point 352 further includes at least one third electrical connection point 352C (FIG. 15), and the at least one third electrical connection point 352C is located outside the wire bonding die 33. position.

在本實施例中，每二個相鄰之電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)之間具有一間距，且每一電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)包括一本體3521及一電鍍層3522，該電鍍層3522位於該本體3521上，且該電鍍層3522之材質係可為但不限定於鎳金。較佳地，該等第一電性連接點352A及該等第二電性連接點352B係位於該上表面361(即接合表面)之中央區域，且該等電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)與該封膠體36之一上表面361(即接合表面)齊平。In this embodiment, there is a spacing between each two adjacent electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C), and each An electrical connection point 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C) includes a body 3521 and a plating layer 3522. The plating layer 3522 is located on the body 3521. The material of the plating layer 3522 may be, but not limited to, nickel gold. Preferably, the first electrical connection points 352A and the second electrical connection points 352B are located in a central region of the upper surface 361 (ie, the bonding surface), and the electrical connection points 352 (first electrical The sexual connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C) are flush with an upper surface 361 (ie, the bonding surface) of the encapsulant 36.

該導線架35位於該封膠體36內，配合參考圖8及圖9，該導線架35包括複數個引腳351、該等第一電性連接點352A及該等第二電性連接點352B，每一引腳351包括一第一部分3511、一第二部分3512及一中間部分3513，該第二部分3512係連接該電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)，該中間部分3513連接該第一部分3511及該第二部分3512，該第二部分3512及該中間部分3513定義出一容置空間353，且該等引腳351包括複數個第一引腳351A及複數個第二引腳351B，該等第一引腳351A連接該等第一電性連接點352A，該等第二引腳351B連接該等第二電性連接點352B。The lead frame 35 is located in the encapsulant 36. Referring to FIG. 8 and FIG. 9 , the lead frame 35 includes a plurality of pins 351 , the first electrical connection points 352A and the second electrical connection points 352B. Each of the leads 351 includes a first portion 3511, a second portion 3512, and a middle portion 3513. The second portion 3512 is connected to the electrical connection point 352 (the first electrical connection point 352A and the second electrical connection point). 352B and a third electrical connection point 352C), the intermediate portion 3513 is connected to the first portion 3511 and the second portion 3512, the second portion 3512 and the intermediate portion 3513 define an accommodating space 353, and the pins The 351 includes a plurality of first pins 351A and a plurality of second pins 351B. The first pins 351A are connected to the first electrical connection points 352A, and the second pins 351B are connected to the second electrical terminals. Connection point 352B.

較佳地，該導線架35之材質係為銅。在本實施例中，該第一部分3511與該第二部分3512平行，且具有一高度差，而該中間部分3513分別與該第一部分3511及該第二部分3512間具有一夾角，使每一引腳351具有二個彎折處，該第二部分3512及該中間部分3513定義出一容置空間353。在本實施例中，該等引腳351之第二部分3512連接該等電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)之本體3521。此外，每一第二引腳351B係穿過二個相鄰之第一電性連接點352A之間隙。Preferably, the lead frame 35 is made of copper. In this embodiment, the first portion 3511 is parallel to the second portion 3512 and has a height difference, and the intermediate portion 3513 has an angle with the first portion 3511 and the second portion 3512, respectively. The foot 351 has two bends, and the second portion 3512 and the intermediate portion 3513 define an accommodation space 353. In this embodiment, the second portion 3512 of the pins 351 is connected to the electrical connection points 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C). Body 3521. In addition, each of the second pins 351B passes through a gap between two adjacent first electrical connection points 352A.

該晶片位於該容置空間353內。在本實施例中，該晶片係為一打線晶片33，且利用一黏著層332附著於該基板31。該基板31具有一上表面311(即第一表面)、一下表面312(即第二表面)、至少一第一銲墊313及複數個第二銲墊314，該第一銲墊313及該等第二銲墊314係位於該上表面311(即第一表面)。該基板31之上表面311(即第一表面)承載該晶片、該導線架35及該封膠體36。該基板31之第一銲墊313透過該銲料32及該等引腳351之第一部分3511電性連接至該等電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)。該基板31之第二銲墊314透過複數條導線331電性連接至該打線晶片33。較佳地，該封膠體36之側邊362、該等引腳351之側邊3514及該基板31之側邊315切齊。該等第一銲球37位於該基板31之下表面312(即第二表面)。The wafer is located in the accommodating space 353. In the present embodiment, the wafer is a wire wafer 33 and is attached to the substrate 31 by an adhesive layer 332. The substrate 31 has an upper surface 311 (ie, a first surface), a lower surface 312 (ie, a second surface), at least one first bonding pad 313, and a plurality of second bonding pads 314, the first bonding pad 313 and the like The second pad 314 is located on the upper surface 311 (ie, the first surface). The upper surface 311 (ie, the first surface) of the substrate 31 carries the wafer, the lead frame 35, and the encapsulant 36. The first pad 313 of the substrate 31 is electrically connected to the first electrical connection point 352 through the solder 32 and the first portion 3511 of the pins 351 (the first electrical connection point 352A and the second electrical connection point 352B). And a third electrical connection point 352C). The second pad 314 of the substrate 31 is electrically connected to the wire bonding die 33 through a plurality of wires 331. Preferably, the side 362 of the encapsulant 36, the side 3514 of the pins 351 and the side 315 of the substrate 31 are aligned. The first solder balls 37 are located on the lower surface 312 (ie, the second surface) of the substrate 31.

再參考圖12，較佳地，該可堆疊式封裝結構3更包括至少一上封裝結構4，其配置於該封膠體36之一上表面361(即接合表面)，且電性連接該等電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)。該上封裝結構4係為一球柵陣列封裝結構(Ball Grid Array Package)，其包括複數個外接點(例如：第二銲球41)，每一外接點(例如：第二銲球41)係對應且電性連接並直接接觸該導線架35之每一電性連接點352(第一電性連接點352A、第二電性連接點352B及第三電性連接點352C)。然而，在其他應用中，該上封裝結構4係不限定為一球柵陣列封裝結構，且該封裝結構3亦可堆疊二個以上之上封裝結構7，該等上封裝結構7係為並排，如圖13所示。Referring to FIG. 12, the stackable package structure 3 further includes at least one upper package structure 4 disposed on an upper surface 361 (ie, a bonding surface) of the sealant 36, and electrically connected to the same. The physical connection point 352 (the first electrical connection point 352A, the second electrical connection point 352B, and the third electrical connection point 352C). The upper package structure 4 is a Ball Grid Array Package, which includes a plurality of external contacts (eg, the second solder balls 41), and each external contact (eg, the second solder ball 41) is Correspondingly and electrically connected and directly contacting each electrical connection point 352 of the lead frame 35 (first electrical connection point 352A, second electrical connection point 352B and third electrical connection point 352C). However, in other applications, the upper package structure 4 is not limited to a ball grid array package structure, and the package structure 3 may also stack more than two upper package structures 7 , and the upper package structures 7 are side by side. As shown in Figure 13.

又參考圖12，顯示本發明半導體封裝結構之剖面示意圖。該半導體封裝結構6包括一可堆疊式封裝結構及至少一上封裝結構4。該可堆疊式封裝結構係與本發明可堆疊式封裝結構3之第一實施例相同。該上封裝結構4係位於該可堆疊式封裝結構3上，且電性連接至該可堆疊式封裝結構3。Referring again to Figure 12, a cross-sectional view of a semiconductor package structure of the present invention is shown. The semiconductor package structure 6 includes a stackable package structure and at least one upper package structure 4. The stackable package structure is the same as the first embodiment of the stackable package structure 3 of the present invention. The upper package structure 4 is located on the stackable package structure 3 and electrically connected to the stackable package structure 3.

參考圖14，顯示本發明可堆疊式封裝結構之第二實施例之剖面示意圖。本實施例之可堆疊式封裝結構5與第一實施例之可堆疊式封裝結構3(圖11)大致相同，其中相同之元件賦予相同之編號。本實施例與第一實施例之不同處在於該晶片之結構不同。在本實施例中，該晶片係為一覆晶晶片34，其包括一上表面341(即背面)、一下表面342(即主動面)及複數個凸塊343，該等凸塊343係位於該下表面342(即主動面)，且該覆晶晶片34係透過該等凸塊343電性連接至該基板31之第二銲墊314。Referring to Figure 14, a cross-sectional view of a second embodiment of the stackable package structure of the present invention is shown. The stackable package structure 5 of the present embodiment is substantially the same as the stackable package structure 3 (FIG. 11) of the first embodiment, wherein the same components are given the same reference numerals. The difference between this embodiment and the first embodiment is that the structure of the wafer is different. In this embodiment, the wafer is a flip chip 34 including an upper surface 341 (ie, a back surface), a lower surface 342 (ie, an active surface), and a plurality of bumps 343. The lower surface 342 (ie, the active surface), and the flip chip 34 is electrically connected to the second pad 314 of the substrate 31 through the bumps 343.

參考圖15，顯示本發明可堆疊式封裝結構之第三實施例之剖面示意圖。本實施例之可堆疊式封裝結構8與第一實施例之可堆疊式封裝結構3(圖11)大致相同，其中相同之元件賦予相同之編號。本實施例與第一實施例之不同處在於該封裝結構8之電性連接點352更包括至少一第三電性連接點352C，該至少一第三電性連接點352C係位於該打線晶片33外之相對位置。Referring to Figure 15, a cross-sectional view of a third embodiment of the stackable package structure of the present invention is shown. The stackable package structure 8 of the present embodiment is substantially the same as the stackable package structure 3 (FIG. 11) of the first embodiment, wherein the same components are given the same reference numerals. The difference between the present embodiment and the first embodiment is that the electrical connection point 352 of the package structure 8 further includes at least one third electrical connection point 352C, and the at least one third electrical connection point 352C is located on the wire bonding die 33. Relative position outside.

參考圖16，顯示本發明可堆疊式封裝結構之第四實施例之剖面示意圖。本實施例之可堆疊式封裝結構9與第一實施例之可堆疊式封裝結構3(圖11)大致相同，其中相同之元件賦予相同之編號。本實施例與第一實施例之不同處在於該封裝結構9更包括一分隔晶片38，其係位於該打線晶片33上用以支撐該等引腳351。Referring to Figure 16, there is shown a cross-sectional view of a fourth embodiment of the stackable package structure of the present invention. The stackable package structure 9 of the present embodiment is substantially the same as the stackable package structure 3 (FIG. 11) of the first embodiment, wherein the same components are given the same reference numerals. The difference between this embodiment and the first embodiment is that the package structure 9 further includes a spacer wafer 38 on the wire bonding die 33 for supporting the pins 351.

參考圖17，顯示本發明可堆疊式封裝結構之第五實施例之剖面示意圖。本實施例之可堆疊式封裝結構10與第一實施例之可堆疊式封裝結構3(圖11)大致相同，其中相同之元件賦予相同之編號。本實施例與第一實施例之不同處在於該封裝結構10更包括一低模流薄膜(Low Modules Film)39，其係包覆該打線晶片33用以支撐該等引腳351。Referring to Figure 17, there is shown a cross-sectional view of a fifth embodiment of the stackable package structure of the present invention. The stackable package structure 10 of the present embodiment is substantially the same as the stackable package structure 3 (FIG. 11) of the first embodiment, wherein the same components are given the same reference numerals. The difference between this embodiment and the first embodiment is that the package structure 10 further includes a Low Modules Film 39 which covers the wire wafer 33 for supporting the pins 351.

藉此，該導線架35使該等電性連接點352之分佈符合一標準記憶體(Standard Memory)之銲球之分佈，而得以堆疊該標準記憶體於本發明可堆疊式封裝結構3,5之頂端。再者，該導線架35可避免使用額外之介電層24(圖2)，而減少本發明可堆疊式封裝結構3,5之總厚度。並且，該導線架35於該封膠體36之上表面361提供一高線路密集度之接合表面，以供堆疊任一種態樣之上封裝結構4。此外，使用一標準四方形之模具以形成該封膠體36，即可顯露該等電性連接點352，而不需研發特殊形狀之模具，故可降低製造成本。Thereby, the lead frame 35 allows the distribution of the electrical connection points 352 to conform to the distribution of the solder balls of a standard memory, and the standard memory is stacked in the stackable package structure 3, 5 of the present invention. The top. Moreover, the leadframe 35 avoids the use of additional dielectric layers 24 (Fig. 2) while reducing the overall thickness of the stackable package structures 3, 5 of the present invention. Moreover, the lead frame 35 provides a high line-dense bonding surface on the upper surface 361 of the encapsulant 36 for stacking the package structure 4 in any of the aspects. In addition, by using a standard square mold to form the sealant 36, the electrical connection points 352 can be revealed without the need to develop a specially shaped mold, thereby reducing manufacturing costs.

惟上述實施例僅為說明本發明之原理及其功效，而非用以限制本發明。因此，習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。However, the above embodiments are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims.

1．．．習知第一種可堆疊式封裝結構1. . . The first stackable package structure

2．．．習知第二種可堆疊式封裝結構2. . . The second stackable package structure

3．．．本發明可堆疊式封裝結構之第一實施例3. . . First embodiment of the stackable package structure of the present invention

3A．．．可堆疊式封裝結構3A. . . Stackable package structure

4．．．上封裝結構4. . . Upper package structure

5．．．本發明可堆疊式封裝結構之第二實施例5. . . Second embodiment of the stackable package structure of the present invention

6．．．本發明半導體封裝結構6. . . Semiconductor package structure of the invention

7．．．上封裝結構7. . . Upper package structure

8．．．本發明可堆疊式封裝結構之第三實施例8. . . Third embodiment of the stackable package structure of the present invention

9．．．本發明可堆疊式封裝結構之第四實施例9. . . Fourth embodiment of the stackable package structure of the present invention

10．．．本發明可堆疊式封裝結構之第五實施例10. . . Fifth embodiment of the stackable package structure of the present invention

11．．．基板11. . . Substrate

12．．．晶片12. . . Wafer

13．．．導線13. . . wire

14．．．封膠體14. . . Sealant

15．．．銲球15. . . Solder ball

21．．．第一基板twenty one. . . First substrate

22．．．第一晶片twenty two. . . First wafer

23．．．底膠twenty three. . . Primer

24．．．介電層twenty four. . . Dielectric layer

25．．．第二基板25. . . Second substrate

26．．．導線26. . . wire

27．．．封膠體27. . . Sealant

28．．．銲球28. . . Solder ball

31．．．基板31. . . Substrate

32．．．銲料32. . . solder

33．．．打線晶片33. . . Wire wafer

34．．．覆晶晶片34. . . Flip chip

35．．．導線架35. . . Lead frame

36．．．封膠體36. . . Sealant

37．．．第一銲球37. . . First solder ball

38．．．分隔晶片38. . . Separate wafer

39．．．低模流薄膜39. . . Low mold flow film

41．．．第二銲球41. . . Second solder ball

111．．．第一表面111. . . First surface

112．．．第二表面112. . . Second surface

113．．．穿導孔113. . . Through hole

114．．．電性連接點114. . . Electrical connection point

211．．．第一表面211. . . First surface

212．．．第二表面212. . . Second surface

221．．．第一凸塊221. . . First bump

251．．．第一表面251. . . First surface

252．．．第二表面252. . . Second surface

253．．．電性連接點253. . . Electrical connection point

311．．．上表面311. . . Upper surface

312．．．下表面312. . . lower surface

313．．．第一銲墊313. . . First pad

314．．．第二銲墊314. . . Second pad

315．．．側邊315. . . Side

331．．．導線331. . . wire

332．．．黏著層332. . . Adhesive layer

341．．．上表面341. . . Upper surface

342．．．下表面342. . . lower surface

343．．．凸塊343. . . Bump

351．．．引腳351. . . Pin

351A．．．第一引腳351A. . . First pin

351B．．．第二引腳351B. . . Second pin

352．．．電性連接點352. . . Electrical connection point

352A．．．第一電性連接點352A. . . First electrical connection point

352B．．．第二電性連接點352B. . . Second electrical connection point

352C．．．第三電性連接點352C. . . Third electrical connection point

353．．．容置空間353. . . Housing space

354．．．邊框354. . . frame

361．．．上表面361. . . Upper surface

362．．．側邊362. . . Side

3511．．．第一部分3511. . . first part

3512．．．第二部分3512. . . the second part

3513．．．中間部分3513. . . Middle part

3514．．．側邊3514. . . Side

3521．．．本體3521. . . Ontology

3522．．．電鍍層3522. . . Plating

圖1顯示顯示習知第一種可堆疊式封裝結構之剖面示意圖；1 shows a schematic cross-sectional view showing a conventional first stackable package structure;

圖2顯示顯示習知第二種可堆疊式封裝結構之剖面示意圖；2 is a cross-sectional view showing a conventional second stackable package structure;

圖3至圖11顯示本發明可堆疊式封裝結構之第一實施例之製造方法之示意圖；3 to 11 are schematic views showing a manufacturing method of a first embodiment of the stackable package structure of the present invention;

圖12顯示本發明可堆疊式封裝結構之第一實施例堆疊一上封裝結構之示意圖；12 is a schematic view showing a stacked package structure of a first embodiment of the stackable package structure of the present invention;

圖13顯示本發明可堆疊式封裝結構之第一實施例堆疊二個上封裝結構之示意圖；13 is a schematic view showing the stacking of two upper package structures in the first embodiment of the stackable package structure of the present invention;

圖14顯示本發明可堆疊式封裝結構之第二實施例之剖面示意圖；Figure 14 is a cross-sectional view showing a second embodiment of the stackable package structure of the present invention;

圖15顯示本發明可堆疊式封裝結構之第三實施例之剖面示意圖；Figure 15 is a cross-sectional view showing a third embodiment of the stackable package structure of the present invention;

圖16顯示本發明可堆疊式封裝結構之第四實施例之剖面示意圖；及Figure 16 is a cross-sectional view showing a fourth embodiment of the stackable package structure of the present invention;

圖17顯示本發明可堆疊式封裝結構之第五實施例之剖面示意圖。Figure 17 is a cross-sectional view showing a fifth embodiment of the stackable package structure of the present invention.

3．．．本發明可堆疊式封裝結構之第一實施例3. . . First embodiment of the stackable package structure of the present invention

31．．．基板31. . . Substrate

32．．．銲料32. . . solder

33．．．打線晶片33. . . Wire wafer

35．．．導線架35. . . Lead frame

36．．．封膠體36. . . Sealant

37．．．第一銲球37. . . First solder ball

311．．．上表面311. . . Upper surface

312．．．下表面312. . . lower surface

313．．．第一銲墊313. . . First pad

314．．．第二銲墊314. . . Second pad

315．．．側邊315. . . Side

331．．．導線331. . . wire

332．．．黏著層332. . . Adhesive layer

351．．．引腳351. . . Pin

351A．．．第一引腳351A. . . First pin

352．．．電性連接點352. . . Electrical connection point

352A．．．第一電性連接點352A. . . First electrical connection point

352B．．．第二電性連接點352B. . . Second electrical connection point

353．．．容置空間353. . . Housing space

361．．．上表面361. . . Upper surface

362．．．側邊362. . . Side

3511．．．第一部分3511. . . first part

3512．．．第二部分3512. . . the second part

3513．．．中間部分3513. . . Middle part

3514．．．側邊3514. . . Side

3521．．．本體3521. . . Ontology

3522．．．電鍍層3522. . . Plating

Claims (58)

一種可堆疊式封裝結構，包括：一基板，具有一上表面、一下表面及至少一第一銲墊，該第一銲墊係位於該上表面；一晶片，位於該基板之上表面，且電性連接至該基板；一導線架，附著於該基板之上表面，該導線架包括複數個引腳及複數個電性連接點，該等引腳連接該等電性連接點，每一引腳包括一第一部分、一第二部分及一中間部分，該第一部分係電性連接該第一銲墊，該第二部分係連接該電性連接點，該中間部分連接該第一部分及該第二部分，該第二部分及該中間部分定義出一容置空間以容置該晶片；及一封膠體，包覆該基板之上表面、該晶片及該導線架，且顯露該等電性連接點。 A stackable package structure comprising: a substrate having an upper surface, a lower surface, and at least one first bonding pad, the first bonding pad being located on the upper surface; a wafer on the upper surface of the substrate, and electrically Connected to the substrate; a lead frame attached to the upper surface of the substrate, the lead frame includes a plurality of pins and a plurality of electrical connection points, the pins are connected to the electrical connection points, each pin The first portion is electrically connected to the first bonding pad, the second portion is connected to the electrical connection point, and the intermediate portion is connected to the first portion and the second portion a portion, the second portion and the intermediate portion define an accommodating space for accommodating the wafer; and a gel covering the upper surface of the substrate, the wafer and the lead frame, and exposing the electrical connection points . 如請求項1之封裝結構，其中該基板更包括複數個第二銲墊，該等第二銲墊位於該上表面。 The package structure of claim 1, wherein the substrate further comprises a plurality of second pads, the second pads being located on the upper surface. 如請求項2之封裝結構，其中該晶片包括一主動面、一背面及複數個凸塊，該等凸塊係位於該主動面，且該晶片係透過該等凸塊電性連接至該基板之該等第二銲墊。 The package structure of claim 2, wherein the wafer includes an active surface, a back surface, and a plurality of bumps, the bumps are located on the active surface, and the wafer is electrically connected to the substrate through the bumps The second pads. 如請求項2之封裝結構，其中該晶片係透過複數條導線電性連接至該基板之該等第二銲墊，且該晶片利用一黏著層附著於該基板。 The package structure of claim 2, wherein the wafer is electrically connected to the second pads of the substrate through a plurality of wires, and the wafer is attached to the substrate by an adhesive layer. 如請求項1之封裝結構，其中每二個相鄰之電性連接點 之間具有一間距。 The package structure of claim 1, wherein each two adjacent electrical connection points There is a gap between them. 如請求項1之封裝結構，其中每一電性連接點包括一本體及一電鍍層，該本體連接該引腳之第二部分，且該電鍍層位於該本體上。 The package structure of claim 1, wherein each of the electrical connection points comprises a body and a plating layer, the body is connected to the second portion of the pin, and the plating layer is located on the body. 如請求項6之封裝結構，其中該電鍍層之材質係為鎳金。 The package structure of claim 6, wherein the material of the plating layer is nickel gold. 如請求項1之封裝結構，其中該等電性連接點包括複數個第一電性連接點及複數個第二電性連接點，該等第一電性連接點及該等第二電性連接點係位於該晶片之正上方。 The package structure of claim 1, wherein the electrical connection points comprise a plurality of first electrical connection points and a plurality of second electrical connection points, the first electrical connection points and the second electrical connections The dot system is located directly above the wafer. 如請求項8之封裝結構，其中該等電性連接點更包括至少一第三電性連接點，該至少一第三電性連接點係位於 該晶片外之相對位置。 The package structure of claim 8, wherein the electrical connection points further comprise at least one third electrical connection point, the at least one third electrical connection point being located The relative position outside the wafer. 如請求項1之封裝結構，其 中該等電性連接點與該封膠體之一上表面齊平。 Such as the package structure of claim 1, The electrical connection points are flush with the upper surface of one of the encapsulants. 如請求項1之封裝結構，其中該封膠體之側邊、該等引腳之側邊及該基板之側邊切齊。 The package structure of claim 1, wherein the side edges of the encapsulant, the sides of the pins, and the sides of the substrate are aligned. 如請求項1之封裝結構，更包括至少一銲料(Solder Paste)，位於該基板之第一銲墊與該引腳之第一部份之間。 The package structure of claim 1, further comprising at least one solder (Solder Paste) between the first pad of the substrate and the first portion of the pin. 如請求項1之封裝結構，更包括複數個第一銲球，位於該基板之下表面。 The package structure of claim 1, further comprising a plurality of first solder balls on a lower surface of the substrate. 如請求項1之封裝結構，更包括一分隔晶片，其係位於該晶片上用以支撐該等引腳。 The package structure of claim 1 further comprising a spacer wafer on the wafer for supporting the pins. 如請求項1之封裝結構，更包括一低模流薄膜(Low Modules Film)，其係包覆該晶片用以支撐該等引腳。 The package structure of claim 1 further includes a low mold flow film (Low) Modules Film), which covers the wafer to support the pins. 一種可堆疊式封裝結構之製造方法，包括：(a)提供一基板，該基板具有一上表面、一下表面及至少一第一銲墊，該第一銲墊係位於該上表面；(b)設置一晶片於該基板之上表面，該晶片係電性連接至該基板；(c)提供一導線架，該導線架包括複數個引腳及複數個電性連接點，該等引腳連接該等電性連接點，每一引腳包括一第一部分、一第二部分及一中間部分，該第二部分係連接該電性連接點，該中間部分連接該第一部分及該第二部分，該第二部分及該中間部分定義出一容置空間以容置該晶片；(d)附著該導線架於該基板之上表面，使每一引腳之第一部分電性連接該第一銲墊，且該晶片位於該容置空間內；及(e)形成一封膠體，以覆蓋該基板之上表面、該晶片及該導線架，且顯露該等電性連接點。 A method for manufacturing a stackable package structure, comprising: (a) providing a substrate having an upper surface, a lower surface, and at least one first bonding pad, the first bonding pad being located on the upper surface; (b) Providing a wafer on an upper surface of the substrate, the wafer is electrically connected to the substrate; (c) providing a lead frame, the lead frame comprising a plurality of pins and a plurality of electrical connection points, the pins connecting the An isoelectric connection point, each of the pins includes a first portion, a second portion and an intermediate portion, the second portion is connected to the electrical connection point, and the intermediate portion is connected to the first portion and the second portion, The second portion and the intermediate portion define an accommodating space for accommodating the wafer; (d) attaching the lead frame to the upper surface of the substrate, so that the first portion of each pin is electrically connected to the first bonding pad, And the wafer is located in the accommodating space; and (e) forming a gel to cover the upper surface of the substrate, the wafer and the lead frame, and exposing the electrical connection points. 如請求項16之方法，其中該步驟(a)中，該基板更包括複數個第二銲墊，位於該上表面。 The method of claim 16, wherein in the step (a), the substrate further comprises a plurality of second pads located on the upper surface. 如請求項17之方法，其中該步驟(b)中，該晶片包括一主動面、一背面及複數個凸塊，該等凸塊係位於該主動面，且該晶片係透過該等凸塊電性連接至該基板之該等第二銲墊。 The method of claim 17, wherein in the step (b), the wafer comprises an active surface, a back surface and a plurality of bumps, the bumps are located on the active surface, and the wafer is electrically transmitted through the bumps The second pads are connected to the substrate. 如請求項17之方法，其中該步驟(b)中，該晶片係透過複 數條導線電性連接至該基板之該等第二銲墊，且該晶片利用一黏著層附著於該基板。 The method of claim 17, wherein in the step (b), the wafer system is transparent A plurality of wires are electrically connected to the second pads of the substrate, and the wafer is attached to the substrate by an adhesive layer. 如請求項16之方法，其中該步驟(b)後，更包括一設置一分隔晶片於該晶片上之步驟。 The method of claim 16, wherein the step (b) further comprises the step of providing a separate wafer on the wafer. 如請求項16之方法，其中該步驟(b)後，更包括一形成一低模流薄膜(Low Modules Film)以包覆該晶片之步驟，該低模流薄膜係利用噴流(Dispensing)或印刷(Printing)方式形成。 The method of claim 16, wherein after the step (b), further comprising the step of forming a low mold film to coat the wafer, the low mold film utilizing a spray or printing The (Printing) method is formed. 如請求項16之方法，其中該步驟(c)後，更包括一提供一膠帶以黏著該等電性連接點及該等引腳之第二部分之步驟，該步驟(e)後，更包括一移除該膠帶之步驟。 The method of claim 16, wherein the step (c) further comprises the step of providing a tape to adhere the electrical connection points and the second portion of the pins, and after the step (e), further comprising A step of removing the tape. 如請求項16之方法，其中該步驟(c)中，每二個相鄰之電性連接點之間具有一間距。 The method of claim 16, wherein in the step (c), there is a spacing between each of the two adjacent electrical connection points. 如請求項16之方法，其中該步驟(c)中，每一電性連接點包括一本體及一電鍍層，該本體連接該引腳之第二部分，且該電鍍層位於該本體上。 The method of claim 16, wherein in the step (c), each of the electrical connection points comprises a body and a plating layer, the body is connected to the second portion of the pin, and the plating layer is located on the body. 如請求項24之方法，其中該步驟(c)中，該電鍍層之材質係為鎳金。 The method of claim 24, wherein in the step (c), the material of the plating layer is nickel gold. 如請求項16之方法，其中該步驟(c)中，該等電性連接點包括複數個第一電性連接點及複數個第二電性連接點，該等第一電性連接點及該等第二電性連接點係位於該晶片之正上方。 The method of claim 16, wherein in the step (c), the electrical connection point comprises a plurality of first electrical connection points and a plurality of second electrical connection points, the first electrical connection points and the The second electrical connection point is located directly above the wafer. 如請求項26之方法，其中該等電性連接點更包括至少一第三電性連接點，該至少一第三電性連接點係位於該晶 片外之相對位置。 The method of claim 26, wherein the electrical connection points further comprise at least one third electrical connection point, wherein the at least one third electrical connection point is located in the crystal The relative position of the film. 如請求項16之方法，其中該步驟(c)中，該等電性連接點與該封膠體之一上表面齊平。 The method of claim 16, wherein in the step (c), the electrical connection point is flush with an upper surface of the encapsulant. 如請求項16之方法，其中該步驟(a)後，更包括一設置至少一銲料(Solder Paste)於該基板之第一銲墊上之步驟，該步驟(d)中，該導線架係利用表面黏著技術(Surface Mount Technology,SMT)透過該銲料附著於該基板之上表面。 The method of claim 16, wherein the step (a) further comprises the step of providing at least one solder on the first pad of the substrate, wherein the lead frame utilizes a surface in the step (d) A surface mount technology (SMT) is attached to the upper surface of the substrate through the solder. 如請求項29之方法，其中該銲料係利用沾錫(Dipping Solder Paste)或印刷製程設置於該基板之第一銲墊上。 The method of claim 29, wherein the solder is disposed on the first pad of the substrate using a Dipping Solder Paste or a printing process. 如請求項16之方法，其中該步驟(e)後，更包括一進行單體化(Singulation)製程，以形成複數個可堆疊式封裝結構之步驟。 The method of claim 16, wherein the step (e) further comprises the step of performing a singulation process to form a plurality of stackable package structures. 如請求項31之方法，其中該單體化製程係為切割或衝壓製程。 The method of claim 31, wherein the singulation process is a cutting or stamping process. 如請求項32之方法，其中該封膠體之側邊、該等引腳之側邊及該基板之側邊切齊。 The method of claim 32, wherein the sides of the encapsulant, the sides of the pins, and the sides of the substrate are aligned. 如請求項16之方法，其中該步驟(e)後，更包括一形成複數個第一銲球於該基板之下表面之步驟。 The method of claim 16, wherein after the step (e), the step of forming a plurality of first solder balls on the lower surface of the substrate is further included. 如請求項16之方法，其中該步驟(e)後，更包括一堆疊至少一上封裝結構之步驟。 The method of claim 16, wherein after the step (e), the step of stacking at least one upper package structure is further included. 如請求項35之方法，其中係堆疊至少二個上封裝結構，該等上封裝結構係為並排。 The method of claim 35, wherein at least two upper package structures are stacked, the upper package structures being side by side. 如請求項35之方法，其中該上封裝結構係為一球柵陣列 封裝結構(Ball Grid Array Package)。 The method of claim 35, wherein the upper package structure is a ball grid array The package structure (Ball Grid Array Package). 如請求項35之方法，其中該上封裝結構包括複數個第二銲球，每一第二銲球係對應且電性連接該導線架之每一電性連接點。 The method of claim 35, wherein the upper package structure comprises a plurality of second solder balls, each of the second solder balls corresponding to and electrically connected to each electrical connection point of the lead frame. 如請求項38之方法，其中每一第二銲球係直接接觸該導線架之每一電性連接點。 The method of claim 38, wherein each of the second solder balls is in direct contact with each electrical connection point of the lead frame. 一種半導體封裝結構，包括：一可堆疊式封裝結構，包括：一基板，具有一上表面、一下表面及至少一第一銲墊，該第一銲墊係位於該上表面；一晶片，位於該基板之上表面，且電性連接至該基板；一導線架，附著於該基板之上表面，該導線架包括複數個引腳及複數個電性連接點，該等引腳連接該等電性連接點，每一引腳包括一第一部分、一第二部分及一中間部分，該第一部分係電性連接該第一銲墊，該第二部分係連接該電性連接點，該中間部分連接該第一部分及該第二部分，該第二部分及該中間部分定義出一容置空間以容置該晶片；及一封膠體，包覆該基板之上表面、該晶片及該導線架，且顯露該等電性連接點；及至少一上封裝結構，位於該可堆疊式封裝結構上，且電性連接至該可堆疊式封裝結構。 A semiconductor package structure comprising: a stackable package structure, comprising: a substrate having an upper surface, a lower surface, and at least one first bonding pad, the first bonding pad being located on the upper surface; a wafer located at the An upper surface of the substrate and electrically connected to the substrate; a lead frame attached to the upper surface of the substrate, the lead frame comprising a plurality of pins and a plurality of electrical connection points, the pins connecting the electrical properties a connecting point, each of the pins includes a first portion, a second portion and an intermediate portion, the first portion is electrically connected to the first bonding pad, and the second portion is connected to the electrical connection point, the intermediate portion is connected The first portion and the second portion, the second portion and the intermediate portion define an accommodating space for accommodating the wafer; and a gel covering the upper surface of the substrate, the wafer and the lead frame, and And exposing the electrical connection points; and at least one upper package structure on the stackable package structure and electrically connected to the stackable package structure. 如請求項40之封裝結構，其中該基板更包括複數個第二 銲墊，該等第二銲墊位於該上表面。 The package structure of claim 40, wherein the substrate further comprises a plurality of second Solder pads, the second pads are located on the upper surface. 如請求項41之封裝結構，其中該晶片包括一主動面、一背面及複數個凸塊，該等凸塊係位於該主動面，且該晶片係透過該等凸塊電性連接至該基板之該等第二銲墊。 The package structure of claim 41, wherein the wafer includes an active surface, a back surface, and a plurality of bumps, the bumps are located on the active surface, and the wafer is electrically connected to the substrate through the bumps The second pads. 如請求項41之封裝結構，其中該晶片係透過複數條導線電性連接至該基板之該等第二銲墊，且該晶片利用一黏著層附著於該基板。 The package structure of claim 41, wherein the wafer is electrically connected to the second pads of the substrate through a plurality of wires, and the wafer is attached to the substrate by an adhesive layer. 如請求項40之封裝結構，其中每二個相鄰之電性連接點之間具有一間距。 The package structure of claim 40, wherein each of the two adjacent electrical connection points has a spacing therebetween. 如請求項40之封裝結構，其中每一電性連接點包括一本體及一電鍍層，該本體連接該引腳之第二部分，且該電鍍層位於該本體上。 The package structure of claim 40, wherein each of the electrical connection points comprises a body and a plating layer, the body is connected to the second portion of the pin, and the plating layer is located on the body. 如請求項45之封裝結構，其中該電鍍層之材質係為鎳金。 The package structure of claim 45, wherein the material of the plating layer is nickel gold. 如請求項40之封裝結構，其中該等電性連接點包括複數個第一電性連接點及複數個第二電性連接點，該等第一電性連接點及該等第二電性連接點係位於該晶片之正上方。 The package structure of claim 40, wherein the electrical connection points comprise a plurality of first electrical connection points and a plurality of second electrical connection points, the first electrical connection points and the second electrical connections The dot system is located directly above the wafer. 如請求項47之封裝結構，其中該等電性連接點更包括至少一第三電性連接點，該至少一第三電性連接點係位於該晶片外之相對位置。 The package structure of claim 47, wherein the electrical connection points further comprise at least one third electrical connection point, the at least one third electrical connection point being located at a relative position outside the wafer. 如請求項40之封裝結構，其中該等電性連接點與該封膠體之一上表面齊平。 The package structure of claim 40, wherein the electrical connection points are flush with an upper surface of the encapsulant. 如請求項40之封裝結構，其中該封膠體之側邊、該等引 腳之側邊及該基板之側邊切齊。 The package structure of claim 40, wherein the side of the sealant, the lead The sides of the foot are aligned with the sides of the substrate. 如請求項40之封裝結構，其中該可堆疊式封裝結構更包括至少一銲料(Solder Paste)，位於該基板之第一銲墊與該引腳之第一部分之間。 The package structure of claim 40, wherein the stackable package structure further comprises at least one solder (Solder Paste) between the first pad of the substrate and the first portion of the pin. 如請求項40之封裝結構，其中該可堆疊式封裝結構更包括複數個第一銲球，位於該基板之下表面。 The package structure of claim 40, wherein the stackable package structure further comprises a plurality of first solder balls on a lower surface of the substrate. 如請求項40之封裝結構，其中該可堆疊式封裝結構更包括一分隔晶片，其係位於該晶片上用以支撐該等引腳。 The package structure of claim 40, wherein the stackable package structure further comprises a spacer wafer on the wafer for supporting the pins. 如請求項40之封裝結構，其中該可堆疊式封裝結構更包括一低模流薄膜(Low Modules Film)，其係包覆該晶片用以支撐該等引腳。 The package structure of claim 40, wherein the stackable package structure further comprises a Low Modules Film that encapsulates the wafer to support the pins. 如請求項40之封裝結構，係包括至少二個上封裝結構，該等上封裝結構係為並排。 The package structure of claim 40 includes at least two upper package structures, which are side by side. 如請求項40之封裝結構，其中該上封裝結構係為一球柵陣列封裝結構(Ball Grid Array Package)。 The package structure of claim 40, wherein the upper package structure is a Ball Grid Array Package. 如請求項40之封裝結構，其中該上封裝結構包括複數個第二銲球，每一第二銲球係對應且電性連接該導線架之每一電性連接點。 The package structure of claim 40, wherein the upper package structure comprises a plurality of second solder balls, each of the second solder balls corresponding to and electrically connected to each electrical connection point of the lead frame. 如請求項57之封裝結構，其中每一第二銲球係直接接觸該導線架之每一電性連接點。The package structure of claim 57, wherein each of the second solder balls directly contacts each of the electrical connection points of the lead frame.
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