CN102751267A - Semiconductor packaging structure for stacking and manufacturing method thereof - Google Patents
Semiconductor packaging structure for stacking and manufacturing method thereof Download PDFInfo
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- CN102751267A CN102751267A CN2012101698153A CN201210169815A CN102751267A CN 102751267 A CN102751267 A CN 102751267A CN 2012101698153 A CN2012101698153 A CN 2012101698153A CN 201210169815 A CN201210169815 A CN 201210169815A CN 102751267 A CN102751267 A CN 102751267A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
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Abstract
The invention discloses a semiconductor packaging structure for stacking and a manufacturing method thereof. The semiconductor packaging structure comprises a first substrate, at least one first chip, a plurality of switching components, at least one insulating material layer, a plurality of electric conduction blind holes and a redistribution layer. The first chip is arranged on the upper surface of the first substrate, the plurality of switching components are arranged on the upper surface of the first substrate, the insulating material layer is in a press fit with the upper surface of the first substrate to cover the first chip and the switching components, at least one open hole arranged on the insulating material layer is used for exposing the switching components, the electric conduction blind holes are formed in the open hole of the insulating material layer, the redistribution layer is arranged on the insulating material layer, a plurality of bonding pads are arranged on the upper surface of the redistribution layer, and the bonding pads penetrate through the redistribution layer and the electric conduction blind holes to be in an electrical connection with the switching components.
Description
Technical field
The invention relates to a kind of semiconductor packaging structure and manufacturing approach thereof, particularly relevant for a kind of semiconductor packaging structure that is used to pile up and manufacturing approach thereof.
Background technology
Along with making rapid progress of science and technology in modern age; The consumer constantly requires more frivolous and multi-purpose electronic product; The semiconductor packages industry is in order to satisfy the demand of various high-density packages; Develop the package design that various different types gradually, (system in package, SIP) design concept is usually used in framework high-density packages product to wherein various system in package.Generally speaking, system in package can be divided into multi-chip module (multi chip module, MCM), the stacked package body (package on package, POP) and packaging body in the stacked package body (package in package, PIP) etc.Said multi-chip module (MCM) is meant lays several chips on same substrate; After chip is set; Utilize same all chips of packing colloid embedding again, and can be subdivided into stacked chips (stacked die) encapsulation or chip (side-by-side) encapsulation side by side again according to the arrangements of chips mode.The structure of said stacked package body is meant that completion one earlier has first packaging body of substrate; Then on first packaging body, pile up another second complete packaging body again; Second packaging body sees through the suitable assembly (like the tin ball) that electrically connects and is electrically connected on the substrate of first packaging body, thereby becomes a compound packaging structure.In comparison; The structure of stacked package body (PIP) then is to utilize another packing colloid that embedding such as the element of second packaging body, adapter assembly and first packaging body etc. together is fixed on the substrate of first packaging body in the said packaging body, thereby becomes a compound packaging structure.Yet, because each packaging body can be distinguished independent test before the assembling, therefore make the stacked package body ensure higher yield and the various element of freely arranging in pairs or groups so that the advantages such as flexible design of product.
In the structure of existing stacked package body (POP); The substrate of following packaging body is generally tellite; And packing colloid generally is the epoxy resin base material that is doped with solid filling; It is referred to as molding compounds (molding compound), and molding compounds is to utilize transfer casting (transfer molding) technology to be made into packing colloid with reservation shape, and the packing colloid of above-mentioned tellite and transfer casting has bigger thickness.Yet in order to satisfy the lightening requirement of electronic product, the thickness of existing stacked package body encapsulating structure can't meet the demand of slimming gradually, and needs further improvement.Again; Under the situation that the thickness of stacked package body reduces gradually, the overall construction intensity of stacked package body (POP) also can be weakened gradually, easily because thermal coefficient of expansion (the coefficient of thermal expansion between tellite and the molding compounds; CTE) different and cause the warpage (warpage) of encapsulating structure; And then cause the fracture (crack) of encapsulating structure easily, in addition, because the packing colloid of the packaging body permission of carrying out laser drilling process is dwindled down; Feasible spacing of dwindling the through hole of packing colloid becomes difficult, so the spacing between the adapter assembly reaches capacity.The result; Because the spacing between the adapter assembly of following packaging body is too big; Make that the area of the upper surface of packaging body can't reduce down; The area of going up simultaneously the lower surface of packaging body also often must cooperate following packaging body to design, and then produces the many unnecessary package dimensions and the waste of material cost.
So, be necessary to provide a kind of semiconductor package and manufacturing approach thereof, to solve the existing in prior technology problem.
Summary of the invention
In view of this, the present invention provides a kind of semiconductor packaging structure that is used to pile up, to solve problems such as the existing in prior technology package dimension and the spacing limit.
For reaching aforementioned purpose of the present invention, one embodiment of the invention provides a kind of semiconductor packaging structure that is used to pile up.Said semiconductor packaging structure comprises one first substrate, at least one first chip, several adapter assemblies, at least one insulation material layer, several conductive blind holes and a re-distribution layer.Said first chip and said adapter assembly are arranged at a upper surface of said first substrate.Said insulation material layer is pressed together on said first substrate, covering said first chip and said adapter assembly, and have the exposed said adapter assembly of at least one perforate, and said conductive blind hole is formed in the said opening.Said re-distribution layer is arranged on the said insulation material layer, and the upper surface of said re-distribution layer has several joint sheets, and said joint sheet sees through said re-distribution layer and said conductive blind hole electrically connects said adapter assembly.
In addition, one embodiment of the invention provides a kind of manufacturing approach of the semiconductor packaging structure that is used to pile up.At first, one first substrate is provided, said first substrate has a upper surface.At least one chip and several adapter assemblies are arranged at the upper surface of said first substrate.Then, at least one insulation material layer is pressed together on the upper surface of said first substrate, to cover said first chip and said adapter assembly, wherein, said insulation material layer has the exposed said adapter assembly of at least one perforate.Afterwards; Forming several conductive blind holes is arranged on the said insulation material layer in said opening and with a re-distribution layer; The upper surface of said re-distribution layer has several joint sheets, and said joint sheet sees through re-distribution layer and said conductive through hole electrically connects said adapter assembly.
For letting the foregoing of the present invention can be more obviously understandable, hereinafter is special lifts several embodiment, and cooperates appended graphicly, elaborates as follows:
Description of drawings
Fig. 1 is the cutaway view of one embodiment of the invention stack type semiconductor packaging structure.
Fig. 2 A to 2G is the schematic flow sheet of the manufacturing approach of one embodiment of the invention semiconductor packaging structure (following packaging body) of being used to pile up.
Fig. 3 is the cutaway view of another embodiment of the present invention stack type semiconductor packaging structure.
Fig. 4 A is the partial enlarged drawing of the adapter assembly of further embodiment of this invention.
Fig. 4 B is the partial enlarged drawing of the adapter assembly of yet another embodiment of the invention.
Embodiment
Below the explanation of each embodiment be with reference to additional graphic, can be in order to illustration the present invention in order to the specific embodiment of implementing.Moreover, the direction term that the present invention mentioned, for example " on ", D score, " preceding ", " back ", " left side ", " right side ", " interior ", " outward " or " side " etc., only be direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the present invention, but not in order to restriction the present invention.
Please with reference to shown in Figure 1; The semiconductor packaging structure that is used to pile up of one embodiment of the invention is mainly used in the packaging body once 100 as the stacked type semiconductor packaging structure; And in order to combine packaging body 200 on, the semiconductor packaging structure that the present invention hereinafter described is used to pile up promptly directly is called packaging body 100 down.In the present embodiment; Said down packaging body 100 comprises: one first substrate 101, at least one first chip 102, several adapter assemblies 103, an insulation material layer 104, several conductive blind holes 105, a re-distribution layer (redistribution layer, RDL) 106 and one welding resisting layer 107.The present invention will specify detail structure, assembled relation and the operation principles thereof of above-mentioned each element of present embodiment one by one in hereinafter.
Please with reference to shown in Figure 1; The said packaging body 100 down of one embodiment of the invention comprises said first substrate 101 in order to carry said first chip 102; Said first substrate 101 mainly is a rigid or bendable printed circuit board (PCB) (printed circuit board who comprises several copper foil layers and insulating resin layer; But the present invention is not limited to this PCB).Said first chip 102 is arranged on projection (bump) 108 on the said first chip 102 active surface down through the mode of printing, electroplating or planting ball in advance; Then active surface is electrically connected to down on several first weld pads 109 of upper surface of said first substrate 101 with flip-chip (flip chip) mode, the surface lines (not illustrating) that said first weld pad 109 sees through said first substrate 101 realizes that fan-out (fan out) function outwards is connected to said second weld pad 110 and adapter assembly 103.
Said adapter assembly 103 for example can be a plurality of metal soldered balls (solder ball) or projection; Its material for example is tin, silver, copper, indium, lead, aluminium, nickel or its alloy; And be electrically connected at several second weld pads 110 of said first substrate, 101 upper surfaces, with the adapter assembly that makes progress as said first substrate 101, the spacing of wherein said adapter assembly 103 (pitch) is between 200 to 500 microns (μ m); Preferably less than 300 microns, for example can be 200,300,400 or 500 microns etc.; The height of said adapter assembly 103 for example can be 60,140,220 or 300 microns etc. then between 60 to 300 microns.The external diameter of said second weld pad 110 for example can be 125,225,325 or 425 microns etc. between 125 to 425 microns.
Please refer again to shown in Figure 1ly, the material of the said insulation material layer 104 of one embodiment of the invention can be dielectric resin material, and for example glass fabric is through containing the made B rank film (B-stage prepreg) of epoxy resin dipping (epoxy) and dry sclerosis back.Utilize its run gum and gummosis characteristic in HTHP; Be pressed together on said first substrate 101; To cover said first chip 102 and said adapter assembly 103; Insert layer (embedded layer) as one and be filled in the gap between said first substrate 101 and said first chip 102 and the said adapter assembly 103, and, each element is coated and fixed on said first substrate by the powerful adhesion that is appeared behind the epoxy resin cure; Said glass fabric then can provide stronger structural strength, and said insulation material layer 104 integral body also have the thermal coefficient of expansion performance that is similar to said first substrate 101.Said insulation material layer 104 has the exposed said adapter assembly 103 of at least one perforate; Said perforate is for wearing glue through hole (through-prepreg via; TPV); It is a structure wide at the top and narrow at the bottom, and minimum diameter can be less than or equal to the width of said adapter assembly 103, and width can be between 50 to 350 microns; Its degree of depth can be between 20 to 180 microns; Depth-to-width ratio is about between 0.3～0.5.Said packaging body down 100 uses the insulation material layer 104 that comprises glass layer 104a and resin material; It helps dwindling the said three-dimensional dimension of packaging body 100 down and the spacing of following joint sheet 111, and reduces the said length and width size that goes up packaging body 200 simultaneously.
Said re-distribution layer 106 forms with the coat of metal through on said insulation material layer 104, forming Seed Layer 112; Said re-distribution layer 106 is fan-in formula (fan-in) re-distribution layer, inwardly is distributed into several joint sheets 111 in order to the position with said adapter assembly 103 again through its circuit.Said joint sheet 111 is arranged at the upper surface of said re-distribution layer 106, wherein said joint sheet 111 can be in regular turn surface lines, first weld pad 109 and projection 108 through the circuit of said re-distribution layer 106, conductive blind hole 105, adapter assembly 103, second weld pad 110, first substrate 101 be electrically connected to said first chip 102.The material of said re-distribution layer 106 can be selected from copper, aluminium, gold, silver or other conductivity good metal.Also comprise a welding resisting layer 107 on the said re-distribution layer 106; Its material can be selected from epoxy resin infrared ray (IR) baking-type; Ultraviolet ray (UV) constrictive type; The anti-solder ink of liquid photosensitive type or dry-film type (dry film), said welding resisting layer 107 cover the said re-distribution layer 106 of part at least and have the zone at the exposed said joint sheet of at least one opening 111 places.
Please with reference to shown in Figure 1; The last packaging body 200 of one embodiment of the invention can be various forms of packaging bodies; The present invention does not limit; The for example said packaging body 200 of going up also comprises one second substrate 201; The upper surface of said second substrate 201 also is provided with at least one second chip 202, and said electric connection assembly 203 solder bond are on the weld pad of the lower surface of said second substrate 201, and said electric connection assembly 203 forms electrical connection through said second substrate 201 with said second chip 202; Said electric connection assembly 203 of while also can form electrical connections with the joint sheet 111 of said packaging body 100 down, and so said packaging body down 100 reaches goes up the framework that packaging body 200 can constitute stacked type packaging body (POP) jointly.
Please with reference to shown in Fig. 2 A to 2G, it discloses the schematic flow sheet of the manufacturing approach of the semiconductor packaging structure (following packaging body 1) that Fig. 1 embodiment of the present invention is used to pile up.
At first, shown in Fig. 2 A, one first substrate 101 is provided earlier, said first substrate 101 has a upper surface and a lower surface, and said upper surface has several first weld pads 109 and second weld pad 110; Then, at least one first chip 102 and several adapter assemblies 103 successively is arranged at the upper surface of said first substrate 101, wherein, said adapter assembly 103 soldered ball ball attachment machines capable of using place soldered ball on said second weld pad 110.Then, projection 108 solder bond that make said first chip 102 through the reflow stove and make said adapter assembly 103 solder bond on second weld pad 110 of said first substrate 101 on first weld pad 109 of said first substrate 101.Said adapter assembly 103 also utilizes plating mode, on said second weld pad 110, forms projection, also can utilize wire bonding machine table formation figure spike projection (stud bump) on said second weld pad 110 gold thread or copper cash.
Subsequently, shown in Fig. 2 B and 2C, an insulation material layer 104 is provided again.。Said insulation material layer 104 is pressed on the upper surface of said first substrate 101, to cover said first chip 102 and said adapter assembly 103.Said insulation material layer 104 is the material of a low young's modulus (Young ' s modulus), and its young's modulus makes warpage degree can obtain control between 50 to 200 Megapascals (MPa).In addition; But impregnation comprises (or not comprising) glass layer 104a in the said insulation material layer 104; When comprising glass layer 104a in the said insulation material layer 104; Then the said glass layer 104a major part after the pressing only is positioned at the top of said first chip 102 and said adapter assembly 103, and is positioned at the below of a upper surface of said insulation material layer 104.Make said insulation material layer 104 in high temperature pressing machine through melten gel (B-stage melt) step; Absorb heat from outside to inside to reduce viscosity and to get back to gummosis state (A-stage); Then under the driving of low pressure and vacuum; Can carry out gummosis toward each pressure lower gradually; And can flow in the gap between said first substrate 101 and said first chip 102 and the adapter assembly 103, tangible polymerization reaction will appear in the resin material of said insulation material layer 104 after a period of time, reach the infinitely-great solid state of viscosity convergence (C-stage) afterwards; Form at least one perforate through for example laser (laser) ablation drilling technique more after cooling, the exposed at least said adapter assembly 103 of said perforate.
Then; Shown in Fig. 2 D; Because the said insulation material layer 104 of high temperature melting that is produced during laser drill; And then produce surperficial cinder, and therefore need to handle as cleaning surfaces through desmearing (desmear) step, use the upper surface of the said insulation material layer 104 of increase and the plating and the electroless tack of perforate inner surface.According to classification, said desmearing step can be selected sulfuric acid process (sulfuric acid), plasma method (plasma), chromic acid method (chromic acid) or permanganimetric method (permanganate) etc. for use, but is not limited to this.Wait to accomplish the step of promptly carrying out plated-through-hole behind the desmearing; Its purpose makes the said insulation material layer 104 advanced row metalizations (metallization) on the said perforate inwall; The polarization characteristic that utilizes perforate internal cause plasma behind the desmearing or other surface treatments and appear; Make said insulation material layer 104 carry out chemical copper deposition (electroless copper deposition) technology (being called electroless copper technology again) easily; And the catalytic action of borrowing palladium metal (Pd) is with copper ion in the solution and formaldehyde (HCHO) effect, and reduce deposition is attached on the hole wall, forms a Seed Layer 112; But the present invention is not limited to this, for example also can use physical deposition modes such as vapor deposition or sputter to form said Seed Layer 112.
Subsequently; Shown in Fig. 2 E; Re-use liquid photoresist (photoresist) or dry film (dry film) technology; Pass through pre-treatment (pretreatment) in regular turn, film or press mold, exposure (exposure), the steps such as (development) of developing; Define said re-distribution layer 106 required circuit and joint sheet figure with the photoresist layer 300 that forms a patterning, see through said line pattern (not illustrating) and realize that fan-in (fan in) function inwardly reassigns to said joint sheet 111 with conductive blind hole 105 position level at said adapter assembly 103 places.
Then; Shown in Fig. 2 F; After treating the said photoresist layer 300 of patterning; Electroplate (pattern plating) in said Seed Layer 112 enterprising row line again and form the thicker copper metal layer of one decks, so that on said insulation material layer 104, be made up of the circuit and the joint sheet 111 of said re-distribution layer 106 jointly said Seed Layer 112 and copper metal layer, wherein said re-distribution layer 106 also forms conductive blind hole 105 to electrically connect said adapter assembly 103 in the perforate of said insulation material layer 104.After forming said re-distribution layer 106, remove said photoresist layer 300, and carry out wet etching process one, do not covered and adiaphorous Seed Layer 112 parts to remove by copper metal layer.
At last; Shown in Fig. 2 G; The welding resisting layer (solder mask) 107 of one patterning is set on the surface of said re-distribution layer 106; Said welding resisting layer 107 forms the exposed whole said joint sheets 111 of a big opening, or also can form exposed respectively each the said joint sheet 111 of several little openings, and wherein said welding resisting layer 107 is called green lacquer again.In this step, the present invention can do suitable alligatoring clean with the surface through methods such as brush mill, little erosion before the application.Then with screen painting (printing), curtain be coated with, mode such as electrostatic spraying is coated on the green lacquer of liquid photosensitive on the plate face, the preliminary drying drying forms the welding resisting layer 107 of said patterning again.Perhaps, earlier through the anti-welding material of coating, utilize the mode of mask (mask) exposure and developing liquid developing to form the welding resisting layer 107 of said patterning again.Above-mentioned anti-welding material preferably epoxy resin (epoxy) is anti-welding material.The opening of the welding resisting layer 107 of said patterning is to being positioned at the zone at said joint sheet 111 places.
After accomplishing above-mentioned steps, the present invention promptly makes packaging body 100, said packaging body 100 down can with Fig. 1 one on packaging body 200 be combined into the stacked type semiconductor packaging structure jointly.Said packaging body down 100 uses the insulation material layer 104 that comprises glass layer 104a and resin material; Therefore help dwindling the said three-dimensional dimension of packaging body 100 down and the spacing of following joint sheet 111, and reduce the said length and width size that goes up packaging body 200 simultaneously.
Fig. 3 is the cutaway view of another embodiment of the present invention stack type semiconductor packaging structure; The stack type semiconductor packaging structure of Fig. 3 embodiment is approximately identical to the stack type semiconductor packaging structure of Fig. 1 embodiment; But in the stack type semiconductor packaging structure of Fig. 3 embodiment; Said packaging body 100 down also can electrically engage with at least one combination of going up packaging body 200 and at least one passive component 400 through said joint sheet 111 simultaneously; Or packaging body 200 electrically engages on the while and at least two, or electrically engages with at least two passive components (passive element) 400 simultaneously.Said welding resisting layer 107 can form the exposed whole said joint sheets 111 of a big opening, or also can form exposed respectively each the said joint sheet 111 of several little openings.In addition; Said first substrate 101, first chip 102, projection 108, first weld pad 109, second weld pad 110, adapter assembly 103, second substrate 201, second chip 202 and electrically connect assembly 203 making or assembling mode and the then identical Fig. 1 embodiment of the present invention of effect following packaging body 100 and go up packaging body 200, therefore give in detail no longer in addition and giving unnecessary details.
Fig. 4 A and 4B are respectively that further embodiment of this invention reaches the partial enlarged drawing of the adapter assembly of an embodiment again; The stack type semiconductor packaging structure of Fig. 4 A and 4B embodiment is approximately identical to the stack type semiconductor packaging structure of Fig. 1 embodiment; But in the stack type semiconductor packaging structure of Fig. 4 A and 4B embodiment; Said adapter assembly 103 also can be the structures that electrically conduct such as column-like projection block or figure spike projection; It is electrically connected at several second weld pads 110 of said first substrate, 101 upper surfaces equally; Wherein said column-like projection block for example is copper post projection (Cu pillar bumps), and said figure spike projection for example is a golden projection (Gold bumps) of pulling apart formation behind the routing, but the present invention is not limited to this.
The present invention is described by above-mentioned related embodiment, yet the foregoing description is merely the example of embodiment of the present invention.Must be pointed out that disclosed embodiment does not limit scope of the present invention.On the contrary, being contained in the spirit of claims and the modification and impartial setting of scope includes in scope of the present invention.
Claims (20)
1. semiconductor packaging structure that is used to pile up, it is characterized in that: said semiconductor packaging structure comprises:
One first substrate has a upper surface;
At least one first chip is arranged at the upper surface of said first substrate;
Several adapter assemblies are arranged at the upper surface of said first substrate;
At least one insulation material layer is pressed on the upper surface of said first substrate, covering said first chip and said adapter assembly, and has the exposed said adapter assembly of at least one perforate;
Several conductive blind holes are formed in the perforate of said insulation material layer; And
One re-distribution layer is arranged on the said insulation material layer, and the upper surface of said re-distribution layer has several joint sheets, and said joint sheet sees through said re-distribution layer and said conductive blind hole electrically connects said adapter assembly.
2. the semiconductor packaging structure that is used to pile up as claimed in claim 1; It is characterized in that: said semiconductor packaging structure is as the packaging body once of stacked type packaging structure, and several of a lower surface that electrically connect packaging body on through said joint sheet electrically connect assemblies.
3. the semiconductor packaging structure that is used to pile up as claimed in claim 1 is characterized in that: said insulation material layer is the material of a low young's modulus.
4. the semiconductor packaging structure that is used to pile up as claimed in claim 3 is characterized in that: the young's modulus of said insulation material layer is between 50 to 500 Megapascals.
5. the semiconductor packaging structure that is used to pile up as claimed in claim 1 is characterized in that: also contain in the said insulation material layer and be soaked with a glass layer.
6. the semiconductor packaging structure that is used to pile up as claimed in claim 5 is characterized in that: said glass layer is between a upper surface of said first chip and said insulation material layer.
7. the semiconductor packaging structure that is used to pile up as claimed in claim 1 is characterized in that: the diameter of said conductive blind hole is less than the width of said adapter assembly.
8. the semiconductor packaging structure that is used to pile up as claimed in claim 1 is characterized in that: the depth-to-width ratio of said conductive blind hole is less than 0.5.
9. the semiconductor packaging structure that is used to pile up as claimed in claim 1 is characterized in that: said re-distribution layer is a fan-in formula re-distribution layer.
10. the semiconductor packaging structure that is used to pile up as claimed in claim 2 is characterized in that: the length and width size of the said upward lower surface of packaging body is less than the said length and width size of the upper surface of packaging body down.
11. the semiconductor packaging structure that is used to pile up as claimed in claim 2 is characterized in that: said adapter assembly is selected from projection or metal ball, said electric connection assembly is selected from projection or metal ball.
12. the semiconductor packaging structure that is used to pile up as claimed in claim 1 is characterized in that: the spacing of said adapter assembly is between 200 to 500 microns.
13. the semiconductor packaging structure that is used to pile up as claimed in claim 12 is characterized in that: the spacing of said adapter assembly is less than 300 microns.
14. the manufacturing approach of a semiconductor packaging structure that is used to pile up is characterized in that: said manufacturing approach comprises step:
One first substrate is provided, and said first substrate has a upper surface;
At least one chip is arranged at the upper surface of said first substrate;
Several adapter assemblies are arranged at the upper surface of said first substrate;
At least one insulation material layer is pressed together on the upper surface of said first substrate, to cover said first core
Sheet and said adapter assembly, said insulation material layer have the exposed said adapter assembly of at least one perforate;
Form several conductive blind holes in the perforate of said insulation material layer; And
One re-distribution layer is arranged on the said insulation material layer, and the upper surface of said re-distribution layer has several joint sheets, and said joint sheet sees through said re-distribution layer and said conductive blind hole electrically connects said adapter assembly.
15. the manufacturing approach of the semiconductor packaging structure that is used to pile up as claimed in claim 14; It is characterized in that: said semiconductor packaging structure is as the packaging body once of stacked type packaging structure, and several of a lower surface that electrically connect packaging body on through said joint sheet electrically connect assemblies.
16. the manufacturing approach of the semiconductor packaging structure that is used to pile up as claimed in claim 14 is characterized in that: fill in the gap of said insulation material layer between said first substrate and said first chip and adapter assembly.
17. the manufacturing approach of the semiconductor packaging structure that is used to pile up as claimed in claim 14; It is characterized in that: be pressed together at said insulation material layer on the upper surface of said first substrate; After the step that covers said first chip and said adapter assembly, define the perforate of said insulation material layer through laser drill.
18. the manufacturing approach of the semiconductor packaging structure that is used to pile up as claimed in claim 14 is characterized in that: said re-distribution layer is a fan-in formula re-distribution layer.
19. the manufacturing approach of the semiconductor packaging structure that is used to pile up as claimed in claim 15 is characterized in that: the length and width size of the said upward lower surface of packaging body is less than the said length and width size of the upper surface of packaging body down.
20. the manufacturing approach of the semiconductor packaging structure that is used to pile up as claimed in claim 14 is characterized in that: also contain in the said insulation material layer and be soaked with a glass layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101698153A CN102751267A (en) | 2012-05-28 | 2012-05-28 | Semiconductor packaging structure for stacking and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101698153A CN102751267A (en) | 2012-05-28 | 2012-05-28 | Semiconductor packaging structure for stacking and manufacturing method thereof |
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| CN102751267A true CN102751267A (en) | 2012-10-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2012101698153A Pending CN102751267A (en) | 2012-05-28 | 2012-05-28 | Semiconductor packaging structure for stacking and manufacturing method thereof |
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| CN104810339A (en) * | 2014-01-29 | 2015-07-29 | 矽品精密工业股份有限公司 | Package substrate and method for fabricating the same, and semiconductor package and method for fabricating the same |
| CN105405827A (en) * | 2015-12-22 | 2016-03-16 | 华进半导体封装先导技术研发中心有限公司 | Multi-stacked fanout package structure with low cost and fabrication method thereof |
| CN105529276A (en) * | 2015-12-22 | 2016-04-27 | 华进半导体封装先导技术研发中心有限公司 | Low-cost multi-stacked fanout package structure and preparation method thereof |
| CN107046170A (en) * | 2016-02-08 | 2017-08-15 | 波音公司 | The expansible planar package framework of active scan formula phased array antenna system |
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Application publication date: 20121024 |