JP2004071946A

JP2004071946A - Wiring substrate, substrate for semiconductor package, semiconductor package, and their manufacturing method

Info

Publication number: JP2004071946A
Application number: JP2002231310A
Authority: JP
Inventors: Osamu Shimada; 嶋田　修; Toshimasa Nagoshi; 名越　俊昌; Kazuhisa Suzuki; 鈴木　和久; Mitsuo Kikuchi; 菊地　満男
Original assignee: Hitachi Chemical Co Ltd
Current assignee: Showa Denko Materials Co Ltd
Priority date: 2002-08-08
Filing date: 2002-08-08
Publication date: 2004-03-04
Anticipated expiration: 2022-08-08
Also published as: JP4288912B2

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for simply forming a resin layer to a rugged member used for manufacturing a wiring substrate and to provide a method for simply forming the resin layer not causing a bent or a swell to the member. <P>SOLUTION: The manufacturing method of a wiring material includes a print process of printing an insulating resin in a fluid varnishing state before curing to a wire member having a plurality of conductive projections on its surface in a thickness so that the conductive projections are buried with the insulating resin; a curing process of curing the printed insulating resin; and a polishing process of polishing the insulating resin to expose the tips of the conductive projections, and the manufacturing method of an element built-in type wiring substrate includes the steps wherein electronic components are mounted on the wiring substrate, an insulating resin in a fluid varnishing state before curing is coated by printing to the wiring substrate to bury electronic components, an insulating layer is formed by curing the printed insulating resin, and a wire is provided onto the insulating resin layer. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、配線板、半導体パッケージ用基板、半導体パッケージ及びそれらの製造方法に関するものである。
【０００２】
【従来の技術】
電子機器の小型化や高性能化への要求に伴い、半導体の集積度は年々向上し入出力端子が増加している。それに伴って、半導体を搭載する半導体パッケージも多くの入出力端子を必要とするようになり、また、同時に小型化も要求されているため高密度化が進行している。このような要求にこたえる半導体パッケージとして、従来の周辺にしか端子が配置できないリードフレームタイプのＳＯＰ（Ｓｍａｌｌ　Ｏｕｔｌｉｎｅ　Ｐａｃｋａｇｅ）やＱＦＰ（Ｑｕａｄ　Ｆｌａｔ　Ｐａｃｋａｇｅ）に変わって、端子を面上に配置できるＢＧＡ（Ｂａｌｌ　Ｇｒｉｄ　Ａｒｒａｙ）が使用されるようになった。また、最近では、さらに小型な半導体パッケージが必要とされる分野には、チップの外形とほぼ同サイズのＣＳＰ（Ｃｈｉｐ　Ｓｉｚｅ　Ｐａｃｋａｇｅ）が開発され用いられている。これらＢＧＡやＣＳＰは、チップを搭載する基板として、インターポーザと呼ばれる配線基板を用いており、より小型で高密度、かつ低コストな半導体パッケージ用の配線基板が望まれている。
【０００３】
このような要求を満たす配線基板の例として、特開２００２−０４３４６７号公報に報告されているような、接続端子用導体と、接続端子用導体間を埋める樹脂と、接続端子の搭載される面と反対面に設けられた回路用導体からなる配線基板がある。
一方、近年、半導体パッケージの集積度をより向上させるため、１つのパッケージ内に複数のチップをパッケージングしたＭＣＰ（Ｍｕｌｔｉ　Ｃｈｉｐ　Ｐａｃｋａｇｅ）が開発され、また、ＳＩＰ（Ｓｙｓｔｅｍ　Ｉｎ　Ｐａｃｋａｇｅ）と呼ばれる従来ボード上で実現してきたシステムを１つのパッケージにて実現しようとする試みが広がっている。このようなパッケージの形成方法として、チップと配線基板を接続後に、樹脂で埋めその上に配線を形成し積層していく方法がある。
以上のような情勢において、近年、凹凸の有る部材や中間体に対し、絶縁樹脂で埋める工程が増えつつある。しかし、無機、有機物質が複雑に組み合わさっている半導体パッケージや配線板では、樹脂と銅配線、半導体チップ等の異なる材料間の接着性が重要であり、また、同時にそりやうねりのない高い平坦性が要求されている。
【０００４】
【発明が解決しようとする課題】
しかしながら、樹脂層を形成する方法として、樹脂シートをプレスして形成する場合、上記のような凹凸ある部材に対し、樹脂の追随性が問題となる。また、チップを埋める場合には、チップへかかる圧力によりチップの割れが心配される。
本発明は、半導体パッケージ用基板やその他の配線板の製造に用いられる凹凸のある部材に対し、簡便に樹脂層を形成する方法を提案するものである。そして、通常、配線部材、特に導電性突起を有する部材に樹脂層を形成する場合、未硬化状態の樹脂を塗布し硬化すると、樹脂の収縮や、部材と樹脂との熱膨張差に起因してそりやうねりが発生する。また、そりやうねりを抑える方法として、無機粒子を高比率配合させた低収縮の樹脂を用いる方法があるが、その方法では樹脂と部材との接着性が悪くなる問題があった。本発明は、さらに、樹脂層の形成方法に加え、接着性が良く、そりやうねりが発生しない樹脂層を形成する方法をも提供するものである。
【０００５】
【課題を解決するための手段】
本発明は、１．導電性突起を有した金属箔に樹脂層を形成し、その後、研磨で導電性突起を露出させる工程により製造される半導体パッケージ用基板、配線板、２．導電性突起を有した導体と絶縁樹脂からなる配線部材に樹脂層を形成し、その後、研磨で導電性突起を露出させる工程により製造される半導体パッケージ用基板、配線板、３．チップや受動部品を配線基板に実装した後に樹脂で埋め込み、樹脂層を形成し、その上に配線を設ける、素子内蔵型の半導体パッケージ、又は配線板、の３つのものに樹脂層を形成する方法として、ワニス状態にある樹脂を印刷により塗布し、硬化することで形成する方法を提案する。
【０００６】
即ち、本発明は、下記の（１）〜（２１）に関する。
（１）　表面に複数の導電性突起を有する配線部材に、硬化前の流動状のワニス状態にある絶縁樹脂を、印刷により、導電性突起が絶縁樹脂で埋め込まれる厚みに塗布する印刷工程、印刷した絶縁樹脂を硬化させる硬化工程、及び、絶縁樹脂を研磨して導電性突起の先端を露出させる研磨工程を含む配線板の製造方法。
（２）　配線板が半導体パッケージ用基板である（１）記載の配線板の製造方法。
（３）　配線部材が、表面に複数の導電性突起を有する金属箔である（１）又は（２）に記載の配線板の製造方法。
（４）　配線部材が、絶縁樹脂層、絶縁樹脂層両面上の層間接続された導体層、及び絶縁樹脂層の少なくとも片面上に導電性突起を有するものである（１）又は（２）に記載の配線板の製造方法。
（５）　硬化工程の後に研磨工程を行なう（１）〜（４）いずれかに記載の配線板の製造方法。
【０００７】
（６）　表面に複数の導電性突起を有する配線部材に、硬化前の流動状のワニス状態にある絶縁樹脂を、印刷により、導電性突起が絶縁樹脂で埋め込まれる厚みに塗布する印刷工程、印刷した絶縁樹脂を、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥する乾燥工程、半硬化した状態まで乾燥した絶縁樹脂を研磨して導電性突起の先端を露出させる研磨工程、研磨後に絶縁樹脂を完全に硬化させる硬化工程を含む（１）〜（４）いずれかに記載の配線板の製造方法。
（７）　配線部材の導電性突起を有する面に、流動状のワニス状態にある絶縁樹脂（１）を印刷し、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥し、更に、絶縁樹脂（１）と成分が異なり、流動状のワニス状態にある絶縁樹脂（２）及び絶縁樹脂（２）と成分が異なり、流動状のワニス状態にある絶縁樹脂（３）の少なくとも２種類の絶縁樹脂を、この順で、各々、印刷し、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥することにより、絶縁樹脂（１）の層、絶縁樹脂（２）の層及び絶縁樹脂（３）の層の少なくとも３層からなる多層絶縁樹脂層を、導電性突起が絶縁樹脂で埋め込まれる厚みに形成する工程、多層絶縁樹脂層中の全ての絶縁樹脂を同時に完全に硬化させる硬化工程、及び、多層絶縁樹脂層を研磨して導電性突起の先端を露出させる研磨工程を含む（１）〜（４）いずれかに記載の配線板の製造方法。
【０００８】
（８）　硬化工程を研磨工程の後に行なう（７）に記載の配線板の製造方法。
（９）　多層絶縁樹脂層を形成する工程において、絶縁樹脂（１）として配線部材と接着性の良い絶縁樹脂を用い、絶縁樹脂（２）の層及び絶縁樹脂（３）の層を含む第２層以上の層に、作製された配線板のそりを低減させる特性を有した絶縁樹脂を使用した（７）又は（８）に記載の配線板の製造方法。
（１０）　（７）又は（８）に記載の半硬化状態で樹脂を積層する工程において、無機又は有機粒子の含有率が異なる樹脂、又は基本樹脂構造が異なる樹脂、を印刷により任意の位置、形状、厚みで形成し、その後、樹脂を積層することにより、絶縁樹脂中に性質の異なる樹脂を任意の箇所に混在させた樹脂層を形成する方法。
（１１）　（１）〜（１０）いずれかに記載の方法により製造された配線板。
（１２）　（１）〜（１０）いずれかに記載の方法により製造された半導体パッケージ用基板。
（１３）　（１２）に記載の半導体パッケージ用基板を用いた半導体パッケージ。
【０００９】
（１４）　電子部品を配線板に実装した後に絶縁樹脂で埋め込み、絶縁樹脂層を形成し、その絶縁樹脂層の上に配線を設ける、素子内蔵型の配線板の製造方法であって、電子部品を配線板に実装した後、硬化前の流動状のワニス状態にある絶縁樹脂を印刷により塗布して電子部品を埋めこみ、印刷した絶縁樹脂を硬化させて絶縁樹脂層を形成することを特徴とする製造方法。
（１５）　電子部品が半導体チップであり、素子内蔵型の配線板が素子内蔵型の半導体パッケージである（１４）に記載の方法。
（１６）　配線板の電子部品実装面に、流動状のワニス状態にある絶縁樹脂（１）を印刷し、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥し、更に、絶縁樹脂（１）と成分が異なり、流動状のワニス状態にある絶縁樹脂（２）及び絶縁樹脂（２）と成分が異なり、流動状のワニス状態にある絶縁樹脂（３）の少なくとも２種類の絶縁樹脂を、この順で、各々、印刷し、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥することにより、絶縁樹脂（１）の層、絶縁樹脂（２）の層及び絶縁樹脂（３）の層の少なくとも３層からなる多層絶縁樹脂層を、電子部品が絶縁樹脂で埋め込まれる厚みに形成する工程、多層絶縁樹脂層中の全ての絶縁樹脂を同時に完全に硬化させる硬化工程、及び、多層絶縁樹脂層上に配線を設ける工程を含む（１４）又は（１５）に記載の配線板の製造方法。
（１７）　多層絶縁樹脂層を形成する工程の後、多層絶縁樹脂層の表面を平坦に研磨した後に硬化工程を行なう（１６）に記載の方法。
【００１０】
（１８）　多層絶縁樹脂層を形成する工程において、絶縁樹脂（１）として配線板及び電子部品と接着性の良い絶縁樹脂を用い、絶縁樹脂（２）の層及び絶縁樹脂（３）の層を含む第２層以上の層に、作製された素子内蔵型の配線板のそりを低減させる特性を有した絶縁樹脂を使用した（１６）〜（１８）いずれかに記載の配線板の製造方法。
（１９）　（１６）〜（１８）いずれかに記載の半硬化状態で樹脂を積層する工程において、無機又は有機粒子の含有率が異なる樹脂、又は基本樹脂構造が異なる樹脂、を印刷により任意の位置、形状、厚みで形成し、その後、樹脂を積層することにより、絶縁樹脂中に性質の異なる樹脂を任意の箇所に混在させた樹脂層を形成する方法。
（２０）　（１４）〜（１９）いずれかに記載の方法により製造された素子内蔵型の配線板。
（２１）　（１４）〜（１９）いずれかに記載の方法により製造された素子内蔵型の半導体パッケージ。
【００１１】
また、樹脂層の形成方法として、１）配線部材と接着性の良い絶縁樹脂を硬化前の流動性のあるワニス状態で薄く塗布し、塗布後、流動性がなくなるが完全に硬化していない半硬化状態に乾燥して第１層とする工程、２）流動性がなく半硬化状態にある第１層の樹脂層の上から、そりやうねりが発生しないように配合した樹脂を、未硬化でワニス状態にある液状のまま塗布し、同様に流動性がなくなる半硬化状態に乾燥して第２層とする工程、３）樹脂層のバランスを取るために、第１層と同一、又は異なる樹脂を第２層の上に流動状のワニス状態で塗布し、塗布後、流動性のなくなる半硬化状態に乾燥して第３層とする工程、４）半硬化状態にある全ての樹脂層を、一括して完全な硬化の状態に硬化する工程、よりなる製造法を提供する。
【００１２】
【発明の実施の形態】
本発明の配線板の製造方法は、表面に複数の導電性突起を有する配線部材に、硬化前の流動状のワニス状態にある絶縁樹脂を、印刷により、導電性突起が絶縁樹脂で埋め込まれる厚みに塗布する印刷工程、印刷した絶縁樹脂を硬化させる硬化工程、及び、絶縁樹脂を研磨して導電性突起の先端を露出させる研磨工程を含む。
本発明の方法で製造される配線板としては、例えば、半導体パッケージに用いられるインターポーザーとしての半導体パッケージ用基板、半導体パッケージやその他の電子部品を搭載するマザーボード等のその他の配線板が挙げられる。
本発明で用いられる表面に複数の導電性突起を有する配線部材としては、例えば、下記のものが挙げられる。
【００１３】
１．表面に導電性突起を有する金属箔。例えば、第１、第３の金属層が第２の金属層とエッチング条件の異なる金属層である３層の金属箔を、ドライフィルムレジストを用いたエッチングにより第１の金属層を柱状バンプとした金属箔、及び、上記の３層の金属箔を、ドライフィルムレジストを用いたエッチングにより第１の金属層を柱状バンプとし、次いで第２の金属層を、柱状バンプの下部を除いて第３の金属層が露出するまでエッチング除去した金属箔がある。このときの第１、３の金属層が銅、銅合金の場合には、第２の金属層としては、ニッケル、ニッケル合金、チタン、クロム、錫、亜鉛等がある。
２．導電性突起を有した導体と絶縁樹脂からなる配線部材。例えば、配線部材が、絶縁樹脂層、絶縁樹脂層両面上の層間接続された導体層、及び絶縁樹脂層の少なくとも片面上に導電性突起を有するもの。例えば、上記金属箔に、柱状バンプの端面を露出させて樹脂層を形成したものの樹脂層形成面に上記３層金属箔を加熱圧着し、その後、同様に第１層の金属層を柱状バンプとしたものがある。また、一般的な両面配線板の表面に、銀ペースト等の導電性ペーストを印刷して導電性突起を形成したもの、めっきレジスト等を使用して、めっき析出で金属突起を形成したものも含む。
３．素子内蔵型の半導体パッケージ、又は配線板における中間部材。
【００１４】
本発明で使用する絶縁樹脂の例としては、ポリイミド樹脂、ポリアミドイミド樹脂、シリコーン樹脂、フェノール樹脂、ビスマレイミドトリアジン樹脂、エポキシ樹脂、アクリル樹脂等の熱硬化性樹脂、ポリフェニレンサルファイド樹脂、感光性ポリイミド樹脂、アクリルエポキシ樹脂、エチレン、プロピレン、スチレン、ブタジエン等の熱可塑性エラストマー、液晶ポリマー等がある。また、これらの樹脂に有機粒子や無機粒子を配合したものも使用することができる。樹脂に配合することができる有機粒子の例としては、前述の樹脂の硬化物、無機粒子の例としてはアルミナ粒子、二酸化ケイ素（シリカ）、ガラス繊維等がある。これらの有機又は無機粒子の粒径は、平均粒径が０．１〜２０μｍであることが好ましい。
本発明においては、硬化前の流動状のワニス状態にある絶縁樹脂を、配線部材の導電性突起を有する表面に、導電性突起が絶縁樹脂で埋め込まれる厚みに、印刷により塗布する。流動状のワニス状態にある絶縁樹脂は、印刷時に粘度が３〜７０Ｐａ・ｓであることが好ましい。印刷方法としては、メッシュスクリーンマスク、メタルマスク等を用いたスクリーン印刷法、及び配線部材上に直接スキージ、ブレード等を用いて、すり切り又は隙間を空けて均一な厚みに樹脂を塗布する方法、及び樹脂をドラム又はボード等に塗布した後、配線部材上に樹脂を転写する方法等がある。また、これら作業を真空下で行なう方法も、未充填箇所をなくすには有効である。
【００１５】
印刷工程の後、硬化工程の後に研磨工程を行なってもよい。また、研磨工程の後に硬化工程を行なってもよい。その場合、研磨工程の前に、縁樹脂を、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥する乾燥工程を行い、次いで、半硬化した状態まで乾燥した絶縁樹脂を研磨して導電性突起の先端を露出させる研磨工程を行い、その後、絶縁樹脂を完全に硬化させる硬化工程を行なう。この後者の方法では、完全に硬化した樹脂より柔らかいため、研磨効率が向上する。
【００１６】
絶縁樹脂層を形成する配線部材に応じて、各層の樹脂の配合成分、樹脂種類、厚み、或いは層数を変えることで、全体のそり量を制御できる。絶縁樹脂としては、１種類のみを用いて単層の樹脂層を形成してもよいし、２種類以上の絶縁樹脂、同一組成の樹脂にフィラー等の充填率を変えたものも含めて、これらを用いて、多層絶縁樹脂層を形成してもよい。また、多層絶縁樹脂層とする場合、第１層の樹脂を、部材の種類、表面状態に合わせ選択することで接着性の良い層とすることができる。
例えば、配線部材の導電性突起を有する面に、流動状のワニス状態にある絶縁樹脂（１）を印刷し、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥し、更に、絶縁樹脂（１）と成分が異なり、流動状のワニス状態にある絶縁樹脂（２）及び絶縁樹脂（２）と成分が異なり、流動状のワニス状態にある絶縁樹脂（３）の少なくとも２種類の絶縁樹脂を、この順で、各々、印刷し、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥することにより、絶縁樹脂（１）の層、絶縁樹脂（２）の層及び絶縁樹脂（３）の層の少なくとも３層からなる多層絶縁樹脂層を、導電性突起が絶縁樹脂で埋め込まれる厚みに形成する。その後、研磨工程の前又は後に硬化工程を行ない、多層絶縁樹脂層中の全ての絶縁樹脂を同時に完全に硬化させる。
【００１７】
好ましくは、１）配線部材と接着性の良い絶縁樹脂を硬化前の流動性のあるワニス状態で薄く塗布し、塗布後、流動性がなくなるが完全に硬化していない半硬化状態に乾燥して第１層とする工程、２）流動性がなく半硬化状態にある第１層の樹脂層の上から、そりやうねりが発生しないように配合した絶縁樹脂を、未硬化でワニス状態にある液状のまま塗布し、同様に流動性がなくなる半硬化状態に乾燥して第２層とする工程、３）多層絶縁樹脂層のバランスを取るために、第１層と同一、又は異なる絶縁樹脂を第２層の上に流動状のワニス状態で塗布し、塗布後、流動性のなくなる半硬化状態に乾燥して第３層とする工程により、多層絶縁樹脂層を形成する。次いで、研磨工程の前又は後に、４）半硬化状態にある全ての樹脂層を、一括して完全な硬化の状態に硬化する工程を行なう。
【００１８】
一般的に、樹脂を低収縮、低熱膨張にするためには、無機粒子を高い比率で配合させるが、その場合、樹脂と部材との接着力が低下する。そのため、接着界面の第１層を無機粒子の含まない、又は少量、例えば絶縁樹脂中１〜２０重量％含む樹脂層とし、第２層に無機粒子を第１層に対して高い比率、例えば絶縁樹脂中２０重量％より多く９０重量％以下で配合した樹脂層とする。このことにより、接着性の良い状態で低収縮、低熱膨張の樹脂層を形成することができる。多層絶縁樹脂層が３層構造である場合、第３層には、第１層と同じ絶縁樹脂を用いることが好ましい。
また、本発明は、無機、有機粒子等のフィラー成分を多く含有した樹脂を任意の開口を設けたステンシルマスクを通して印刷して乾燥し、繰り返し印刷、乾燥を行うことで、絶縁樹脂中に無機、有機粒子成分を任意の箇所に混在させる方法としても利用できる。この際、同一樹脂を使用することは、各層間との密着信頼性を向上する上で望ましい。
【００１９】
研磨工程における研磨方法としては、ロールペーパー研磨、サンドブラスト法、ホーニング、ラッピング等があり、また刃物を使用した機械加工法、例えばルータ加工等でもよい。また、絶縁樹脂を半硬化状態で研磨をすることは、硬化状態に比べ硬度が低いため、研磨効率を上げることができる。
なお、記載されている樹脂の半硬化状態とは、流動性がなくなり、研磨可能な状態に硬化されたもので完全な硬化に至っていない樹脂の状態を指す。熱硬化性樹脂ではＢステージ状態と呼ばれ、樹脂により異なるが、一般的に硬化率が３０〜８０％のものを指す。この硬化率は、ＤＳＣ（示差走査熱分析）により測定することが可能である。絶縁樹脂の半硬化状態までの乾燥、及び、完全硬化は、絶縁樹脂が熱硬化性樹脂の場合、加熱により行ない、研磨時の室温（５〜３５℃）に戻した状態において、流動性がなく、外力を加えた際に弾性変形又は塑性変形し、外圧をなくすと弾性変形の場合は元の状態に戻り、塑性変形した場合には変形した状態を維持するような状態が研磨可能な状態である。
溶剤希釈タイプの熱可塑性材料の場合、溶剤分を適度に除去することにより、半硬化状態にすることができる。溶剤分を除去する方法としては、加熱又は減圧する方法等がある。熱硬化性樹脂と同様、研磨可能な状態とは、流動性がなく、外力を加えた際に、弾性変形又は塑性変形し、外圧をなくすと弾性変形の場合は元の状態に戻り、塑性変形した場合は変形した状態を維持するような状態である。
【００２０】
感光性ポリイミド等、感光性樹脂を使用する場合、紫外線照射量により硬化量を制御することができる。また、感光性樹脂の場合は、導電性突起上部をマスキング等により紫外線が当たらないようにし、導電性突起部以外の部分の紫外線照射量より紫外線照射量を低減し、導電性突起上部が他の部分より未硬化の状態にすることで、導電性突起上部をより集中して研磨ができ、研磨効率を上げることができる。さらに、この感光性樹脂が露光部分とそれ以外の部分とを薬液で除去できるタイプであれば、導電性突起上部とそれ以外の部分の紫外線照射量を変えることで、導電性突起上部の樹脂のみ薬液で除去することができ、研磨なし、又はわずかな研磨で導電性突起上部の頭出しができる。
また、本発明の方法により表面に導電性突起を有する金属箔を用いて半導体パッケージ用基板を製造する場合、表面にある金属箔のシート状部分を選択的にエッチングして回路パターンを形成してもよい。また、金属箔の導電性突起を有する表面の平坦部に半導体チップを搭載し、導電性突起と共に絶縁樹脂中に埋め込んでもよい。また、半導体パッケージ用基板の導電性突起の端面が露出した面又は回路面に、更に半導体パッケージ用基板を積層して、多層構造の半導体パッケージ用基板としてもよい。
【００２１】
本発明の半導体パッケージは、本発明の方法によって作製された半導体パッケージ用基板を用いたものである。例えば、半導体パッケージ用基板の回路パターンを有する面に、半導体チップをダイボンド材等で固定して回路パターンと半導体チップをワイヤーボンディングでボンディングするか、または、半導体チップをフリップチップボンディングして回路パターンと接続する。次いで、半導体パッケージ用基板の半導体チップ搭載面を封止材で封止することにより、半導体パッケージが得られる。
【００２２】
本発明の素子内蔵型の配線板の製造方法では、電子部品を配線板に実装した後、硬化前の流動状のワニス状態にある絶縁樹脂を印刷により塗布して電子部品を埋めこみ、印刷した絶縁樹脂を硬化させて絶縁樹脂層を形成し、絶縁樹脂層の上に配線を設ける。電子部品としては、半導体チップ、受動部品等、特に制限はなく用いられる。配線板としては、本発明の製造方法によって得られる配線板を含む各種の配線板を使用することができる。また、配線板の製造方法と同様に、絶縁樹脂層は、単層としてもよいし、多層絶縁樹脂層としてもよい。使用可能な樹脂は、配線板の製造方法について記載したものと同様である。
例えば、まず、配線板の電子部品実装面に、流動状のワニス状態にある絶縁樹脂（１）を印刷し、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥し、更に、絶縁樹脂（１）と成分が異なり、流動状のワニス状態にある絶縁樹脂（２）及び絶縁樹脂（２）と成分が異なり、流動状のワニス状態にある絶縁樹脂（３）の少なくとも２種類の絶縁樹脂を、この順で、各々、印刷し、流動性はなくなるが、完全な硬化に至るまえの、半硬化状態まで乾燥することにより、絶縁樹脂（１）の層、絶縁樹脂（２）の層及び絶縁樹脂（３）の層の少なくとも３層からなる多層絶縁樹脂層を、電子部品が絶縁樹脂で埋め込まれる厚みに形成する。その後、多層絶縁樹脂層中の全ての絶縁樹脂を同時に完全に硬化させる硬化工程、及び、多層絶縁樹脂層上に配線を設ける工程を行なう。
多層絶縁樹脂層を形成する場合の絶縁樹脂の組み合わせの例も、配線板の製造方法について記載したものと同様である。
【００２３】
【実施例】
以下、本発明の実施例及びその比較例によって本発明を更に具体的に説明するが、本発明はこれらの実施例に限定されるものではない。
【００２４】
実施例１
図に基づいて本発明の一実施例を説明する。図１は導電性突起を有した金属箔への多層樹脂層を形成する各工程における断面を示した図である。図１（ａ）に導電性突起Ａを有した金属箔７と接着性の良い第１樹脂層１を形成する工程を示す。ここで、導電性突起Ａを有する金属箔７は、以下のようにして作製した。厚さ７０μｍの銅層、０．２μｍのニッケル層、１０μｍの銅層からなる３層金属箔（日本電解（株）製）を、フォトドライフィルムＨ−Ｋ３５０（日立化成工業（株）製）を用いてパターンを形成し、メルテックス社製エープロセス液（アンモニア銅錯塩２０〜３０重量％、塩化アンモニウム１０〜２０重量％及びアンモニア１〜１０重量％含有）からなるアルカリエッチング液で７０μｍ銅層を選択的にエッチングして、露出したニッケル層の表面に銅からなる金属柱を形成した。このとき、金属柱はφ２５０μｍの円柱となるようにした。次いで、ニッケル層の金属柱下以外の部分を、硝酸・過酸化水素水溶液からなるエッチング液で選択的に除去することにより、銅及びニッケルからなるφ２５０μｍの円柱状の導電性突起Ａを形成した。露出した１０μｍの銅層表面に、樹脂との密着性を良くするために化学リン系処理を施した。
【００２５】
第１樹脂層１の形成には、シリコーン変性ポリアミドイミド樹脂からなるＫＳ６６００（日立化成工業（株）製）を用いた。流動状のワニス状態の粘度４０Ｐａ・ｓの上記樹脂を、印刷機ＶＥ−５００（東レエンジニアリング（株）製）で印刷した。１８はマスクを、１７はスキージを示す。印刷後、８０℃で３０分、乾燥し流動性がなくなった半硬化状態とし第１樹脂層１を形成した。乾燥後の第１樹脂層１の厚さ（水平部分での厚み；以下同様）は、２０μｍであった。
次に、ＫＳ６６００に無機粒子（二酸化ケイ素）を７５％含有させた樹脂を、流動状のワニス状態で第１樹脂層１の上に印刷した。第１樹脂層１と同様、８０℃で３０分、乾燥し流動性がなくなった半硬化状態の第２樹脂層２を形成した（図１（ｂ）。乾燥後の第２樹脂層２の厚さは３０μｍであった。
図１（ｃ）に示すように、第２樹脂層２の上に、流動状のワニス状態のＫＳ６６００を印刷した。塗布後、８０℃、３０分で乾燥し流動性がなくなった半硬化状態に半硬化し第３樹脂層３とした。乾燥後の第３樹脂層３の厚さは２５μｍであった。
【００２６】
金属箔７に第１樹脂層１、第２樹脂層２及び第３樹脂層３からなる３層の半硬化状態の樹脂層を形成後、図１（ｄ）に示すように、埋め込まれた導電性突起Ａの端面を絶縁樹脂層表面に露出させるため、絶縁樹脂層が半硬化状態のまま、市販用研磨紙で研磨した。研磨時間は、２５０ｍｍｘ２５０ｍｍの金属箔上の絶縁樹脂層表面を＃４００の研磨紙で３０分／枚で研磨することができた。比較として行った絶縁樹脂層を完全に硬化した部材を研磨した場合は、同研磨紙で６０分／枚であった。
図１（ｅ）に示すように、研磨後、１８０℃で３０分間、２２０℃で１０分間加熱して、半硬化状態にある３層の樹脂層を完全に硬化し硬化樹脂層４、５、６とした。
硬化樹脂層を形成した後の半導体パッケージ用の本部材は、樹脂を完全に硬化させた後もそりやうねりがなく平坦であった。また、得られた部材を用いて、金属箔表面（導電性突起と反対面）を、メルテックス社製エープロセス液を用いてエッチングし、回路形成した。その後、回路表面及び導電性突起の露出面に電解ニッケル／金メッキを施すことにより、半導体パッケージ用基板を作製した。得られた半導体パッケージ用基板も同様に平坦であった。また、樹脂層と銅のピール強度も１．２ｋｇ／ｃｍと、無機粒子を高比率（６０重量％）で配合させた樹脂と銅のピール強度０．５ｋｇ／ｃｍに比べ強かった。
【００２７】
実施例２
図２に本実施例の工程の断面図を示す。以下、工程に沿って説明する。
図２（ａ）の、導電性突起Ａを有する金属箔７は、以下のようにして作製した。厚さ１００μｍの銅層、０．２μｍのニッケル層、５μｍの銅層からなる３層金属箔（日本電解（株）製）を、フォトドライフィルムＨ−Ｋ３５０（日立化成工業（株）製）を用いてパターンを形成し、メルテックス社製エープロセス液（アンモニア銅錯塩２０〜３０重量％、塩化アンモニウム１０〜２０重量％及びアンモニア１〜１０重量％含有）からなるアルカリエッチング液で１００μｍ銅層を選択的にエッチングして、露出したニッケル層の表面に銅からなる金属柱を形成した。このとき、金属柱はφ２５０μｍの円柱となるようにした。次いで、ニッケル層の金属柱下以外の部分を、硝酸・過酸化水素水溶液からなるエッチング液で選択的に除去することにより、銅及びニッケルからなるφ２５０μｍの円柱状の導電性突起Ａを形成した。露出した５μｍの銅層表面に、樹脂との密着性を良くするために化学リン系処理を施した。
準備した導電性突起を有する金属箔７にサイズ６．５ｘ６．５ｍｍ、厚さ０．０５０ｍｍの半導体チップ１０を、Ａｌ電極Ｂが導電性突起Ａの形成されていない銅箔面に接するように、ダイボンディングペーストＥＮ−Ｘ５０Ｎ（日立化成工業（株）製）１９を用いて固定した。この際、半導体チップのパッド部にダイボンディングペーストが付着しないようにした。
【００２８】
図２（ｂ）は、実施例１と同様に、シリコーン変性ポリアミドイミド樹脂からなるＫＳ６６００（日立化成工業（株）製）及びこの樹脂と無機粒子からなる樹脂を用いて半硬化状態にある第１樹脂層１、第２樹脂層２及び第３樹脂層３の３層からなる絶縁樹脂層を形成したのち、樹脂が半硬化の状態で研磨を行い、埋め込んだ導電性突起を露出させた後、３層の樹脂を完全に硬化させたときの断面図である。なお、乾燥後の各樹脂層の厚さは、第１樹脂層１が３０μｍ、第２樹脂層２が４０μｍ、第３樹脂層３が３５μｍであった。
図２（ｃ）は、厚さ５μｍの銅層を選択的にエッチングして回路Ｃを形成した形成を行った断面図である。その際、半導体チップ１０搭載部分の銅箔は、チップのパッド部分のみ露出するようにエッチングを行った。
【００２９】
図２（ｄ）に示すのは、露出した半導体チップのＡｌ電極Ｂを、形成した回路Ｃとの接続を行うため、Ａｌ電極Ｂ部分に導電性ペーストのドーデント（ニホンハンダ（株）製）２０を穴埋め印刷し、その後、１８０℃、３０分で硬化させた断面図である。
図２（ｅ）は、実施例１と同様の工程で導電性突起を有した金属箔に３層の半硬化状態の絶縁樹脂層を形成した部材を準備している。
図２（ｆ）は、図２（ｄ）に示す部材に、図２（ｅ）で準備した部材を真空プレス装置により、真空下で加熱圧着した断面図である。加熱することにより半硬化状態の図２（ｃ）の部材の樹脂が一旦軟化し、加圧することにより樹脂が回路間に押し込まれ、図２（ｄ）の部材に接着する。層間の接続は埋め込まれた銅からなる導電性突起Ａと５μｍの銅層から形成した回路Ｃとの間で行っている。
【００３０】
図２（ｆ）の場合、層間の接続は周りの樹脂の接着力で導電性突起Ａと回路Ｃとが接触している状態であるが、より接続信頼性を上げるためには、導電性突起Ａの露出部と回路Ｃとに金めっきを施し、密着性を上げたり、同様箇所に、はんだめっきを施して、プレス接続時又はプレス後にはんだ溶融温度以上に加熱しはんだ接続したり、プレス前に導電性突起Ａの露出部又は回路Ｃの接続部又は両方の部位に導電性接着剤を塗布しておき、プレス時に同時に接着硬化する方法が考えられる。
図２（ｇ）は、加熱圧着した部材の第１樹脂層１、第２樹脂層２及び第３樹脂層３からなる絶縁樹脂層を完全に硬化して、硬化樹脂層１、硬化樹脂層２及び硬化樹脂層３からなる層とした後の断面図である。
硬化後、電解ニッケル／金めっき（大和電機工業（株）製）を行い図２（ｇ）に示すような断面構造を持つ半導体チップが内蔵された半導体パッケージ用基板を作製した。
【００３１】
実施例３
図３に本実施例を行った工程の断面図を示す。ベース基板として、ガラスエポキシ基材１４を絶縁層とする両面配線板を作製し（図３（ａ））、この両面配線板の配線８上に端子部に金バンプ９を備えるＬＳＩ素子１０（厚み５０μｍ）を搭載して、金バンプ９と配線８とを、熱圧着により相互接続させた（図３（ｂ））。このようにして作製された組み立て体を、実施例１と同様にして、シリコーン変性ポリアミドイミド樹脂からなるＫＳ６６００（日立化成工業（株）製）を及びこの樹脂と無機充填材とからなる樹脂を用いて半硬化状態にある第１樹脂層１、第２樹脂層２及び第３樹脂層３からなる３層の絶縁樹脂層を形成した（図３（ｃ））。なお、乾燥後の各樹脂層のソルダーレジスト１２上の厚さは、第１樹脂層１が４０μｍ、第２樹脂層２が６０μｍ、第３樹脂層３が４０μｍであった。半硬化させた後、研磨を行い、ついで、絶縁樹脂層の樹脂を完全に硬化させた。
研磨及び完全硬化して表面が平坦な絶縁樹脂層を形成後、層間接続用のビアをあけ無電解銅めっきを用いたアディティブ法により多層配線を形成し、その上にソルダーレジスト１２を形成して配線パターン１１を形成した（図３（ｄ））。その後、形成した配線パターン１１上に、金バンプ９を備えるＬＳＩ素子１０を搭載して、金バンプ９と配線パターン１１とを、熱圧着により相互接続させ、ＬＳＩ素子１０とソルダーレジスト１２との間には液状エポキシ樹脂（アンダーフィル材）１３をフィルして硬化させ、素子内蔵型３次元半導体パッケージを得た（図３（ｅ））。
【００３２】
【発明の効果】
本発明では、金属箔や配線板用の部材、半導体パッケージ用基板に、特に凹凸のある場合に、密着性の良い樹脂層を、そりやうねりを発生させずに形成することができる。また、該部材を用いて平坦な半導体パッケージや配線板を提供することができる。
【図面の簡単な説明】
【図１】本発明の方法により、導電性突起を有した金属箔に樹脂層を形成する工程の断面図。
【図２】本発明の方法により、導電性突起有した金属箔に半導体チップを埋め込んだ後、樹脂層を形成する工程、及び半導体チップを埋め込んだ後、半導体パッケージ用基板とする工程の断面図。
【図３】本発明の方法を、複数の半導体チップを内蔵した３次元半導体パッケージの製造方法に適用する工程の断面図。
【符号の説明】
１　第１樹脂層
２　第２樹脂層
３　第３樹脂層
４　硬化第１樹脂層
５　硬化第２樹脂層
６　硬化第３樹脂層
７　導電性突起を有した金属箔
Ａ　導電性突起
８　配線
９　金バンプ
１０　半導体チップ（ＬＳＩ素子）
Ｂ　Ａｌ電極
Ｃ　回路
１１　アディティブ法により形成した配線パターン
１２　ソルダーレジスト
１３　アンダーフィル材
１４　ガラスエポキシ基材
１５　スルーホールめっき接続部
１６　ニッケル／金めっきパッド
１７　スキージ
１８　マスク
１９　ダイボンディングペースト
２０　導電性ペースト[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a wiring board, a substrate for a semiconductor package, a semiconductor package, and a method for manufacturing the same.
[0002]
[Prior art]
With the demand for miniaturization and high performance of electronic devices, the degree of integration of semiconductors has been improving year by year and the number of input / output terminals has been increasing. Along with this, a semiconductor package on which a semiconductor is mounted also requires many input / output terminals, and at the same time, miniaturization is also required, so that high density is being promoted. As a semiconductor package that meets such requirements, a lead frame type SOP (Small Outline Package) or a QFP (Quad Flat Package) in which terminals can be arranged only in a conventional peripheral area, and a BGA (Ball) in which terminals can be arranged on a surface are used. Grid Array). Recently, a CSP (Chip Size Package) having almost the same size as the outer shape of a chip has been developed and used in a field where a smaller semiconductor package is required. These BGAs and CSPs use a wiring substrate called an interposer as a substrate on which a chip is mounted, and a smaller, higher-density, and lower-cost wiring substrate for a semiconductor package is desired.
[0003]
As an example of a wiring board that satisfies such requirements, a connection terminal conductor, a resin filling between the connection terminal conductors, and a surface on which the connection terminal is mounted, as reported in JP-A-2002-043467. And a wiring board made of a circuit conductor provided on the opposite surface.
On the other hand, in recent years, in order to further improve the integration degree of a semiconductor package, an MCP (Multi Chip Package) in which a plurality of chips are packaged in one package has been developed, and a conventional board called SIP (System In Package) has been developed. Attempts have been made to realize the system realized by using a single package. As a method of forming such a package, there is a method of connecting a chip and a wiring board, filling the chip with a resin, forming wiring thereon, and stacking the wiring.
Under the circumstances as described above, in recent years, the number of steps of filling an uneven member or intermediate with an insulating resin is increasing. However, in semiconductor packages and wiring boards in which inorganic and organic substances are complexly combined, the adhesiveness between different materials such as resin and copper wiring and semiconductor chips is important, and at the same time, high flatness without warpage or undulation Is required.
[0004]
[Problems to be solved by the invention]
However, when a resin sheet is formed by pressing a resin sheet as a method of forming the resin layer, there is a problem of the ability of the resin to follow the above-mentioned uneven member. Further, when burying the chip, there is a concern that the chip may be broken due to the pressure applied to the chip.
The present invention proposes a method for easily forming a resin layer on an uneven member used for manufacturing a semiconductor package substrate or another wiring board. Usually, when a resin layer is formed on a wiring member, particularly a member having conductive protrusions, when an uncured resin is applied and cured, the resin contracts or due to a difference in thermal expansion between the member and the resin. Warpage and swell occur. Further, as a method of suppressing warpage and undulation, there is a method of using a low shrinkage resin in which inorganic particles are blended in a high ratio, but this method has a problem that the adhesiveness between the resin and the member is deteriorated. The present invention further provides a method for forming a resin layer having good adhesiveness and preventing warpage or undulation, in addition to the method for forming a resin layer.
[0005]
[Means for Solving the Problems]
The present invention provides: 1. a substrate for a semiconductor package, a wiring board, which is manufactured by forming a resin layer on a metal foil having conductive protrusions and then exposing the conductive protrusions by polishing; 2. a substrate for a semiconductor package, a wiring board, which is manufactured by forming a resin layer on a wiring member made of a conductor having conductive protrusions and an insulating resin, and then exposing the conductive protrusions by polishing; A method of forming a resin layer on a semiconductor package with a built-in element or a wiring board, in which a chip or a passive component is mounted on a wiring board and then buried with a resin, a resin layer is formed, and wiring is provided thereon. A method of applying a resin in a varnish state by printing and curing the resin is proposed.
[0006]
That is, the present invention relates to the following (1) to (21).
(1) A printing process in which an insulating resin in a fluid varnish state before curing is applied to a wiring member having a plurality of conductive protrusions on its surface by printing to a thickness at which the conductive protrusions are embedded with the insulating resin. A method for manufacturing a wiring board, comprising: a curing step of curing the insulating resin thus formed; and a polishing step of polishing the insulating resin to expose the tips of the conductive protrusions.
(2) The method for manufacturing a wiring board according to (1), wherein the wiring board is a substrate for a semiconductor package.
(3) The method for manufacturing a wiring board according to (1) or (2), wherein the wiring member is a metal foil having a plurality of conductive protrusions on a surface.
(4) The wiring member according to (1) or (2), wherein the wiring member has an insulating resin layer, a conductor layer connected between layers on both surfaces of the insulating resin layer, and a conductive protrusion on at least one surface of the insulating resin layer. Manufacturing method of wiring board.
(5) The method for producing a wiring board according to any one of (1) to (4), wherein a polishing step is performed after the curing step.
[0007]
(6) A printing process in which an insulating resin in a fluid varnish state before curing is applied to a wiring member having a plurality of conductive protrusions on its surface by printing to a thickness such that the conductive protrusions are embedded with the insulating resin. The drying process of drying the semi-cured insulating resin to a semi-cured state before it is completely cured, but polishing the semi-cured insulating resin to expose the tips of the conductive protrusions. The method for producing a wiring board according to any one of (1) to (4), including a curing step of completely curing the insulating resin after the polishing step.
(7) The insulating resin (1) in a fluid varnish state is printed on the surface of the wiring member having the conductive protrusions, and although the fluidity is lost, the resin is dried to a semi-cured state before complete curing. Further, at least the insulating resin (2) having a different component from the insulating resin (1) and being in a fluid varnish state and having a different component from the insulating resin (2) and being in a fluid varnish state. The two types of insulating resin are printed in this order, and the fluidity is lost. However, by drying to a semi-cured state before complete curing, the layer of the insulating resin (1), the insulating resin ( Forming a multilayer insulating resin layer comprising at least three layers of the layer 2) and the layer of the insulating resin (3) to a thickness such that the conductive protrusions are embedded with the insulating resin; Curing process to completely cure at the same time, and multi-layer The method for manufacturing a wiring board according to any one of (1) to (4), further comprising a polishing step of polishing the insulating resin layer to expose the tips of the conductive protrusions.
[0008]
(8) The method for manufacturing a wiring board according to (7), wherein the curing step is performed after the polishing step.
(9) In the step of forming the multilayer insulating resin layer, an insulating resin having good adhesion to the wiring member is used as the insulating resin (1), and a second insulating resin (2) and an insulating resin (3) are included. The method of manufacturing a wiring board according to (7) or (8), wherein an insulating resin having a characteristic of reducing warpage of the manufactured wiring board is used for at least one layer.
(10) In the step of laminating the resin in a semi-cured state according to (7) or (8), a resin having a different content of inorganic or organic particles, or a resin having a different basic resin structure is printed at an arbitrary position by printing. A method of forming a resin layer in which resins having different properties are mixed in an arbitrary portion in an insulating resin by forming the resin into a shape and a thickness, and then laminating the resin.
(11) A wiring board manufactured by the method according to any one of (1) to (10).
(12) A substrate for a semiconductor package manufactured by the method according to any one of (1) to (10).
(13) A semiconductor package using the semiconductor package substrate according to (12).
[0009]
(14) A method of manufacturing a wiring board with a built-in element, comprising: mounting an electronic component on a wiring board, filling the electronic component with an insulating resin, forming an insulating resin layer, and providing wiring on the insulating resin layer. After mounting on a wiring board, an insulating resin in a fluid varnish state before curing is applied by printing to embed an electronic component, and the printed insulating resin is cured to form an insulating resin layer. Production method.
(15) The method according to (14), wherein the electronic component is a semiconductor chip, and the wiring board with a built-in element is a semiconductor package with a built-in element.
(16) The insulating resin (1) in a fluid varnish state is printed on the electronic component mounting surface of the wiring board, and although the fluidity is lost, it is dried to a semi-cured state before complete curing, and And at least two types of insulating resin (2) having a different component from the insulating resin (1) and being in a fluid varnish state and having a different component from the insulating resin (2) and being in a fluid varnish state. The insulating resin is printed in this order, and the fluidity is lost. However, by drying to a semi-cured state before complete curing, the layer of the insulating resin (1), the insulating resin (2) Forming a multilayer insulating resin layer composed of at least three layers of the first resin layer and the insulating resin (3) to a thickness at which the electronic component is embedded with the insulating resin. Curing process to cure, and multi-layer insulating resin The method for manufacturing a wiring board according to (14) or (15), comprising a step of providing wiring on the layer.
(17) The method according to (16), wherein after the step of forming the multilayer insulating resin layer, a hardening step is performed after the surface of the multilayer insulating resin layer is polished flat.
[0010]
(18) In the step of forming a multilayer insulating resin layer, an insulating resin having good adhesion to a wiring board and an electronic component is used as the insulating resin (1), and the layer of the insulating resin (2) and the layer of the insulating resin (3) are formed. The method for manufacturing a wiring board according to any one of (16) to (18), wherein an insulating resin having a characteristic of reducing warpage of the manufactured wiring board with a built-in element is used for the second layer or more including the second layer.
(19) In the step of laminating the resin in a semi-cured state according to any one of (16) to (18), a resin having a different content of inorganic or organic particles or a resin having a different basic resin structure is optionally printed by printing. A method of forming a resin layer in which resins having different properties are mixed at an arbitrary position in an insulating resin by forming the resin in a position, a shape, and a thickness, and then laminating the resin.
(20) A wiring board with a built-in element manufactured by the method according to any one of (14) to (19).
(21) A semiconductor package with a built-in element manufactured by the method according to any one of (14) to (19).
[0011]
In addition, as a method for forming the resin layer, 1) an insulating resin having good adhesiveness to the wiring member is applied thinly in a fluid varnish state before curing, and after the application, the fluidity is lost, but the resin is not completely cured. Step of drying into a cured state to form a first layer; 2) Uncured resin blended from the first resin layer in a semi-cured state without fluidity so as not to generate warpage or undulation. A step of applying in a liquid state in a varnish state and similarly drying to a semi-cured state in which fluidity is lost to form a second layer; 3) the same or different resin as the first layer in order to balance the resin layer Is applied on the second layer in a fluid varnish state, and after the application, is dried to a semi-cured state where fluidity is lost to form a third layer. 4) All the resin layers in the semi-cured state are A process for curing the whole to a completely cured state is provided.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
The method for manufacturing a wiring board according to the present invention is a method for manufacturing a wiring member having a plurality of conductive protrusions on a surface, by printing an insulating resin in a fluid varnish state before curing, by printing, and by embedding the conductive protrusions in the insulating resin. And a curing step of curing the printed insulating resin, and a polishing step of polishing the insulating resin to expose the tips of the conductive protrusions.
Examples of the wiring board manufactured by the method of the present invention include other wiring boards such as a semiconductor package substrate as an interposer used for a semiconductor package, and a motherboard on which a semiconductor package and other electronic components are mounted.
Examples of the wiring member having a plurality of conductive protrusions on the surface used in the present invention include the following.
[0013]
1. Metal foil having conductive protrusions on its surface. For example, a three-layer metal foil in which the first and third metal layers are different from the second metal layer in etching conditions is used as the first metal layer is formed into a columnar bump by etching using a dry film resist. The metal foil and the three-layered metal foil are etched using a dry film resist to form a first metal layer into a columnar bump, and then a second metal layer is formed into a third metal bump except for the lower part of the columnar bump. There is a metal foil etched away until the metal layer is exposed. When the first and third metal layers at this time are copper and copper alloy, the second metal layer includes nickel, nickel alloy, titanium, chromium, tin, zinc, and the like.
2. A wiring member made of a conductor having conductive protrusions and an insulating resin. For example, a wiring member having an insulating resin layer, a conductor layer connected between layers on both surfaces of the insulating resin layer, and a conductive protrusion on at least one surface of the insulating resin layer. For example, although the resin layer is formed by exposing the end face of the columnar bump to the metal foil, the three-layer metal foil is heat-pressed to the resin layer forming surface, and then the first metal layer is similarly formed with the columnar bump. There is something. In addition, a conductive paste such as silver paste is printed on the surface of a common double-sided wiring board to form conductive protrusions, and a metal resist is formed by plating deposition using a plating resist or the like. .
3. An intermediate member in a semiconductor package with a built-in element or a wiring board.
[0014]
Examples of the insulating resin used in the present invention include thermosetting resins such as polyimide resin, polyamide imide resin, silicone resin, phenol resin, bismaleimide triazine resin, epoxy resin, acrylic resin, polyphenylene sulfide resin, and photosensitive polyimide resin. , An acrylic epoxy resin, a thermoplastic elastomer such as ethylene, propylene, styrene, butadiene, and a liquid crystal polymer. Further, those obtained by blending organic particles or inorganic particles with these resins can also be used. Examples of the organic particles that can be blended with the resin include cured products of the aforementioned resins, and examples of the inorganic particles include alumina particles, silicon dioxide (silica), and glass fibers. The organic or inorganic particles preferably have an average particle size of 0.1 to 20 μm.
In the present invention, the insulating resin in a fluid varnish state before curing is applied by printing to the surface of the wiring member having the conductive protrusions to a thickness at which the conductive protrusions are embedded with the insulating resin. The insulating resin in the fluid varnish state preferably has a viscosity of 3 to 70 Pa · s during printing. As a printing method, a screen printing method using a mesh screen mask, a metal mask, and the like, and a method of applying a resin to a uniform thickness by using a squeegee, a blade, or the like directly on a wiring member with a gap or a gap. After applying the resin to a drum or a board, there is a method of transferring the resin onto a wiring member. Further, a method of performing these operations under vacuum is also effective for eliminating unfilled portions.
[0015]
After the printing step, the polishing step may be performed after the curing step. Further, a curing step may be performed after the polishing step. In this case, before the polishing step, the edge resin is subjected to a drying step of drying to a semi-cured state before fluidity is lost, but before complete curing, and then the insulating resin dried to a semi-cured state is removed. A polishing step for polishing to expose the tip of the conductive projection is performed, and then a curing step for completely curing the insulating resin is performed. In the latter method, the polishing efficiency is improved because the resin is softer than the completely cured resin.
[0016]
The overall amount of warpage can be controlled by changing the composition of the resin in each layer, the type of resin, the thickness, or the number of layers according to the wiring member forming the insulating resin layer. As the insulating resin, a single resin layer may be formed by using only one kind, or two or more kinds of insulating resins, including those obtained by changing the filling ratio of a filler or the like to a resin having the same composition, May be used to form a multilayer insulating resin layer. When a multi-layer insulating resin layer is used, a resin having a good adhesiveness can be obtained by selecting the resin of the first layer according to the type and surface condition of the member.
For example, the insulating resin (1) in a fluid varnish state is printed on the surface of the wiring member having the conductive protrusions, and although the fluidity is lost, it is dried to a semi-cured state before complete curing, Furthermore, at least two of the insulating resin (2) and the insulating resin (3) which have different components from the insulating resin (1) and are in the fluid varnish state and have different components from the insulating resin (2) in the fluid varnish state. Each kind of insulating resin is printed in this order, and the fluidity is lost, but by drying to a semi-cured state before complete curing, the layer of the insulating resin (1), the insulating resin (2) ) And at least three layers of the insulating resin (3) are formed to a thickness such that the conductive protrusions are embedded in the insulating resin. Thereafter, a curing step is performed before or after the polishing step, and all the insulating resins in the multilayer insulating resin layer are simultaneously completely cured.
[0017]
Preferably, 1) an insulating resin having good adhesion to the wiring member is applied thinly in a fluid varnish state before curing, and after application, dried to a semi-cured state in which fluidity is lost but not completely cured. Step of forming the first layer, 2) An uncured, varnished liquid insulating resin blended from the first resin layer in a semi-cured state without fluidity so as not to generate warpage or undulation Step of applying as it is and similarly drying to a semi-cured state where fluidity is lost to form a second layer. 3) In order to balance the multilayer insulating resin layer, the same or different insulating resin as the first layer is used for the second layer. A multi-layer insulating resin layer is formed by applying a fluid varnish state on the two layers, drying the semi-cured state after the application, and forming a third layer. Next, before or after the polishing step, 4) a step of collectively curing all the resin layers in the semi-cured state to a completely cured state is performed.
[0018]
Generally, in order to make the resin have low shrinkage and low thermal expansion, inorganic particles are blended in a high ratio, but in this case, the adhesive force between the resin and the member is reduced. Therefore, the first layer at the bonding interface is a resin layer containing no or a small amount of inorganic particles, for example, 1 to 20% by weight in the insulating resin, and the second layer has a high ratio of inorganic particles to the first layer, for example, insulating. A resin layer is blended in an amount of more than 20% by weight and 90% by weight or less in the resin. This makes it possible to form a resin layer with low shrinkage and low thermal expansion with good adhesiveness. When the multilayer insulating resin layer has a three-layer structure, it is preferable to use the same insulating resin as the first layer for the third layer.
In addition, the present invention is a resin containing a large amount of filler components such as inorganic and organic particles, is printed and dried through a stencil mask provided with an arbitrary opening, and by repeatedly printing and drying, the inorganic resin in the insulating resin, It can also be used as a method of mixing the organic particle component at an arbitrary position. At this time, it is desirable to use the same resin in order to improve the adhesion reliability between the respective layers.
[0019]
Examples of the polishing method in the polishing step include roll paper polishing, sand blasting, honing, lapping, and the like, and a mechanical processing method using a blade, such as router processing, may be used. Polishing the insulating resin in a semi-cured state has a lower hardness than the cured state, so that the polishing efficiency can be increased.
The semi-cured state of the resin described herein refers to a state of the resin that has lost its fluidity and has been cured to a polished state and has not yet been completely cured. The thermosetting resin is called a B-stage state, and generally varies depending on the resin, but generally has a curing rate of 30 to 80%. This curing rate can be measured by DSC (differential scanning calorimetry). When the insulating resin is a thermosetting resin, the drying of the insulating resin to a semi-cured state and the complete curing are performed by heating, and when the insulating resin is returned to room temperature (5 to 35 ° C.) during polishing, there is no fluidity. When an external force is applied, elastic deformation or plastic deformation occurs.When the external pressure is removed, the elastic deformation returns to the original state, and when plastic deformation occurs, the deformed state is maintained in a polished state. is there.
In the case of a solvent-diluted type thermoplastic material, a semi-cured state can be obtained by appropriately removing the solvent component. As a method of removing the solvent, there is a method of heating or reducing the pressure. Like a thermosetting resin, a state that can be polished means that there is no fluidity, elastic deformation or plastic deformation occurs when an external force is applied, and when external pressure is removed, the state returns to the original state in the case of elastic deformation, plastic deformation If so, the state is such that the deformed state is maintained.
[0020]
When a photosensitive resin such as a photosensitive polyimide is used, the amount of curing can be controlled by the amount of ultraviolet irradiation. In the case of a photosensitive resin, the upper portion of the conductive protrusion is prevented from being exposed to ultraviolet light by masking or the like, the amount of ultraviolet light irradiation is reduced from the amount of ultraviolet light irradiation of portions other than the conductive protrusion portion, and the upper portion of the conductive protrusion is not exposed to other light. By setting the part in an uncured state, the upper portion of the conductive protrusion can be polished more concentratedly, and the polishing efficiency can be increased. Further, if the photosensitive resin is of a type that can remove the exposed portion and the other portion with a chemical solution, by changing the amount of ultraviolet irradiation on the conductive protrusion and the other portion, only the resin on the conductive protrusion can be removed. It can be removed with a chemical solution, and the top of the conductive projection can be caught without polishing or with slight polishing.
When a semiconductor package substrate is manufactured using a metal foil having conductive protrusions on the surface according to the method of the present invention, a circuit pattern is formed by selectively etching a sheet-like portion of the metal foil on the surface. Is also good. Alternatively, a semiconductor chip may be mounted on a flat portion of a surface of a metal foil having conductive protrusions, and may be embedded in an insulating resin together with the conductive protrusions. Further, a semiconductor package substrate may be further laminated on the surface or the circuit surface of the semiconductor package substrate where the end faces of the conductive protrusions are exposed, to obtain a semiconductor package substrate having a multilayer structure.
[0021]
The semiconductor package of the present invention uses the semiconductor package substrate manufactured by the method of the present invention. For example, a semiconductor chip is fixed to a surface having a circuit pattern of a semiconductor package substrate with a die bonding material or the like, and the circuit pattern and the semiconductor chip are bonded by wire bonding, or the semiconductor chip is flip-chip bonded to the circuit pattern. Connecting. Next, a semiconductor package is obtained by sealing the semiconductor chip mounting surface of the semiconductor package substrate with a sealing material.
[0022]
In the method for manufacturing a wiring board with a built-in element of the present invention, after mounting the electronic component on the wiring board, the insulating resin in a fluid varnish state before curing is applied by printing to embed the electronic component, and the printed insulation is The resin is cured to form an insulating resin layer, and wiring is provided on the insulating resin layer. As the electronic component, a semiconductor chip, a passive component, or the like is used without any particular limitation. As the wiring board, various wiring boards including the wiring board obtained by the manufacturing method of the present invention can be used. Further, similarly to the method of manufacturing a wiring board, the insulating resin layer may be a single layer or a multilayer insulating resin layer. Usable resins are the same as those described for the method of manufacturing a wiring board.
For example, first, the insulating resin (1) in a fluid varnish state is printed on the electronic component mounting surface of the wiring board, and although the fluidity is lost, it is dried to a semi-cured state before complete curing, Furthermore, at least two of the insulating resin (2) and the insulating resin (3) which have different components from the insulating resin (1) and are in the fluid varnish state and have different components from the insulating resin (2) in the fluid varnish state. Each kind of insulating resin is printed in this order, and the fluidity is lost, but by drying to a semi-cured state before complete curing, the layer of the insulating resin (1), the insulating resin (2) ) And at least three layers of the insulating resin (3) are formed to a thickness such that the electronic component is embedded with the insulating resin. After that, a curing step of completely curing all the insulating resins in the multilayer insulating resin layer simultaneously and a step of providing wiring on the multilayer insulating resin layer are performed.
The example of the combination of the insulating resins when forming the multilayer insulating resin layer is the same as that described for the method of manufacturing the wiring board.
[0023]
【Example】
Hereinafter, the present invention will be described more specifically with reference to Examples of the present invention and Comparative Examples thereof, but the present invention is not limited to these Examples.
[0024]
Example 1
An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a cross section in each step of forming a multilayer resin layer on a metal foil having conductive protrusions. FIG. 1A shows a process of forming the metal foil 7 having the conductive protrusions A and the first resin layer 1 having good adhesiveness. Here, the metal foil 7 having the conductive protrusions A was produced as follows. A three-layer metal foil (manufactured by Nippon Electrolysis Co., Ltd.) consisting of a copper layer having a thickness of 70 μm, a nickel layer having a thickness of 0.2 μm, and a copper layer having a thickness of 10 μm, and a photo dry film H-K350 (manufactured by Hitachi Chemical Co., Ltd.) were used. A 70 μm copper layer was formed with an alkaline etching solution comprising an A process solution manufactured by Meltex Co. (containing 20 to 30% by weight of an ammonia copper complex salt, 10 to 20% by weight of ammonium chloride and 1 to 10% by weight of ammonia). By selective etching, a metal column made of copper was formed on the exposed surface of the nickel layer. At this time, the metal column was made a φ250 μm column. Then, portions other than the portions below the metal pillars of the nickel layer were selectively removed with an etching solution composed of an aqueous solution of nitric acid and hydrogen peroxide, thereby forming cylindrical conductive projections A of φ250 μm composed of copper and nickel. The exposed surface of the copper layer having a thickness of 10 μm was subjected to a chemical phosphorus treatment in order to improve the adhesion to the resin.
[0025]
For the formation of the first resin layer 1, KS6600 (manufactured by Hitachi Chemical Co., Ltd.) made of a silicone-modified polyamide-imide resin was used. The above resin having a viscosity of 40 Pa · s in a fluid varnish state was printed by a printing machine VE-500 (manufactured by Toray Engineering Co., Ltd.). Reference numeral 18 denotes a mask, and 17 denotes a squeegee. After printing, the first resin layer 1 was formed by drying at 80 ° C. for 30 minutes to be in a semi-cured state in which fluidity was lost. The thickness of the first resin layer 1 after drying (the thickness at the horizontal portion; the same applies hereinafter) was 20 μm.
Next, a resin containing 75% of inorganic particles (silicon dioxide) in KS6600 was printed on the first resin layer 1 in a fluid varnish state. Similarly to the first resin layer 1, the second resin layer 2 in a semi-cured state was dried at 80 ° C. for 30 minutes and became non-flowable (FIG. 1 (b). Thickness of the dried second resin layer 2) The length was 30 μm.
As shown in FIG. 1C, KS6600 in a fluid varnish state was printed on the second resin layer 2. After the application, the coating was dried at 80 ° C. for 30 minutes and semi-cured to a semi-cured state in which the fluidity was lost, thereby forming a third resin layer 3. The thickness of the third resin layer 3 after drying was 25 μm.
[0026]
After forming a three-layer semi-cured resin layer composed of the first resin layer 1, the second resin layer 2, and the third resin layer 3 on the metal foil 7, as shown in FIG. In order to expose the end face of the protruding projection A to the surface of the insulating resin layer, the insulating resin layer was polished with a commercially available abrasive paper in a semi-cured state. The polishing time was such that the surface of the insulating resin layer on the metal foil of 250 mm × 250 mm could be polished with # 400 abrasive paper at 30 minutes / sheet. As a comparison, when the member obtained by completely curing the insulating resin layer was polished, the polishing paper was used for 60 minutes / sheet.
As shown in FIG. 1 (e), after the polishing, the three resin layers in the semi-cured state are completely cured by heating at 180 ° C. for 30 minutes and at 220 ° C. for 10 minutes to completely cure the cured resin layers 4, 5,. 6.
The member for a semiconductor package after the formation of the cured resin layer was flat without warping or undulation even after the resin was completely cured. Using the obtained member, the surface of the metal foil (the surface opposite to the conductive protrusions) was etched using an A process liquid manufactured by Meltex Co., Ltd. to form a circuit. Thereafter, a semiconductor package substrate was manufactured by applying electrolytic nickel / gold plating to the circuit surface and the exposed surface of the conductive protrusion. The obtained substrate for a semiconductor package was also flat. Further, the peel strength between the resin layer and copper was 1.2 kg / cm, which was higher than the peel strength between resin and copper in which inorganic particles were blended in a high ratio (60% by weight) of 0.5 kg / cm.
[0027]
Example 2
FIG. 2 shows a cross-sectional view of the process of this embodiment. Hereinafter, the process will be described.
The metal foil 7 having the conductive protrusions A in FIG. 2A was manufactured as follows. A three-layer metal foil (manufactured by Nippon Electrolysis Co., Ltd.) consisting of a copper layer having a thickness of 100 μm, a nickel layer having a thickness of 0.2 μm, and a copper layer having a thickness of 5 μm, and a photo dry film H-K350 (manufactured by Hitachi Chemical Co., Ltd.) were used. A 100 μm copper layer was formed with an alkali etching solution composed of an A process solution manufactured by Meltex Co., Ltd. (containing 20 to 30% by weight of an ammonia copper complex salt, 10 to 20% by weight of ammonium chloride and 1 to 10% by weight of ammonia). By selective etching, a metal column made of copper was formed on the exposed surface of the nickel layer. At this time, the metal column was made a φ250 μm column. Then, portions other than the portions below the metal pillars of the nickel layer were selectively removed with an etching solution composed of an aqueous solution of nitric acid and hydrogen peroxide, thereby forming cylindrical conductive projections A of φ250 μm composed of copper and nickel. The exposed surface of the copper layer having a thickness of 5 μm was subjected to a chemical phosphorus treatment in order to improve the adhesion to the resin.
A semiconductor chip 10 having a size of 6.5 × 6.5 mm and a thickness of 0.050 mm is placed on the prepared metal foil 7 having conductive protrusions so that the Al electrode B is in contact with the copper foil surface on which the conductive protrusions A are not formed. Die bonding paste EN-X50N (manufactured by Hitachi Chemical Co., Ltd.) 19 was used for fixing. At this time, the die bonding paste was prevented from adhering to the pad portion of the semiconductor chip.
[0028]
FIG. 2 (b) shows, similarly to Example 1, a KS6600 (manufactured by Hitachi Chemical Co., Ltd.) made of a silicone-modified polyamide-imide resin and a first semi-cured state using a resin made of this resin and inorganic particles. After forming an insulating resin layer composed of three layers of the resin layer 1, the second resin layer 2, and the third resin layer 3, the resin is polished in a semi-cured state to expose the embedded conductive protrusions. It is sectional drawing when three layers of resin are completely hardened. The thickness of each resin layer after drying was 30 μm for the first resin layer 1, 40 μm for the second resin layer 2, and 35 μm for the third resin layer 3.
FIG. 2C is a cross-sectional view of a circuit C formed by selectively etching a 5 μm-thick copper layer. At this time, the copper foil on the mounting portion of the semiconductor chip 10 was etched so that only the pad portion of the chip was exposed.
[0029]
FIG. 2D shows that in order to connect the exposed Al electrode B of the semiconductor chip to the formed circuit C, a conductive paste dodent (manufactured by Nihon Handa Co., Ltd.) 20 is provided on the Al electrode B portion. FIG. 4 is a cross-sectional view in which fill-in printing is performed, and then cured at 180 ° C. for 30 minutes.
FIG. 2E shows a member prepared by forming three semi-cured insulating resin layers on a metal foil having conductive protrusions in the same process as in Example 1.
FIG. 2F is a cross-sectional view in which the member prepared in FIG. 2E is heat-pressed under a vacuum to the member shown in FIG. By heating, the resin of the member of FIG. 2C in a semi-cured state is once softened, and by applying pressure, the resin is pushed between the circuits and adheres to the member of FIG. 2D. The connection between the layers is made between the conductive protrusion A made of embedded copper and the circuit C formed of a 5 μm copper layer.
[0030]
In the case of FIG. 2 (f), the connection between the layers is in a state in which the conductive protrusion A and the circuit C are in contact with each other by the adhesive force of the surrounding resin. A gold plating is applied to the exposed portion of A and the circuit C to improve adhesion, or a similar portion is subjected to solder plating, and is heated to a solder melting temperature or more at the time of press connection or after the press to perform solder connection, or before the press. A method in which a conductive adhesive is applied to the exposed portion of the conductive protrusion A or the connection portion of the circuit C, or both portions, and the adhesive is cured at the same time as pressing is considered.
FIG. 2 (g) shows that the insulating resin layer composed of the first resin layer 1, the second resin layer 2 and the third resin layer 3 of the thermocompression-bonded member is completely cured, and the cured resin layer 1 and the cured resin layer 2 are cured. FIG. 3 is a cross-sectional view after a layer made of a cured resin layer 3 is formed.
After curing, electrolytic nickel / gold plating (manufactured by Daiwa Electric Industry Co., Ltd.) was performed to produce a semiconductor package substrate incorporating a semiconductor chip having a cross-sectional structure as shown in FIG. 2 (g).
[0031]
Example 3
FIG. 3 shows a cross-sectional view of a step in which this embodiment is performed. As a base substrate, a double-sided wiring board having a glass epoxy base material 14 as an insulating layer is manufactured (FIG. 3A), and an LSI element 10 having a gold bump 9 at a terminal portion on a wiring 8 of the double-sided wiring board (thickness). 50 μm), and the gold bumps 9 and the wirings 8 were interconnected by thermocompression bonding (FIG. 3B). The assembly thus produced was used in the same manner as in Example 1 using KS6600 (manufactured by Hitachi Chemical Co., Ltd.) made of a silicone-modified polyamideimide resin and a resin made of this resin and an inorganic filler. Thus, three insulating resin layers composed of the first resin layer 1, the second resin layer 2, and the third resin layer 3 in a semi-cured state were formed (FIG. 3C). The thickness of each resin layer on the solder resist 12 after drying was 40 μm for the first resin layer 1, 60 μm for the second resin layer 2, and 40 μm for the third resin layer 3. After semi-curing, polishing was performed, and then the resin of the insulating resin layer was completely cured.
After polishing and complete curing to form an insulating resin layer having a flat surface, a via for interlayer connection is opened, a multilayer wiring is formed by an additive method using electroless copper plating, and a solder resist 12 is formed thereon. The wiring pattern 11 was formed (FIG. 3D). Thereafter, the LSI element 10 having the gold bump 9 is mounted on the formed wiring pattern 11, and the gold bump 9 and the wiring pattern 11 are interconnected by thermocompression bonding, and the space between the LSI element 10 and the solder resist 12 is formed. Then, a liquid epoxy resin (underfill material) 13 was filled and cured to obtain a three-dimensional semiconductor package with a built-in element (FIG. 3E).
[0032]
【The invention's effect】
According to the present invention, a resin layer having good adhesiveness can be formed on a metal foil, a member for a wiring board, or a substrate for a semiconductor package, especially when there is unevenness, without causing warpage or undulation. Further, a flat semiconductor package or a wiring board can be provided by using the member.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a step of forming a resin layer on a metal foil having conductive protrusions by the method of the present invention.
FIG. 2 is a cross-sectional view of a step of forming a resin layer after embedding a semiconductor chip in a metal foil having conductive protrusions, and a step of forming a semiconductor package substrate after embedding the semiconductor chip by the method of the present invention. .
FIG. 3 is a cross-sectional view of a step of applying the method of the present invention to a method of manufacturing a three-dimensional semiconductor package having a plurality of built-in semiconductor chips.
[Explanation of symbols]
1 First resin layer
2 Second resin layer
3 Third resin layer
4 first cured resin layer
5 cured second resin layer
6 cured third resin layer
7 Metal foil with conductive protrusions
A Conductive protrusion
8 Wiring
9 Gold Bump
10 Semiconductor chip (LSI element)
B Al electrode
C circuit
11 Wiring pattern formed by additive method
12 Solder resist
13 Underfill material
14 Glass epoxy base material
15 Through-hole plating connection
16 Nickel / gold plated pad
17 Squeegee
18 Mask
19 Die bonding paste
20 conductive paste

Claims

A printing step of applying an insulating resin in a fluid varnish state before curing to a wiring member having a plurality of conductive protrusions on its surface by printing to a thickness at which the conductive protrusions are embedded with the insulating resin, and a printed insulating resin. And a polishing step of polishing the insulating resin to expose the tips of the conductive projections.

2. The method for manufacturing a wiring board according to claim 1, wherein the wiring board is a substrate for a semiconductor package.

The method according to claim 1, wherein the wiring member is a metal foil having a plurality of conductive protrusions on a surface.

3. The method for manufacturing a wiring board according to claim 1, wherein the wiring member has an insulating resin layer, a conductive layer connected between layers on both surfaces of the insulating resin layer, and a conductive protrusion on at least one surface of the insulating resin layer. .

The method for manufacturing a wiring board according to claim 1, wherein a polishing step is performed after the curing step.

A printing step of applying an insulating resin in a fluid varnish state before curing to a wiring member having a plurality of conductive protrusions on its surface by printing to a thickness at which the conductive protrusions are embedded with the insulating resin, and a printed insulating resin. Before the fluidity is lost, but before complete curing, a drying step of drying to a semi-cured state, a polishing step of polishing the insulating resin dried to a semi-cured state to expose the tips of the conductive protrusions, polishing The method for manufacturing a wiring board according to any one of claims 1 to 4, further comprising a curing step of completely curing the insulating resin later.

On the surface of the wiring member having the conductive protrusions, the insulating resin (1) in a fluid varnish state is printed, and the fluidity is lost. However, the resin is dried to a semi-cured state before complete curing. At least two kinds of insulating resin (2) which are different from the insulating resin (1) in component and different from the insulating resin (2) in a fluid varnish state and are different from the insulating resin (2) in a fluid varnish state. The insulating resin is printed in this order, and the fluidity is lost, but by drying to a semi-cured state before complete curing, the insulating resin (1) layer and the insulating resin (2) are dried. Forming a multilayer insulating resin layer composed of at least three layers of a layer and a layer of the insulating resin (3) to a thickness such that the conductive protrusions are embedded with the insulating resin; Curing process to cure and multi-layer insulation tree A method for manufacturing a wiring board according to any one claims 1 to 4 comprising a polishing step by polishing the layer to expose the tip of the conductive protrusion.

The method for manufacturing a wiring board according to claim 7, wherein the curing step is performed after the polishing step.

In the step of forming the multilayer insulating resin layer, an insulating resin having good adhesiveness to the wiring member is used as the insulating resin (1), and a second or more layer including the insulating resin (2) layer and the insulating resin (3) layer is used. 9. The method for manufacturing a wiring board according to claim 7, wherein an insulating resin having a characteristic of reducing warpage of the manufactured wiring board is used for the layer.

In the step of laminating the resin in a semi-cured state according to claim 7 or 8, a resin having a different content of inorganic or organic particles, or a resin having a different basic resin structure is formed by printing at an arbitrary position, shape, and thickness. Then, a method of forming a resin layer in which resins having different properties are mixed in an arbitrary portion in an insulating resin by laminating the resins.

A wiring board manufactured by the method according to claim 1.

A semiconductor package substrate manufactured by the method according to claim 1.

A semiconductor package using the semiconductor package substrate according to claim 12.

A method of manufacturing a wiring board with a built-in element, comprising: mounting an electronic component on a wiring board, embedding it with an insulating resin, forming an insulating resin layer, and providing wiring on the insulating resin layer. And mounting the electronic component by printing an insulating resin in a fluid varnish state before curing by printing, embedding an electronic component, and curing the printed insulating resin to form an insulating resin layer.

The method according to claim 14, wherein the electronic component is a semiconductor chip, and the wiring board with a built-in element is a semiconductor package with a built-in element.

The insulating resin (1) in a fluid varnish state is printed on the electronic component mounting surface of the wiring board, and the fluidity is lost. However, the resin is dried to a semi-cured state before it is completely cured. At least two kinds of insulating resins, which are different from (1) in composition and in a fluid varnish state, are insulative resin (2) and insulative resin (2) are different in composition and are in fluid varnish state Are printed in this order, and dried to a semi-cured state before complete curing, although the fluidity is lost, so that a layer of the insulating resin (1), a layer of the insulating resin (2) and A step of forming a multilayer insulating resin layer composed of at least three layers of the insulating resin (3) to a thickness at which the electronic component is embedded with the insulating resin, and curing to simultaneously and completely cure all the insulating resins in the multilayer insulating resin layer Process and arrange on the multilayer insulating resin layer The method of claim 14 or 15 wiring board according comprising the step of providing a.

17. The method according to claim 16, wherein after the step of forming the multilayer insulating resin layer, the surface of the multilayer insulating resin layer is polished flat and then a curing step is performed.

In the step of forming the multilayer insulating resin layer, an insulating resin having good adhesion to a wiring board and an electronic component is used as the insulating resin (1), and a second insulating resin (2) including an insulating resin (3) layer is used. The method for manufacturing a wiring board according to claim 16, wherein an insulating resin having a characteristic of reducing warpage of the manufactured element-containing wiring board is used for at least one layer.

In the step of laminating the resin in a semi-cured state according to claims 16 to 18, a resin having a different content of inorganic or organic particles, or a resin having a different basic resin structure is formed by printing at an arbitrary position, shape, and thickness. Then, a method of forming a resin layer in which resins having different properties are mixed in an arbitrary portion in an insulating resin by laminating the resins.

An element-containing wiring board manufactured by the method according to claim 14.

An element-containing semiconductor package manufactured by the method according to claim 14.