JPWO2006100909A1 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JPWO2006100909A1
JPWO2006100909A1 JP2006526475A JP2006526475A JPWO2006100909A1 JP WO2006100909 A1 JPWO2006100909 A1 JP WO2006100909A1 JP 2006526475 A JP2006526475 A JP 2006526475A JP 2006526475 A JP2006526475 A JP 2006526475A JP WO2006100909 A1 JPWO2006100909 A1 JP WO2006100909A1
Authority
JP
Japan
Prior art keywords
electrically insulating
semiconductor chip
insulating substrate
chip
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006526475A
Other languages
Japanese (ja)
Inventor
小松　慎五
慎五 小松
中谷　誠一
誠一 中谷
平野　浩一
浩一 平野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Publication of JPWO2006100909A1 publication Critical patent/JPWO2006100909A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01045—Rhodium [Rh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Abstract

複数の金属配線（５０５）を備えた電気絶縁性基板（５０４）の表面に半導体チップ（５０１）が実装され、少なくとも前記複数の金属配線（５０５）の一部を樹脂（５０９）が覆っている半導体装置であって、電気絶縁性基板（５０４）に形成された複数の金属配線（５０５）のうち、少なくとも前記半導体チップ（５０１）と電気的に接続される金属配線の表面には金層（５０８）を形成し、電気絶縁性基板に形成された複数の金属配線のうち、前記樹脂（５０９）と接触する金属配線の表面には金層を形成せず粗化部（５０７）を形成する。これにより、半導体チップが実装された半導体装置の電気接続の信頼性を向上させた半導体装置及びその製造方法を提供する。A semiconductor chip (501) is mounted on the surface of an electrically insulating substrate (504) having a plurality of metal wirings (505), and at least a part of the plurality of metal wirings (505) is covered with a resin (509). Among the plurality of metal wirings (505) formed on the electrically insulating substrate (504) in the semiconductor device, a gold layer (at least on the surface of the metal wiring electrically connected to the semiconductor chip (501)) 508) and a roughened portion (507) is formed without forming a gold layer on the surface of the metal wiring in contact with the resin (509) among the plurality of metal wirings formed on the electrically insulating substrate. . Thus, a semiconductor device in which the reliability of electrical connection of a semiconductor device on which a semiconductor chip is mounted is improved and a method for manufacturing the semiconductor device are provided.

Description

本発明は、半導体装置及びその製造方法に関し、とくに電気絶縁性基板の表面に金層が形成された電極端子に半導体チップが実装された半導体装置及びその製造方法に関する。  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a semiconductor chip is mounted on an electrode terminal having a gold layer formed on the surface of an electrically insulating substrate, and a manufacturing method thereof.

半導体装置は、情報通信機器、事務用電子機器、家庭用電子機器、測定装置、組み立てロボット等の産業用電子機器、医療用電子機器などの小型化、薄型化、高性能化に大きく寄与している。特に情報通信機器の分野での小型化の要求は大きく、半導体装置の高密度化、高機能化を目指し、半導体チップを積み重ねた構造の積層半導体チップを電気絶縁性基板に実装したものや、電気絶縁性基板の表面に電子部品を実装する従来の２次元的な実装方法から、電気絶縁性基板に電子部品を内蔵し、実装面積を大幅に縮小する３次元的な実装方法の開発が盛んに行なわれている。  Semiconductor devices greatly contribute to the downsizing, thinning, and high performance of industrial electronic devices such as information communication equipment, office electronic devices, home electronic devices, measuring devices, assembly robots, and medical electronic devices. Yes. In particular, there is a great demand for downsizing in the field of information and communication equipment. Aiming at higher density and higher functionality of semiconductor devices, stacked semiconductor chips stacked on an electrically insulating substrate, From the conventional two-dimensional mounting method of mounting electronic components on the surface of an insulating substrate, the development of a three-dimensional mounting method that incorporates electronic components in an electrically insulating substrate and greatly reduces the mounting area has been actively developed. It is done.

半導体装置の作製には、半導体チップとそれを搭載する電気絶縁性基板が必要である。半導体チップを電気絶縁性基板に搭載する実装技術は、大きくは、ワイヤボンディング実装とフリップチップ実装に分けられる。従来からの技術であるワイヤボンディング実装は、図９に示すように、半導体チップ９０１の素子電極９０２が形成された面と反対の面をダイボンディング材９１０を用いて電気絶縁性基板９０４にダイボンディングし、半導体チップの素子電極から電気絶縁性基板の表面に金９０８が形成された電極端子９０６の間を金ワイヤ９０３で電気接続し、半導体チップ、金ワイヤ部分をモールド樹脂９０９で全面的にモールドする方法である。  For manufacturing a semiconductor device, a semiconductor chip and an electrically insulating substrate on which the semiconductor chip is mounted are necessary. Mounting techniques for mounting a semiconductor chip on an electrically insulating substrate can be broadly divided into wire bonding mounting and flip chip mounting. As shown in FIG. 9, wire bonding mounting, which is a conventional technique, is performed by die bonding a surface opposite to the surface on which the element electrode 902 of the semiconductor chip 901 is formed on an electrically insulating substrate 904 using a die bonding material 910. Then, between the element electrode of the semiconductor chip and the electrode terminal 906 on which the gold 908 is formed on the surface of the electrically insulating substrate is electrically connected by the gold wire 903, and the semiconductor chip and the gold wire portion are entirely molded by the molding resin 909. It is a method to do.

一方、半導体チップの実装面積を小さくすることができ、最近、主流となっているフリップチップ実装は、半導体チップの素子電極面を電気絶縁性基板の電極端子に向け、電気接続する方法である。フリップチップ実装は、図１０に示すように、半導体チップ１００１の素子電極１００２と電気絶縁性基板１００４の電極端子１００６をバンプ１００３を介して電気接続する方法で、電気接続部分を封止樹脂１００９が保護している。フリップチップ実装は、封止樹脂の種類、電気接続方式によって、ＡＣＦ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）接続、ＡＣＰ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）接続といった半導体チップの素子電極と電気絶縁性基板の電極端子間に導電性粒子を介在して接続する方法、ＮＣＦ（Ｎｏｎ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）接続、ＮＣＰ（Ｎｏｎ Ｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）接続、超音波接合といった半導体チップの素子電極と電気絶縁性基板の電極端子同士を直接接触させて電気接続する方法がある。  On the other hand, the mounting area of a semiconductor chip can be reduced, and flip chip mounting, which has become the mainstream in recent years, is a method in which an element electrode surface of a semiconductor chip is directed to an electrode terminal of an electrically insulating substrate and is electrically connected. As shown in FIG. 10, the flip chip mounting is a method in which the element electrodes 1002 of the semiconductor chip 1001 and the electrode terminals 1006 of the electrically insulating substrate 1004 are electrically connected via bumps 1003. Protect. In flip chip mounting, conductive particles between an element electrode of a semiconductor chip and an electrode terminal of an electrically insulating substrate such as an ACF (Anisotropic Conductive Film) connection or an ACP (Anisotropic Conductive Paste) connection depending on the type of sealing resin and the electrical connection method. A method of connecting via an IC, an NCF (Non Conductive Film) connection, an NCP (Non Conductive Paste) connection, an ultrasonic bonding, and the like. There is a way.

通常、ワイヤボンディング実装、フリップチップ実装ともに、電気絶縁性基板の半導体チップ実装面の金属配線には、半導体チップが実装される電極端子を含めて一面に、金メッキ等によって表面に金が形成され、主に表面の清浄性を保つことで、半導体チップと電気絶縁性基板の電極端子との間を良好に電気接続している。  Usually, in both wire bonding mounting and flip chip mounting, the metal wiring on the semiconductor chip mounting surface of the electrically insulating substrate is formed with gold on the surface by gold plating or the like, including the electrode terminals on which the semiconductor chip is mounted, By mainly maintaining the cleanliness of the surface, the semiconductor chip and the electrode terminal of the electrically insulating substrate are electrically connected well.

また、より半導体装置の高密度化、高機能化を実現するために、図１１に示す積層半導体チップを電気絶縁性基板に実装した半導体装置（特許文献１、２）や、図１２に示す電子部品を電気絶縁性基板に内蔵し、内蔵した半導体チップと同一の電気絶縁性基板の層内で、導電性樹脂組成物を充填したインナービアにより電気接続を行い、２次元実装に対し、飛躍的に実装密度を向上させた部品内蔵モジュール（特許文献３）がある。また、特許文献４に示すように、半導体チップがフリップチップ実装された半導体装置において、半導体チップと電気絶縁性基板間に補強用の金属配線を形成する提案もある。  In order to realize higher density and higher functionality of the semiconductor device, a semiconductor device (Patent Documents 1 and 2) in which the laminated semiconductor chip shown in FIG. 11 is mounted on an electrically insulating substrate, or an electronic device shown in FIG. Incorporating components in an electrically insulating substrate, and making electrical connections with inner vias filled with a conductive resin composition within the same electrically insulating substrate layer as the embedded semiconductor chip, a dramatic improvement over 2D packaging There is a component built-in module (Patent Document 3) with improved mounting density. In addition, as shown in Patent Document 4, there is a proposal of forming a reinforcing metal wiring between a semiconductor chip and an electrically insulating substrate in a semiconductor device on which a semiconductor chip is flip-chip mounted.

しかし、ワイヤボンディング実装及びフリップチップ実装に通常必須となる電気絶縁性基板の金属配線の表面の金層は、電気接続の信頼性に悪影響を及ぼすことがある。金層は、酸化されず清浄であり、またワイヤボンディング実装に用いる金ワイヤや、フリップチップ実装時の半導体チップのバンプを圧着するのに適度な柔軟性をもち、良好な半導体チップと電気絶縁性基板の電極端子との間の電気接続を行ないやすいが、一方で、金層は平滑で樹脂との接着性が悪く、例えば銅表面のように表面の粗化処理によって簡単に樹脂との接着性を大きくすることが難しいという課題があった。  However, the gold layer on the surface of the metal wiring of the electrically insulating substrate, which is usually essential for wire bonding mounting and flip chip mounting, may adversely affect the reliability of electrical connection. The gold layer is clean and not oxidized, and has good flexibility for crimping gold wires used for wire bonding mounting and bumps of semiconductor chips during flip chip mounting, and good semiconductor chip and electrical insulation It is easy to make electrical connection with the electrode terminals on the board, but on the other hand, the gold layer is smooth and has poor adhesion to the resin. For example, the adhesion to the resin can be easily achieved by roughening the surface, such as the copper surface. There was a problem that it was difficult to increase the size.

この金層の特性に起因する半導体装置の課題として、第１番目にＡＣＦ接続、ＡＣＰ接続、ＮＣＦ接続、ＮＣＰ接続、超音波接合のような、半導体チップの素子電極に形成した金バンプと電気絶縁性基板の金属配線の金層を圧接によって電気接続するフリップチップ実装において、半導体チップの金バンプと電気絶縁性基板の金属配線の金層との接触、電気接続部分を物理的に保持するために半導体チップと電気絶縁性基板の間に配置される封止樹脂と電気絶縁性基板との接着性が悪く、例えば吸湿リフロー試験のような半導体パッケージの信頼性試験において熱衝撃が加えられると、容易に封止樹脂、電気絶縁性基板間が剥離し、剥離した界面が電気接続部分にも拡大し接続部の電気接続不良を起こす原因になるという課題があった。  As a problem of the semiconductor device due to the characteristics of the gold layer, first, gold bumps formed on element electrodes of a semiconductor chip, such as ACF connection, ACP connection, NCF connection, NCP connection, and ultrasonic bonding, are electrically insulated. In flip chip mounting, where the gold layer of the metal wiring on the conductive substrate is electrically connected by pressure contact, the contact between the gold bump of the semiconductor chip and the gold layer of the metal wiring of the electrically insulating substrate, to physically hold the electrical connection portion Adhesion between the sealing resin and the electrically insulating substrate disposed between the semiconductor chip and the electrically insulating substrate is poor, and it is easy to apply a thermal shock in a semiconductor package reliability test such as a moisture absorption reflow test. In other words, the sealing resin and the electrically insulating substrate are peeled off, and the peeled interface expands to the electrical connection portion, causing an electrical connection failure in the connection portion.

第２番目に、金ワイヤを用いて半導体チップの素子電極と電気絶縁性基板の金属配線の金層を電気接続し、半導体チップと金ワイヤを含めて、モールド樹脂でモールドするワイヤボンディング実装において、金ワイヤと金属配線の金層の接触部分、及び金ワイヤの形状を維持し、保護するためのモールド樹脂が、吸湿リフロー試験において熱衝撃が加えられると、ワイヤボンディング実装の形態においてはモールド樹脂、電気絶縁性基板間が容易に剥離し、同様にこの剥離した界面が発端となって電気接続不良を起こす原因になるという課題があった。  Second, in wire bonding mounting in which the element electrode of the semiconductor chip and the gold layer of the metal wiring of the electrically insulating substrate are electrically connected using a gold wire, and the semiconductor chip and the gold wire are molded with a molding resin. When the thermal shock is applied in the moisture absorption reflow test when the mold resin for maintaining and protecting the contact portion of the gold layer and the gold layer of the metal wiring and the shape of the gold wire is molded resin in the form of wire bonding mounting, There was a problem that the electrically insulating substrates were easily separated, and similarly, the separated interface was the origin and caused electrical connection failure.

第３番目に、複数の半導体チップを積層した積層半導体チップを電気絶縁性基板の電極端子にワイヤボンディング実装、もしくはワイヤボンディング実装とフリップチップ実装によって電気接続した形態でも、吸湿リフロー試験において、第１〜２番目の例と同様にワイヤボンディング実装のモールド樹脂やフリップチップ実装の封止樹脂の電気絶縁性基板との接着力不足に起因する剥離が生じ、半導体実装の電気接続不良が発生しやすいという課題があった。  Third, even in a form in which a laminated semiconductor chip in which a plurality of semiconductor chips are stacked is electrically connected to an electrode terminal of an electrically insulating substrate by wire bonding mounting or wire bonding mounting and flip chip mounting, ~ Similar to the second example, peeling due to insufficient adhesion of the mold resin for wire bonding mounting and the sealing resin for flip chip mounting to the electrically insulating substrate is likely to cause poor electrical connection in semiconductor mounting. There was a problem.

第４番目にフリップチップ実装された半導体を内蔵した部品内蔵モジュールの形態では、通常の半導体チップの実装形態のように表面に露出しておらず、電気絶縁性基板に内蔵されている。そのため、吸湿リフロー試験において熱衝撃が加えられると、半導体チップと電気絶縁性基板間に、第１〜３番目の例以上に、より大きな剥離応力が加えられ、容易に封止樹脂、電気絶縁性基板間が剥離し、電気接続不良を起こす原因となるという課題があった。また、電気絶縁性基板の金属配線の表面金層が平滑で非常に樹脂が滑りやすいため、部品内蔵モジュールに形成された導電性樹脂組成物からなる導電性ペーストが充填されたインナービアが滑って位置ずれを起こしやすいという課題があった。さらに導電性ペースト中の熱硬化性樹脂と金層との充分な接着性を得ることが難しく、容易に導電性ペーストが充填されたインナービアの剥離断線が起きやすかった。  In the form of a component built-in module that contains a fourth flip-chip mounted semiconductor, it is not exposed on the surface as in the case of a normal semiconductor chip mounting, but is built in an electrically insulating substrate. Therefore, when a thermal shock is applied in the moisture absorption reflow test, a larger peeling stress is applied between the semiconductor chip and the electrically insulating substrate than in the first to third examples, and the sealing resin and the electrical insulating property can be easily applied. There was a problem that the substrates were peeled off, causing electrical connection failure. Also, since the surface gold layer of the metal wiring of the electrically insulating substrate is smooth and the resin is very slippery, the inner via filled with the conductive paste made of the conductive resin composition formed on the component built-in module slips. There was a problem that it was easy to cause a positional shift. Furthermore, it was difficult to obtain sufficient adhesion between the thermosetting resin and the gold layer in the conductive paste, and the inner vias filled with the conductive paste were easily peeled off.

また、上記の課題は、金層の金属配線の面積に依存しやすく、同一作製条件でも、電気絶縁性基板の金属配線の設計パターンで信頼性が変わることがあり、確実な信頼性確保が非常に難しかった。  In addition, the above problem is likely to depend on the area of the metal wiring of the gold layer, and the reliability may vary depending on the design pattern of the metal wiring of the electrically insulating substrate even under the same manufacturing conditions. It was difficult.

また、特許文献４に示すように、半導体チップがフリップチップ実装された半導体装置において、半導体チップと電気絶縁性基板間に補強用の金属配線を形成する手法もあるが、余分な金属配線が必要となるため、金属配線の設計パターンの自由度が減るという問題を含んでいた。
特開２０００−３４９２２８号公報 特開２００４−２２８３２３号公報 特開平１１−２２０２６２号公報 特開２００４−１５３２１０号公報 In addition, as shown in Patent Document 4, in a semiconductor device in which a semiconductor chip is flip-chip mounted, there is a method of forming a reinforcing metal wiring between the semiconductor chip and the electrically insulating substrate, but an extra metal wiring is required. Therefore, there is a problem that the degree of freedom of the metal wiring design pattern is reduced.
JP 2000-349228 A JP 2004-228323 A Japanese Patent Laid-Open No. 11-220262 JP 2004-153210 A

本発明は、前記従来の問題を解決するため、半導体チップが実装された半導体装置の電気接続の信頼性を向上させた半導体装置及びその製造方法を提供する。  In order to solve the above-described conventional problems, the present invention provides a semiconductor device in which the reliability of electrical connection of a semiconductor device mounted with a semiconductor chip is improved, and a method for manufacturing the same.

本発明の半導体装置は、複数の金属配線を備えた電気絶縁性基板の表面に半導体チップが実装され、少なくとも前記複数の金属配線の一部を樹脂が覆っている半導体装置であって、前記電気絶縁性基板に形成された複数の金属配線のうち、少なくとも前記半導体チップと電気的に接続される金属配線の表面には金層を形成し、前記電気絶縁性基板に形成された複数の金属配線のうち、前記樹脂と接触する金属配線の表面には粗化部を形成することを特徴とする。  The semiconductor device of the present invention is a semiconductor device in which a semiconductor chip is mounted on the surface of an electrically insulating substrate having a plurality of metal wirings, and at least a part of the plurality of metal wirings is covered with a resin. Among the plurality of metal wirings formed on the insulating substrate, a gold layer is formed on at least the surface of the metal wiring electrically connected to the semiconductor chip, and the plurality of metal wirings formed on the electric insulating substrate Of these, a roughened portion is formed on the surface of the metal wiring in contact with the resin.

本発明の半導体装置の製造方法は、半導体チップと、前記半導体チップがフリップチップ実装される電極端子を含む複数の粗化処理された表面の金属配線が形成された主面をもつ電気絶縁性基板とを準備する工程（ａ）と、フォトリソグラフィー法によって、前記電気絶縁性基板の前記半導体チップがフリップチップ実装される主面の、前記電極端子以外の部分に、フォトレジストを形成する工程（ｂ）と、前記電気絶縁性基板のフリップチップ実装される主面に無電解金メッキを行なって、前記電極端子表面に金を形成した後、フォトレジストを除去する工程（ｃ）と、前記半導体チップの素子電極面と前記電気絶縁性基板の電極端子面との間に封止樹脂を介して、前記半導体チップを前記電気絶縁性基板にフリップチップ実装する工程（ｄ）とを含むことを特徴とする。  A method of manufacturing a semiconductor device according to the present invention includes a semiconductor chip and an electrically insulating substrate having a main surface on which a plurality of roughened metal wirings including electrode terminals on which the semiconductor chip is flip-chip mounted are formed. And (b) forming a photoresist on a portion other than the electrode terminals on the main surface of the electrically insulating substrate on which the semiconductor chip is flip-chip mounted by a photolithography method (b) And (c) removing the photoresist after forming gold on the surface of the electrode terminal by performing electroless gold plating on the main surface of the electrically insulating substrate to be flip-chip mounted; and A step of flip-chip mounting the semiconductor chip on the electrically insulating substrate via a sealing resin between the element electrode surface and the electrode terminal surface of the electrically insulating substrate ( Characterized in that it comprises a) and.

本発明の別の半導体装置の製造方法は、半導体チップと、前記半導体チップがワイヤボンディング実装される電極端子を含む複数の粗化処理された表面の金属配線が形成された主面をもつ電気絶縁性基板とを準備する工程（ａ）と、フォトリソグラフィー法によって、前記電気絶縁性基板の前記半導体チップがワイヤボンディング実装される主面の、前記電極端子以外の部分に、フォトレジストを形成する工程（ｂ）と、前記電気絶縁性基板のワイヤボンディング実装される主面に無電解金メッキを行なって、前記電極端子表面に金を形成した後、フォトレジストを除去する工程（ｃ）と、前記半導体チップの素子電極が形成されている面の反対の主面を前記電気絶縁性基板に接合する工程（ｄ）と、前記半導体チップを前記電気絶縁性基板にワイヤボンディング実装する工程（ｅ）と、前記半導体チップと前記ワイヤボンディング実装部分を樹脂モールドする工程（ｆ）とを含むことを特徴とする。  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising: a semiconductor chip; and an electrical insulation having a main surface on which a plurality of roughened surface metal wirings including electrode terminals on which the semiconductor chip is wire-bonded and mounted are formed. A step of preparing a conductive substrate, and a step of forming a photoresist on a portion other than the electrode terminals on a main surface of the electrically insulating substrate on which the semiconductor chip is wire-bonded and mounted by photolithography. (B), a step (c) of removing the photoresist after performing electroless gold plating on the main surface of the electrically insulating substrate to be wire-bonded and mounted to form the electrode terminal surface, and the semiconductor A step (d) of bonding a main surface opposite to a surface on which an element electrode of a chip is formed to the electrically insulating substrate; and the semiconductor chip is bonded to the electrically insulating substrate. A wire bonding mounting to step (e), the semiconductor chip and the wire bonding mounting portion, characterized in that it comprises a step of resin molding (f).

本発明のさらに別の半導体装置の製造方法は、半導体チップと、前記半導体チップがフリップチップ実装される電極端子を含む複数の粗化処理された表面の金属配線が形成された主面をもつ第１の電気絶縁性基板と、複数の金属配線が形成された主面をもつ第２の電気絶縁性基板と、無機フィラーと熱硬化性樹脂とを含む混合物からなる第３の電気絶縁性基板である板状体を準備する工程（ａ）と、フォトリソグラフィー法によって、前記第１の電気絶縁性基板の前記半導体チップがフリップチップ実装される主面の、前記電極端子以外の部分に、フォトレジストを形成する工程（ｂ）と、前記第１の電気絶縁性基板のフリップチップ実装される主面に無電解金メッキを行なって、前記電極端子表面に金を形成した後、フォトレジストを除去する工程（ｃ）と、前記半導体チップの素子電極面と前記電気絶縁性基板の電極端子面との間に封止樹脂を介して、前記半導体チップを前記電気絶縁性基板にフリップチップ実装する工程（ｄ）と、前記板状体に貫通孔を形成し、前記貫通孔に導電性樹脂組成物からなる導電性ペーストを充填する工程（ｅ）と、前記第１と第２の電気絶縁性基板及び前記板状体を、前記板状体の一方の主面に前記第１の電気絶縁性基板の前記半導体チップがフリップチップ実装された主面が向くように、もう一方の主面に前記第２の電気絶縁性基板の金属配線が形成された主面が向くように位置あわせし、積層する工程（ｆ）と、加熱加圧して、前記第１と第２の電気絶縁性基板を前記板状体に接着し、前記半導体チップを前記板状体に埋設して一体化し、前記板状体及び前記導電性樹脂組成物からなる導電性ペーストを硬化させる工程（ｇ）とを含むことを特徴とする。  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device having a main surface on which a plurality of roughened surface metal wirings including a semiconductor chip and electrode terminals on which the semiconductor chip is flip-chip mounted are formed. A third electrically insulating substrate made of a mixture comprising an electrically insulating substrate, a second electrically insulating substrate having a main surface on which a plurality of metal wirings are formed, and an inorganic filler and a thermosetting resin; Step (a) of preparing a plate-like body, and a photoresist on a portion other than the electrode terminals on the main surface of the first electrically insulating substrate on which the semiconductor chip is flip-chip mounted by photolithography. And forming the gold on the electrode terminal surface by performing electroless gold plating on the flip chip mounted main surface of the first electrically insulating substrate, and then removing the photoresist (C) and flip-chip mounting the semiconductor chip on the electrically insulating substrate via a sealing resin between the element electrode surface of the semiconductor chip and the electrode terminal surface of the electrically insulating substrate (D), a step (e) of forming a through hole in the plate-like body, and filling the through hole with a conductive paste made of a conductive resin composition, and the first and second electrically insulating substrates. The plate-like body is placed on the other main surface so that the main surface on which the semiconductor chip of the first electrically insulating substrate is flip-chip mounted faces one main surface of the plate-like body. Step (f) of aligning and laminating the main surface on which the metal wiring of the electrically insulating substrate of 2 is formed, and laminating and heating and pressing the first and second electrically insulating substrates to the plate Adhering to a body, the semiconductor chip is embedded in the plate body and integrated, Comprise a serial plate-like body and curing the conductive paste comprising the conductive resin composition (g) and said.

図１は本発明の実施形態１における半導体装置の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention. 図２は本発明の実施形態２における半導体装置の断面図である。FIG. 2 is a cross-sectional view of a semiconductor device according to Embodiment 2 of the present invention. 図３は本発明の実施形態３における半導体装置の断面図である。FIG. 3 is a cross-sectional view of a semiconductor device according to Embodiment 3 of the present invention. 図４は本発明の実施形態４における半導体装置の断面図である。FIG. 4 is a cross-sectional view of a semiconductor device according to Embodiment 4 of the present invention. 図５は本発明の実施形態５及び実施例１における半導体装置の断面図である。FIG. 5 is a cross-sectional view of the semiconductor device according to Embodiment 5 and Example 1 of the present invention. 図６Ａ−Ｄは本発明の実施形態６における半導体装置の製造方法を示す工程断面図である。6A to 6D are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 6 of the present invention. 図７Ａ−Ｅは本発明の実施形態７における半導体装置の製造方法を示す工程断面図である。7A to 7E are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 7 of the present invention. 図８Ａ−Ｉは本発明の実施形態８における半導体装置の製造方法を示す工程断面図である。8A to 8I are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 8 of the present invention. 図９は従来の半導体装置の一例を示す断面図である。FIG. 9 is a cross-sectional view showing an example of a conventional semiconductor device. 図１０は従来の半導体装置の別の一例を示す断面図である。FIG. 10 is a cross-sectional view showing another example of a conventional semiconductor device. 図１１は従来の半導体装置の別の一例を示す断面図である。FIG. 11 is a cross-sectional view showing another example of a conventional semiconductor device. 図１２は従来の半導体装置の別の一例を示す断面図である。FIG. 12 is a cross-sectional view showing another example of a conventional semiconductor device.

本発明の半導体装置は、半導体チップが実装された電気絶縁性基板の金属配線において、半導体チップが実装された電極端子の表面に金層を形成し、その他の金属配線には金層を形成せず表面を粗化することで、フリップチップ実装における封止樹脂と電気絶縁性基板間、ワイヤボンディング実装におけるモールド樹脂と電気絶縁性基板間の接着強度を大きくしたものである。接着強度を大きくすることで、吸湿リフロー試験等の信頼性試験における電気接続の信頼性を向上させることができる。また、フリップチップ実装における封止樹脂部分、ワイヤボンディング実装におけるモールド樹脂部分の電気絶縁性基板の金属配線の設計パターンが、電気接続信頼性へ与える影響を低減することができる。  In the semiconductor device of the present invention, in the metal wiring of the electrically insulating substrate on which the semiconductor chip is mounted, a gold layer is formed on the surface of the electrode terminal on which the semiconductor chip is mounted, and the gold layer is not formed on the other metal wiring. By roughening the surface, the adhesive strength between the sealing resin and the electrically insulating substrate in flip chip mounting and between the mold resin and the electrically insulating substrate in wire bonding mounting is increased. By increasing the adhesive strength, the reliability of electrical connection in a reliability test such as a moisture absorption reflow test can be improved. Moreover, the influence which the design pattern of the metal wiring of the electrically insulating board | substrate of the sealing resin part in flip chip mounting and the mold resin part in wire bonding mounting has on electrical connection reliability can be reduced.

また、複数の半導体チップを積層した積層半導体チップを電気絶縁性基板にワイヤボンディング実装、もしくはワイヤボンディング実装とフリップチップ実装によって電気接続した形態において、ワイヤボンディング実装のモールド樹脂と電気絶縁性基板間やフリップチップ実装の封止樹脂と電気絶縁性基板間の接着強度を大きくし、吸湿リフロー試験等の信頼性試験における信頼性を向上させることができる。積層半導体チップの形態では、一枚の半導体チップに比べ、樹脂との接着面数や面積が多くなり、また形状的にコーナー部や半導体チップ間の積層界面等に局所的により大きな応力がかかりやすい。そのため、積層半導体チップの実装信頼性の確保は、通常の一枚の半導体チップの実装信頼性の確保以上に難しいものであったが、電気絶縁性基板の実装面の接着強度を大きくすることで、積層半導体チップの実装信頼性を改善することができる。  Also, in a form in which a laminated semiconductor chip in which a plurality of semiconductor chips are stacked is electrically connected to an electrically insulating substrate by wire bonding mounting or wire bonding mounting and flip chip mounting, the wire bonding mounting between the mold resin and the electrically insulating substrate The adhesive strength between the flip-chip mounting sealing resin and the electrically insulating substrate can be increased, and the reliability in a reliability test such as a moisture absorption reflow test can be improved. In the form of the laminated semiconductor chip, the number and area of the adhesive surface with the resin are larger than that of a single semiconductor chip, and a larger stress is likely to be applied locally to the corner portion or the laminated interface between the semiconductor chips due to the shape. . For this reason, securing the mounting reliability of the laminated semiconductor chip was more difficult than securing the mounting reliability of a single semiconductor chip, but by increasing the adhesive strength of the mounting surface of the electrically insulating substrate. The mounting reliability of the laminated semiconductor chip can be improved.

また、フリップチップ実装された半導体を内蔵した部品内蔵モジュールの形態において、フリップチップ実装の封止樹脂と電気絶縁性基板間の接着強度を向上させ、表面実装された半導体チップより封止樹脂と電気絶縁性基板間の剥離応力が大きく、信頼性の高い電気接続の実現が難しい部品内蔵モジュールの形態の半導体装置の吸湿リフロー試験等の信頼性試験における電気接続信頼性を向上させることができる。また、部品内蔵モジュールに形成された導電性樹脂組成物が充填されたインナービアの電気接続される金属配線の表面が粗化処理されているので、平滑で樹脂が滑りやすい金層で発生しやすいインナービアの位置ずれを抑制することができ、またインナービアと金属配線との接着強度が大きくなるため、各種の信頼性試験において、剥離の発生がなく、高信頼な電気接続を保つことができる。  Also, in the form of a component built-in module containing a flip-chip mounted semiconductor, the adhesive strength between the flip-chip mounting sealing resin and the electrically insulating substrate is improved, and the sealing resin and electrical It is possible to improve electrical connection reliability in a reliability test such as a moisture absorption reflow test of a semiconductor device in the form of a component built-in module in which peeling stress between insulating substrates is large and it is difficult to realize highly reliable electrical connection. Moreover, since the surface of the metal wiring electrically connected to the inner via filled with the conductive resin composition formed in the component built-in module is roughened, it is easy to generate a smooth and slippery gold layer. The displacement of the inner vias can be suppressed, and the adhesive strength between the inner vias and the metal wiring is increased. Therefore, in various reliability tests, no peeling occurs and a highly reliable electrical connection can be maintained. .

半導体チップが実装される電気絶縁性基板の電極端子を含む一部の金属配線の表面に金層が形成されており、他の金属配線の表面に金層が形成されておらず、粗化処理されている形態が好ましい。金属配線の表面の選択的な金層の形成を行なうことができる。半導体チップの実装のために金層の形成が必須の電極端子を除いて、金層の形成を行なう金属配線表面の選択は、簡単な設計パターンで金層形成のフォトレジストを形成できるように、また、半導体チップの実装の電気接続信頼性が悪化しない面積であるよう、選択するのがよい。  A gold layer is formed on the surface of some of the metal wiring including the electrode terminals of the electrically insulating substrate on which the semiconductor chip is mounted, and no gold layer is formed on the surface of the other metal wiring. The form is preferred. A selective gold layer can be formed on the surface of the metal wiring. With the exception of electrode terminals that require the formation of a gold layer for mounting a semiconductor chip, the selection of the metal wiring surface on which the gold layer is to be formed can be used to form a gold layer-forming photoresist with a simple design pattern. Further, it is preferable to select an area that does not deteriorate the electrical connection reliability of the mounting of the semiconductor chip.

電極端子表面の金層の形成方法は、無電解メッキ、電解メッキ、蒸着、又はスパッタのいずれかが好ましい。既存の金層の形成技術をそのまま用いて本発明の半導体装置を作製することができる。特に、蒸着、スパッタはドライプロセスで形成することができ、簡易な手法としてより好ましい。  The method for forming the gold layer on the electrode terminal surface is preferably any one of electroless plating, electrolytic plating, vapor deposition, and sputtering. The semiconductor device of the present invention can be manufactured using an existing gold layer forming technique as it is. In particular, vapor deposition and sputtering can be formed by a dry process, which is more preferable as a simple method.

フリップチップ実装は、ＡＣＦ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ），ＡＣＰ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ），ＮＣＦ（Ｎｏｎ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ），ＮＣＰ（Ｎｏｎ Ｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）のいずれかを用いた熱圧着工法、又は半導体チップの素子電極に形成された金バンプと電気絶縁性基板の電極端子表面に形成された金の超音波接合によって行なわれることが好ましい。既存のフリップチップ実装技術をそのまま用いることができる。また、上記の既存のフリップチップ実装技術のみに限定されるのでなく、電気絶縁性基板の半導体チップを実装する電極端子に金配線を用い、封止樹脂、モールド樹脂等によって実装部を保護する形態の実装技術には、同様の効果を得ることができる。  Flip chip mounting is performed using either an ACF (Anisotropic Conductive Film), ACP (Anisotropic Conductive Paste), NCF (Non Conductive Film), NCP (Non Conductive Paste), or a semiconductor using a thermal bonding method. Preferably, this is performed by ultrasonic bonding of the gold bumps formed on the electrode terminal surface of the electrically insulating substrate. Existing flip chip mounting technology can be used as it is. Also, the present invention is not limited to the above existing flip chip mounting technology, and a form in which gold wiring is used for an electrode terminal for mounting a semiconductor chip on an electrically insulating substrate and the mounting portion is protected by a sealing resin, a mold resin, or the like. The same effect can be obtained in the mounting technology.

配線は粗化した銅とすることが好ましい。銅配線基板は、安価に作製することができ、多種多様な市販品を入手しやすい。また、表面の粗化処理を行ないやすい。銅以外にも銅を含む合金であっても良い。粗化した銅箔は市販品を用いてもよいし、平滑な銅箔をエッチング液によるエッチング処理、プラズマ処理、研磨剤による研磨処理、電解などの処理により形成できる。  The wiring is preferably roughened copper. The copper wiring board can be manufactured at low cost, and a wide variety of commercially available products are easily available. Moreover, it is easy to roughen the surface. An alloy containing copper other than copper may be used. A commercially available product may be used as the roughened copper foil, or a smooth copper foil may be formed by an etching process using an etching solution, a plasma process, a polishing process using an abrasive, or an electrolysis process.

前記第３の電気絶縁性基板は、無機フィラーと熱硬化性樹脂とを含む混合物からなることが好ましい。また第１〜３に含まれる熱可塑性樹脂は同一の材料としてもよい。これにより、電気絶縁性基板１、３間及び２、３間の樹脂同士の接着強度を大きくすることで、それぞれの電気絶縁性基板の接着面の接着強度を大きくし、吸湿リフロー試験等の信頼性試験において、電気接続の信頼性を向上させることができる。また、異なる材料の異種積層の形態からなる半導体装置に比べ、応力が小さくなることで、電気接続の信頼性が向上する効果がある。  The third electrically insulating substrate is preferably made of a mixture containing an inorganic filler and a thermosetting resin. The thermoplastic resins included in the first to third may be the same material. As a result, the adhesive strength between the electrically insulating substrates 1 and 3 and between the resins 2 and 3 is increased, thereby increasing the adhesive strength of the adhesive surfaces of the respective electrically insulating substrates, and reliability such as a moisture absorption reflow test. In the reliability test, the reliability of the electrical connection can be improved. In addition, since the stress is reduced as compared with a semiconductor device formed of different layers of different materials, there is an effect of improving the reliability of electrical connection.

無機フィラーは７０重量％〜９５重量％含まれることが好ましい。９５重量％以上であると、粉体量に対し、液体量が少なすぎ、シート化することが難しい。また、７０重量％以下であると、無機フィラーを混合したことによる放熱性の向上等の効果が少なくなる。加熱加圧して半導体チップを電気絶縁性基板に内蔵する時に、半導体チップに損傷を与えない粘度であれば、無機フィラーの配合率は大きい方がより好ましい。  The inorganic filler is preferably contained in an amount of 70% to 95% by weight. If it is 95% by weight or more, the amount of liquid is too small relative to the amount of powder, making it difficult to form a sheet. On the other hand, when it is 70% by weight or less, effects such as improvement of heat dissipation due to mixing of the inorganic filler are reduced. When the viscosity is such that the semiconductor chip is not damaged when the semiconductor chip is built in the electrically insulating substrate by heating and pressurizing, it is more preferable that the blending ratio of the inorganic filler is large.

無機フィラーは、Ａｌ２Ｏ３、ＭｇＯ、ＢＮ、ＡｌＮ及びＳｉＯ２から選ばれる少なくとも一つの無機フィラーであることが好ましい。これらの無機フィラーを用いることで、放熱性に優れた半導体装置となる。また、無機フィラーとして、ＳｉＯ２を用いた場合、誘電率を小さくすることができる。The inorganic filler is preferably at least one inorganic filler selected from Al 2 O 3 , MgO, BN, AlN and SiO 2 . By using these inorganic fillers, a semiconductor device having excellent heat dissipation is obtained. Further, when SiO 2 is used as the inorganic filler, the dielectric constant can be reduced.

熱硬化性樹脂は、エポキシ樹脂、フェノール樹脂、及びシアネート樹脂から選ばれる少なくとも一つの熱硬化性樹脂であることが好ましい。これらの樹脂は多種多様な種類が市販されており、これらの樹脂を用いることで耐熱性や電気絶縁性に優れた半導体装置となる。  The thermosetting resin is preferably at least one thermosetting resin selected from an epoxy resin, a phenol resin, and a cyanate resin. A wide variety of these resins are commercially available, and by using these resins, a semiconductor device having excellent heat resistance and electrical insulation can be obtained.

導電性樹脂組成物は金、銀、銅、及びニッケルから選ばれる少なくとも一つの金属を含む金属粒子を導電性成分として含み、エポキシ樹脂を樹脂成分として含むことが好ましい。上記金属は電気抵抗が低く、また、エポキシ樹脂は、耐熱性や電気絶縁性に優れているからである。特に、銅粉をコア材に表面を銀でコートした金属粒子は、機械的強度が強く安価である銅粉と酸化しにくい銀粉の両方の特性を併せもち、好適である。  The conductive resin composition preferably contains metal particles containing at least one metal selected from gold, silver, copper, and nickel as a conductive component, and an epoxy resin as a resin component. This is because the metal has a low electrical resistance, and the epoxy resin is excellent in heat resistance and electrical insulation. In particular, metal particles obtained by coating copper powder on a core material with silver on the surface are suitable because they have both characteristics of copper powder having high mechanical strength and low cost and silver powder that is difficult to oxidize.

本発明の製造方法においては、半導体チップと、前記半導体チップがフリップチップ実装される電極端子を含む複数の表面に粗化処理が行なわれた金属配線が形成された主面をもつ電気絶縁性基板とを準備する工程（ａ）と、フォトリソグラフィー法によって、前記電気絶縁性基板の前記半導体チップがフリップチップ実装される主面の、前記電極端子以外の部分に、フォトレジストを形成する工程（ｂ）と、前記電気絶縁性基板のフリップチップ実装される主面に無電解金メッキを行なって前記電極端子表面に金を形成した後、フォトレジストを除去する工程（ｃ）と、前記半導体チップの素子電極面と前記電気絶縁性基板の電極端子面との間に封止樹脂を介して、前記半導体チップを前記電気絶縁性基板にフリップチップ実装する工程（ｄ）とを含むのが好ましい。既存のフリップチップ実装技術とフォトリソグラフィー法をそのまま使用することができ、本発明の信頼性の高い半導体装置を作製することができる。  In the manufacturing method of the present invention, an electrically insulating substrate having a main surface on which a plurality of surfaces including a semiconductor chip and an electrode terminal on which the semiconductor chip is flip-chip mounted is provided with a roughened metal wiring. And (b) forming a photoresist on a portion other than the electrode terminals on the main surface of the electrically insulating substrate on which the semiconductor chip is flip-chip mounted by a photolithography method (b) And (c) removing the photoresist after forming gold on the surface of the electrode terminal by performing electroless gold plating on the flip-chip mounted main surface of the electrically insulating substrate, and the element of the semiconductor chip A step of flip-chip mounting the semiconductor chip on the electrically insulating substrate via a sealing resin between the electrode surface and the electrode terminal surface of the electrically insulating substrate ( ) And preferably includes a. Existing flip chip mounting technology and photolithography can be used as they are, and a highly reliable semiconductor device of the present invention can be manufactured.

また、半導体チップと、前記半導体チップがワイヤボンディング実装される電極端子を含む複数の表面に粗化処理が行なわれた金属配線が形成された主面をもつ電気絶縁性基板とを準備する工程（ａ）と、フォトリソグラフィー法によって、前記電気絶縁性基板の前記半導体チップがワイヤボンディング実装される主面の、前記電極端子以外の部分に、フォトレジストを形成する工程（ｂ）と、前記電気絶縁性基板のワイヤボンディング実装される主面に無電解金メッキを行なって前記電極端子表面に金を形成した後、フォトレジストを除去する工程（ｃ）と、前記半導体チップの素子電極が形成されている面の反対の主面を前記電気絶縁性基板に接合する工程（ｄ）と、前記半導体チップを前記電気絶縁性基板にワイヤボンディング実装する工程（ｅ）と、前記半導体チップと前記ワイヤボンディング実装部分を樹脂モールドする工程（ｆ）とを含むのが好ましい。既存のワイヤボンディング実装技術とフォトリソグラフィー法をそのまま使用することができ、本発明の信頼性の高い半導体装置を作製することができる。  A step of preparing a semiconductor chip and an electrically insulating substrate having a main surface on which a plurality of surfaces including a metal wire subjected to a roughening process are formed, including electrode terminals on which the semiconductor chip is wire-bonded and mounted ( a), a step (b) of forming a photoresist on a portion other than the electrode terminals on a main surface of the electrically insulating substrate on which the semiconductor chip is wire-bonded and mounted by photolithography, and the electrical insulation Forming a gold on the electrode terminal surface by performing electroless gold plating on the main surface of the conductive substrate to be wire-bonded and mounted, and then removing the photoresist (c), and the element electrode of the semiconductor chip is formed A step (d) of bonding a main surface opposite to the surface to the electrically insulating substrate; and wire bonding mounting the semiconductor chip to the electrically insulating substrate. And step (e), preferably contains said semiconductor chip and the wire bonding mounting portions to the resin molding step (f). Existing wire bonding mounting technology and photolithography can be used as they are, and a highly reliable semiconductor device of the present invention can be manufactured.

また、複数の半導体チップが積層された積層半導体チップをワイヤボンディング実装、もしくはフリップチップ実装及びワイヤボンディング実装によって前記電気絶縁性基板に実装したものである。積層半導体チップを実装した形態の作製は、２段の高さの異なるワイヤボンディング実装を行なったり、ワイヤボンディング実装とフリップチップ実装の２種の実装を行なったり、非常に複雑な作製工程となり、既存の技術をそのまま用いて信頼性の高い半導体装置を作製することができる。  Also, a laminated semiconductor chip in which a plurality of semiconductor chips are laminated is mounted on the electrically insulating substrate by wire bonding mounting, or flip chip mounting and wire bonding mounting. Fabrication of a form in which a laminated semiconductor chip is mounted is a very complicated fabrication process, such as wire bonding mounting with two different heights, or wire bonding mounting and flip chip mounting. A highly reliable semiconductor device can be manufactured using this technique as it is.

また、導電性ペーストが充填されたインナービアと電気接続される金属配線が粗化されているため、加熱加圧工程において、半導体チップを板状体に埋設する際に、板状体を構成する熱硬化性樹脂の流動に抗してインナービアの位置ずれが起きにくい。このため、半導体チップにより近い領域にインナービアを形成したり、より狭ピッチにインナービアを配置したりすることができる。  Further, since the metal wiring electrically connected to the inner via filled with the conductive paste is roughened, the plate-like body is formed when the semiconductor chip is embedded in the plate-like body in the heating and pressing step. The inner via is less likely to be displaced against the flow of the thermosetting resin. For this reason, inner vias can be formed in a region closer to the semiconductor chip, or inner vias can be arranged at a narrower pitch.

電気絶縁性基板の電極端子表面の金の形成方法は、電解メッキ、蒸着、又はスパッタのいずれかからなることが好ましい。既存の技術をそのまま使用して、電極端子表面への金の形成を行なうことができる。また、蒸着、スパッタによる電極端子表面への金の形成では、メッキのように薬品を使わないため、薬液の処理の必要がなく、簡単なドライプロセスで行なうことができる。  The method for forming gold on the electrode terminal surface of the electrically insulating substrate is preferably one of electrolytic plating, vapor deposition, and sputtering. The existing technology can be used as it is, and gold can be formed on the electrode terminal surface. Further, in the formation of gold on the electrode terminal surface by vapor deposition or sputtering, since no chemical is used unlike plating, there is no need for chemical treatment, and a simple dry process can be performed.

本発明において、前記金を形成しない金属配線表面の粗化の程度は、ＪＩＳ Ｂ ０６０１に規定の十点平均粗さＲｚにおいて、１〜１０μｍの範囲が好ましく、より好ましくは３〜６μｍの範囲である。前記範囲であれば、樹脂との接着性を高く維持できる。ここでＪＩＳ Ｂ ０６０１に規定の十点平均粗さ（ｔｅｎ ｐｏｉｎｔ ａｖｅｒａｇｅ ｈｅｉｇｈｔ，ｐｅａｋ ｔｏ ｖａｌｌｅｙ ａｖｅｒａｇｅ）は、任意の基準長さの粗さ曲線において、その平均線から高いほうの５個の山及び低いほうの５個の谷間での距離を平均した値の差で算出する（単位はμｍ）。  In the present invention, the degree of roughening of the surface of the metal wiring not forming the gold is preferably in the range of 1 to 10 μm, more preferably in the range of 3 to 6 μm, in the ten-point average roughness Rz defined in JIS B 0601. is there. If it is the said range, adhesiveness with resin can be maintained highly. Here, ten point average height, peak to valley average, as defined in JIS B 0601, is 5 peaks higher and lower than the average line in a roughness curve of an arbitrary reference length. The difference between the average values of the distances between the five valleys is calculated (unit: μm).

本発明によれば、半導体チップが実装された半導体装置において、電気絶縁性基板の金属配線の半導体チップが実装される電極端子の表面に金層が形成され、その他の金属配線の表面を粗化することにより、電気絶縁性基板の半導体チップ実装面とフリップチップ実装の封止樹脂、ワイヤボンディング実装のモールド樹脂との接着強度が大きくなり、半導体チップ実装の電気接続の信頼性を向上することができる。  According to the present invention, in a semiconductor device mounted with a semiconductor chip, a gold layer is formed on the surface of the electrode terminal on which the semiconductor chip of the metal wiring of the electrically insulating substrate is mounted, and the surface of the other metal wiring is roughened. As a result, the bonding strength between the semiconductor chip mounting surface of the electrically insulating substrate and the sealing resin for flip chip mounting and the mold resin for wire bonding mounting is increased, and the reliability of electrical connection for semiconductor chip mounting can be improved. it can.

以下、本発明の実施の形態について、図１乃至図８を用いて説明する。なお、本発明は下記の実施形態に限定されるものではない。  Hereinafter, embodiments of the present invention will be described with reference to FIGS. In addition, this invention is not limited to the following embodiment.

（実施形態１）
本発明の半導体装置の一実施形態を、図１の模式的な断面図を参照して説明する。１０１は半導体チップ、１０２は半導体チップの素子電極、１０３はバンプ、１０４は電気絶縁性基板、１０５は金属配線、１０６は半導体チップが実装される電極端子、１０７は金属配線の粗化部分、１０８は電極端子の金層、１０９は封止樹脂である。(Embodiment 1)
An embodiment of the semiconductor device of the present invention will be described with reference to the schematic cross-sectional view of FIG. 101 is a semiconductor chip, 102 is an element electrode of the semiconductor chip, 103 is a bump, 104 is an electrically insulating substrate, 105 is a metal wiring, 106 is an electrode terminal on which the semiconductor chip is mounted, 107 is a roughened portion of the metal wiring, 108 Is a gold layer of the electrode terminal, and 109 is a sealing resin.

電気絶縁性基板１０４の金属配線１０５の中で、半導体チップ１０１がフリップチップ実装される電極端子１０６の表面に金１０８を０．０１〜３μｍの厚みに形成し、その他の金属配線１０５の表面には金を形成せずに粗化（１０７）処理することにより、封止樹脂１０９と電気絶縁性基板１０４の接着強度が大きくし、封止樹脂１０９によって保持されている半導体チップ１０１のフリップチップ実装の電気接続信頼性を向上させる。実際の半導体装置では、封止樹脂１０９に接触している金属配線１０５の面積によって、電気接続信頼性が影響を受けやすいが、電極端子１０６以外の金属配線の表面に金を形成せず粗化処理することで、金属配線１０５の面積の影響を低減し、電気接続の信頼性を向上させることができる。  Gold 108 is formed to a thickness of 0.01 to 3 μm on the surface of the electrode terminal 106 on which the semiconductor chip 101 is flip-chip mounted in the metal wiring 105 of the electrically insulating substrate 104, and on the surface of the other metal wiring 105. By performing roughening (107) treatment without forming gold, the bonding strength between the sealing resin 109 and the electrically insulating substrate 104 is increased, and the flip chip mounting of the semiconductor chip 101 held by the sealing resin 109 is performed. Improve the electrical connection reliability. In an actual semiconductor device, although the electrical connection reliability is easily affected by the area of the metal wiring 105 in contact with the sealing resin 109, the surface of the metal wiring other than the electrode terminal 106 is roughened without forming gold. By processing, the influence of the area of the metal wiring 105 can be reduced, and the reliability of electrical connection can be improved.

本発明の実施形態において、市販されているもともと粗化された銅配線基板に選択的に金メッキを施すことで粗化部と平滑な金表面部を形成してもよいし、光沢銅箔を用いて後から粗化してもよい。後から粗化する手段として、化学的なエッチングによる表面の微粗化処理等が用いられる。  In an embodiment of the present invention, a roughened portion and a smooth gold surface portion may be formed by selectively performing gold plating on an originally roughened copper wiring board that is commercially available, or a bright copper foil is used. It may be roughened later. As a means for roughening later, surface roughening treatment by chemical etching or the like is used.

前記金を形成しない金属配線表面の粗化の程度は、ＪＩＳ Ｂ ０６０１に規定の十点平均粗さＲｚにおいて、１〜１０μｍの範囲が好ましく、より好ましくは３〜６μｍの範囲である。前記範囲であれば、樹脂との接着性を高く維持できる。  The degree of roughening of the surface of the metal wiring not forming gold is preferably in the range of 1 to 10 μm, more preferably in the range of 3 to 6 μm, in the ten-point average roughness Rz defined in JIS B 0601. If it is the said range, adhesiveness with resin can be maintained highly.

（実施形態２）
本発明の半導体装置の別の一実施形態を、図２の模式的な断面図を参照して説明する。２０１は半導体チップ、２０２は半導体チップの素子電極、２０３は金ワイヤ、２０４は電気絶縁性基板、２０５は金属配線、２０６は半導体チップが実装される電極端子、２０７は金属配線の粗化部分、２０８は電極端子の金層、２０９はモールド樹脂、２１０は半導体チップのダイボンディング材である。(Embodiment 2)
Another embodiment of the semiconductor device of the present invention will be described with reference to the schematic cross-sectional view of FIG. 201 is a semiconductor chip, 202 is an element electrode of the semiconductor chip, 203 is a gold wire, 204 is an electrically insulating substrate, 205 is a metal wiring, 206 is an electrode terminal on which the semiconductor chip is mounted, 207 is a roughened portion of the metal wiring, 208 is a gold layer of electrode terminals, 209 is a mold resin, and 210 is a die bonding material of a semiconductor chip.

電気絶縁性基板２０４の金属配線の中で、半導体チップ２０１がワイヤボンディング実装される電極端子２０６の表面に金を形成し、その他の金属配線２０５の表面には金を形成せずに粗化（２０７）処理することにより、モールド樹脂２０９と電気絶縁性基板２０４の接着強度を大きくし、モールド樹脂２０９によって保持されている半導体チップ２０１のワイヤボンディング実装の電気接続信頼性を向上させることができる。粗化の程度は実施形態１と同程度が好ましい。  In the metal wiring of the electrically insulating substrate 204, gold is formed on the surface of the electrode terminal 206 on which the semiconductor chip 201 is mounted by wire bonding, and the surface of the other metal wiring 205 is roughened without forming gold ( 207) By processing, the adhesive strength between the mold resin 209 and the electrically insulating substrate 204 can be increased, and the electrical connection reliability of the wire bonding mounting of the semiconductor chip 201 held by the mold resin 209 can be improved. The degree of roughening is preferably the same as in the first embodiment.

（実施形態３）
本発明の半導体装置の別の一実施形態を、図３の模式的な断面図を参照して説明する。３０１は積層半導体チップ、３０２は積層半導体チップの素子電極、３０３は金ワイヤ、３０４は電気絶縁性基板、３０５は金属配線、３０６は積層半導体チップが実装される電極端子、３０７は金属配線の粗化部分、３０８は電極端子の金層、３０９はモールド樹脂、３１０は半導体チップのダイボンディング材である。(Embodiment 3)
Another embodiment of the semiconductor device of the present invention will be described with reference to the schematic cross-sectional view of FIG. Reference numeral 301 is a laminated semiconductor chip, 302 is an element electrode of the laminated semiconductor chip, 303 is a gold wire, 304 is an electrically insulating substrate, 305 is a metal wiring, 306 is an electrode terminal on which the laminated semiconductor chip is mounted, and 307 is a rough metal wiring. 308 is a gold layer of an electrode terminal, 309 is a mold resin, and 310 is a die bonding material of a semiconductor chip.

２個の半導体チップが積層された積層半導体チップ３０１がワイヤボンディング実装された半導体装置においても、実施形態１〜２と同様に、電気絶縁性基板３０４の金属配線の中で、積層半導体チップ３０１がワイヤボンディング実装される電極端子３０６の表面に金を形成し、その他の金属配線３０５の表面には金を形成せず粗化（３０７）処理することにより、モールド樹脂３０９と電気絶縁性基板３０４の接着強度を大きくし、モールド樹脂３０９によって保持されている積層半導体チップ３０１のワイヤボンディング実装の電気接続信頼性を向上させることができる。また、積層する半導体チップ数が３枚に増えても、同様の効果を得ることができる。粗化の程度は実施形態１と同程度が好ましい。  Also in the semiconductor device in which the laminated semiconductor chip 301 in which two semiconductor chips are laminated is wire-bonded, the laminated semiconductor chip 301 is included in the metal wiring of the electrically insulating substrate 304 as in the first and second embodiments. Gold is formed on the surface of the electrode terminal 306 to be mounted by wire bonding, and the surface of the other metal wiring 305 is roughened (307) without forming gold, so that the mold resin 309 and the electrically insulating substrate 304 are formed. The adhesive strength can be increased, and the electrical connection reliability of the wire bonding mounting of the laminated semiconductor chip 301 held by the mold resin 309 can be improved. The same effect can be obtained even when the number of stacked semiconductor chips is increased to three. The degree of roughening is preferably the same as in the first embodiment.

（実施形態４）
本発明の半導体装置の別の一実施形態を、図４の模式的な断面図を参照して説明する。４０１は積層半導体チップ、４０２は積層半導体チップの素子電極、４０３は金ワイヤ、４０４はバンプ、４０５は電気絶縁性基板、４０６は金属配線、４０７は積層半導体チップが実装される電極端子、４０８は金属配線の粗化部分、４０９は電極端子の金層、４１０はモールド樹脂、４１１は封止樹脂、４１２は積層半導体チップのダイボンディング材である。(Embodiment 4)
Another embodiment of the semiconductor device of the present invention will be described with reference to the schematic cross-sectional view of FIG. 401 is a laminated semiconductor chip, 402 is an element electrode of the laminated semiconductor chip, 403 is a gold wire, 404 is a bump, 405 is an electrically insulating substrate, 406 is a metal wiring, 407 is an electrode terminal on which the laminated semiconductor chip is mounted, and 408 is A roughened portion of the metal wiring, 409 is a gold layer of an electrode terminal, 410 is a mold resin, 411 is a sealing resin, and 412 is a die bonding material of a laminated semiconductor chip.

２個の半導体チップが積層された積層半導体チップ４０１がフリップチップ実装及びワイヤボンディング実装によって電気接続された半導体装置においても、実施形態１〜３と同様に電気絶縁性基板４０５の金属配線の中で、積層半導体チップ４０１がワイヤボンディング実装及びフリップチップ実装によって電気接続される電極端子４０７の表面に金を形成し、その他の金属配線４０６の表面には金を形成せずに粗化（４０８）処理することにより、モールド樹脂４１０及び封止樹脂４１１と電気絶縁性基板４０５の接着強度を大きくし、モールド樹脂４１０及び封止樹脂４１１によって保持されている積層半導体チップ４０１のワイヤボンディング実装及びフリップチップ実装の電気接続信頼性を向上させることができる。また、積層する半導体チップ数が３枚に増えても、最下段の半導体チップをフリップチップ実装、上二段の半導体チップをワイヤボンディングすることで作製することができる。粗化の程度は実施形態１と同程度が好ましい。  Also in a semiconductor device in which a laminated semiconductor chip 401 in which two semiconductor chips are laminated is electrically connected by flip chip mounting and wire bonding mounting, in the metal wiring of the electrically insulating substrate 405 as in the first to third embodiments. The gold is formed on the surface of the electrode terminal 407 to which the laminated semiconductor chip 401 is electrically connected by wire bonding mounting and flip chip mounting, and the surface of the other metal wiring 406 is roughened without forming gold (408). By doing so, the bonding strength between the mold resin 410 and the sealing resin 411 and the electrically insulating substrate 405 is increased, and the wire bonding mounting and flip chip mounting of the laminated semiconductor chip 401 held by the mold resin 410 and the sealing resin 411 are performed. The electrical connection reliability can be improved. Further, even if the number of stacked semiconductor chips is increased to three, it can be manufactured by flip-chip mounting the lowermost semiconductor chip and wire bonding the upper two semiconductor chips. The degree of roughening is preferably the same as in the first embodiment.

（実施形態５）
本発明の半導体装置の別の一実施形態を、図５の模式的な断面図を参照して説明する。５０１は半導体チップ、５０２は半導体チップの素子電極、５０３はバンプ、５０４は電気絶縁性基板、５０５は金属配線、５０６は半導体チップが実装される電極端子、５０７は金属配線の粗化部分、５０８は電極端子の金層、５０９は封止樹脂、５１０は無機フィラーと熱硬化性樹脂とを含む混合物からなる電気絶縁性基板、５１１は導電性樹脂組成物が充填されたインナービアである。(Embodiment 5)
Another embodiment of the semiconductor device of the present invention will be described with reference to the schematic cross-sectional view of FIG. 501 is a semiconductor chip, 502 is an element electrode of the semiconductor chip, 503 is a bump, 504 is an electrically insulating substrate, 505 is a metal wiring, 506 is an electrode terminal on which the semiconductor chip is mounted, 507 is a roughened portion of the metal wiring, 508 Is an electrode terminal gold layer, 509 is a sealing resin, 510 is an electrically insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin, and 511 is an inner via filled with a conductive resin composition.

フリップチップ実装された半導体を電気絶縁性基板に内蔵した部品内蔵モジュールの形態の半導体装置において、電気絶縁性基板５０４の金属配線の中で、半導体チップ５０１がフリップチップ実装される電極端子５０６の表面に金を形成し、その他の金属配線５０５の表面には金を形成せず粗化（５０７）処理することにより、封止樹脂５０９と電気絶縁性基板５０４の接着強度及び無機フィラーと熱硬化性樹脂とを含む混合物からなる電気絶縁性基板５１０と電気絶縁性基板５０４の接着強度を大きくできる。また、これにより封止樹脂５０９によって保持され、電気絶縁性基板５１０に内蔵されている半導体チップ５０１のフリップチップ実装の電気接続信頼性を向上させることができる。この実施形態５のような半導体チップ５０１が電気絶縁性基板５１０に内蔵された形態においては、表面実装された半導体チップの形態より封止樹脂５０９、電気絶縁性基板５０４間の剥離応力が大きく、信頼性の高い電気接続の実現が難しいが、本実施形態の半導体装置によって、半導体チップの電気接続の信頼性を大きく向上させることができる。また、導電性樹脂組成物が充填されたインナービア５１１の電気接続される金属配線の表面が粗化処理されており、平滑な金層の場合、導電性樹脂組成物が充填されたインナービア５１１が金層上を滑って位置ずれを起こしやすかったが、本実施形態の半導体装置では、位置ずれを抑制することができる。また、インナービアと電気絶縁性基板の金属配線の接着強度が大きくなり、部品内蔵モジュールの形態の半導体装置における信頼性の高いインナービア接続を実現することができる。粗化の程度は実施形態１と同程度が好ましい。  In a semiconductor device in the form of a component built-in module in which a flip-chip mounted semiconductor is embedded in an electrically insulating substrate, the surface of the electrode terminal 506 on which the semiconductor chip 501 is flip-chip mounted in the metal wiring of the electrically insulating substrate 504 By forming gold on the surface and roughening (507) the surface of the other metal wiring 505 without forming gold, the adhesive strength between the sealing resin 509 and the electrically insulating substrate 504 and the inorganic filler and thermosetting The adhesive strength between the electrically insulating substrate 510 and the electrically insulating substrate 504 made of a mixture containing resin can be increased. In addition, the electrical connection reliability of the flip chip mounting of the semiconductor chip 501 held by the sealing resin 509 and built in the electrically insulating substrate 510 can thereby be improved. In the embodiment in which the semiconductor chip 501 is embedded in the electrically insulating substrate 510 as in the fifth embodiment, the peeling stress between the sealing resin 509 and the electrically insulating substrate 504 is larger than that of the surface-mounted semiconductor chip, Although it is difficult to realize highly reliable electrical connection, the reliability of electrical connection of a semiconductor chip can be greatly improved by the semiconductor device of this embodiment. In addition, the surface of the metal wiring electrically connected to the inner via 511 filled with the conductive resin composition is roughened, and in the case of a smooth gold layer, the inner via 511 filled with the conductive resin composition. However, in the semiconductor device of this embodiment, it is possible to suppress the positional deviation. Further, the adhesive strength between the inner via and the metal wiring of the electrically insulating substrate is increased, and a highly reliable inner via connection in the semiconductor device in the form of a component built-in module can be realized. The degree of roughening is preferably the same as in the first embodiment.

（実施形態６）
本発明の半導体装置の製造方法の一実施形態を、図６Ａ−Ｄの模式的な工程断面図を参照して説明する。６０１は半導体チップ、６０２は半導体チップの素子電極、６０３はバンプ、６０４は電気絶縁性基板、６０５は金属配線、６０６は半導体チップが実装される電極端子、６０７は金属配線の粗化部分、６０８は電極端子の金層、６０９は封止樹脂、６１０はフォトレジストである。(Embodiment 6)
One embodiment of a method for manufacturing a semiconductor device of the present invention will be described with reference to schematic process cross-sectional views of FIGS. 6A to 6D. 601 is a semiconductor chip, 602 is an element electrode of the semiconductor chip, 603 is a bump, 604 is an electrically insulating substrate, 605 is a metal wiring, 606 is an electrode terminal on which the semiconductor chip is mounted, 607 is a roughened portion of the metal wiring, 608 Is a gold layer of electrode terminals, 609 is a sealing resin, and 610 is a photoresist.

まず、金属配線６０５の表面が粗化された電気絶縁性基板６０４を用意する（図６Ａ）。次に、フォトリソグラフィー法により半導体チップ６０１（図６Ｄ）がフリップチップ実装される電極端子６０６を除く部分にフォトレジスト６１０を形成する（図６Ｂ）。次に、電極端子６０６の表面に金６０８を形成する。金層６０８は金メッキにより形成する。その後、フォトレジスト６１０を除去する（図６Ｃ）。次に、封止樹脂６０９を介して半導体チップ６０１を電気絶縁性基板６０４にフリップチップ実装して、本実施形態の半導体装置を作製する（図６Ｄ）。以上のとおり、既存のフリップチップ実装技術とフォトリソグラフィー法をそのまま使用することができ、信頼性の高い半導体装置を作製することができる。  First, an electrically insulating substrate 604 whose surface of the metal wiring 605 is roughened is prepared (FIG. 6A). Next, a photoresist 610 is formed on the portion excluding the electrode terminal 606 on which the semiconductor chip 601 (FIG. 6D) is flip-chip mounted by photolithography (FIG. 6B). Next, gold 608 is formed on the surface of the electrode terminal 606. The gold layer 608 is formed by gold plating. Thereafter, the photoresist 610 is removed (FIG. 6C). Next, the semiconductor chip 601 is flip-chip mounted on the electrically insulating substrate 604 via the sealing resin 609 to manufacture the semiconductor device of this embodiment (FIG. 6D). As described above, the existing flip chip mounting technique and the photolithography method can be used as they are, and a highly reliable semiconductor device can be manufactured.

（実施形態７）
本発明の半導体装置の製造方法の別の一実施形態を、図７Ａ−Ｅの模式的な工程断面図を参照して説明する。７０１は半導体チップ、７０２は半導体チップの素子電極、７０３は金ワイヤ、７０４は電気絶縁性基板、７０５は金属配線、７０６は半導体チップが実装される電極端子、７０７は金属配線の粗化部分、７０８は電極端子の金層、７０９はモールド樹脂、７１０は半導体チップのダイボンディング材、７１１はフォトレジストである。(Embodiment 7)
Another embodiment of the method for manufacturing a semiconductor device of the present invention will be described with reference to schematic process sectional views of FIGS. 701 is a semiconductor chip, 702 is an element electrode of the semiconductor chip, 703 is a gold wire, 704 is an electrically insulating substrate, 705 is a metal wiring, 706 is an electrode terminal on which the semiconductor chip is mounted, 707 is a roughened portion of the metal wiring, 708 is a gold layer of electrode terminals, 709 is a mold resin, 710 is a die bonding material of a semiconductor chip, and 711 is a photoresist.

まず、金属配線７０５の表面が粗化された電気絶縁性基板７０４を用意する（図７Ａ）。次に、フォトリソグラフィー法により半導体チップがワイヤボンディング実装される電極端子７０６を除く部分にフォトレジスト７１１を形成する（図７Ｂ）。次に、電極端子７０６の表面に金を形成し、フォトレジスト７１０を除去する（図７Ｃ）。次に、半導体チップ７０１の素子電極７０２が形成されていない面をダイボンディング材７１０を介して絶縁性基板７０４に接合し、金ワイヤ７０３を用いて半導体チップ７０１をワイヤボンディング実装する（図７Ｄ）。その後、半導体チップ７０１及び金ワイヤ７０３を含むワイヤボンディング実装部をモールド樹脂７０９でモールドし、本実施形態の半導体装置を作製する（図７Ｅ）。以上のようにして既存のワイヤボンディング実装技術とフォトリソグラフィー法をそのまま使用することができ、信頼性の高い半導体装置を作製することができる。  First, an electrically insulating substrate 704 whose surface of the metal wiring 705 is roughened is prepared (FIG. 7A). Next, a photoresist 711 is formed on the portion excluding the electrode terminal 706 where the semiconductor chip is mounted by wire bonding by photolithography (FIG. 7B). Next, gold is formed on the surface of the electrode terminal 706, and the photoresist 710 is removed (FIG. 7C). Next, the surface of the semiconductor chip 701 where the element electrode 702 is not formed is bonded to the insulating substrate 704 via the die bonding material 710, and the semiconductor chip 701 is wire-bonded and mounted using the gold wire 703 (FIG. 7D). . Thereafter, the wire bonding mounting portion including the semiconductor chip 701 and the gold wire 703 is molded with a mold resin 709 to manufacture the semiconductor device of this embodiment (FIG. 7E). As described above, the existing wire bonding mounting technique and the photolithography method can be used as they are, and a highly reliable semiconductor device can be manufactured.

（実施形態８）
本発明の半導体装置の製造方法の別の一実施形態を、図８Ａ−Ｉの模式的な工程断面図を参照して説明する。８０１は半導体チップ、８０２は半導体チップの素子電極、８０３はバンプ、８０４は半導体チップが電気接続される電気絶縁性基板、８０５は電気絶縁性基板、８０６は無機フィラーと熱硬化性樹脂とを含む混合物からなる板状体、８０７は貫通孔、８０８は導電性樹脂組成物からなる導電性ペーストが充填されたインナービア、８０９は金属配線、８１０は半導体チップが実装される電極端子、８１１は金属配線の粗化部分、８１２は電極端子の金層、８１３は封止樹脂、８１４はフォトレジストである。(Embodiment 8)
Another embodiment of the method for manufacturing a semiconductor device of the present invention will be described with reference to schematic process sectional views of FIGS. 8A-I. 801 is a semiconductor chip, 802 is an element electrode of the semiconductor chip, 803 is a bump, 804 is an electrically insulating substrate to which the semiconductor chip is electrically connected, 805 is an electrically insulating substrate, and 806 includes an inorganic filler and a thermosetting resin. A plate-like body made of a mixture, 807 is a through hole, 808 is an inner via filled with a conductive paste made of a conductive resin composition, 809 is a metal wiring, 810 is an electrode terminal on which a semiconductor chip is mounted, and 811 is a metal A roughened portion of the wiring, 812 is a gold layer of the electrode terminal, 813 is a sealing resin, and 814 is a photoresist.

まず、金属配線８０９の表面が粗化された電気絶縁性基板８０４を用意する（図８Ａ）。次に、フォトリソグラフィー法により半導体チップがフリップチップ実装される電極端子８１０を除く部分にフォトレジスト８１４を形成する（図８Ｂ）。次に、電極端子８１０の表面に金層８１２を形成し、フォトレジスト８１４を除去する（図８Ｃ）。次に、封止樹脂８１３を介して半導体チップ８０１を電気絶縁性基板８０４にフリップチップ実装する（図８Ｄ）。一方、無機フィラーと熱硬化性樹脂とを含む混合物からなる板状体８０６を準備し（図８Ｅ）、導電性ペーストが充填されインナービア８０８となる貫通孔８０７を形成する（図８Ｆ）。次に、貫通孔８０７に導電性ペーストを充填する（図８Ｇ）。次に、半導体チップ８０１をフリップチップ実装した電気絶縁性基板８０４と、導電性ペーストが充填されたインナービア８０８が形成された板状体８０６と、板状体８０６のもう一方の金属配線を形成するための電気絶縁性基板８０５を、インナービア８０８によって電気接続するように位置あわせする（図８Ｈ）。次に、加熱加圧して、電気絶縁性基板８０４と板状体８０６と電気絶縁性基板８０５を接着して、半導体チップ８０１を板状体８０６に埋設して一体化し、板状体８０６及びインナービア８０８に充填された導電性ペーストを硬化して、本実施形態の半導体装置を作製する（図８１）。以上のように、既存のフリップチップ実装技術とフォトリソグラフィー法をそのまま使用することができ、信頼性の高い半導体装置を作製することができる。また、加熱加圧工程による半導体チップの板状体への埋設時に、導電性ペーストが充填されたインナービアと電気接続される金属配線が粗化されており、インナービアの位置ずれが置きにくいため、金属配線の微細化、インナービアのビアピッチの狭ピッチ化が進んでも、この半導体装置では、導電性樹脂組成物からなる導電性ペーストが充填されたインナービアを位置精度良く形成することができる。  First, an electrically insulating substrate 804 whose surface of the metal wiring 809 is rough is prepared (FIG. 8A). Next, a photoresist 814 is formed on the portion excluding the electrode terminal 810 on which the semiconductor chip is flip-chip mounted by photolithography (FIG. 8B). Next, a gold layer 812 is formed on the surface of the electrode terminal 810, and the photoresist 814 is removed (FIG. 8C). Next, the semiconductor chip 801 is flip-chip mounted on the electrically insulating substrate 804 via the sealing resin 813 (FIG. 8D). On the other hand, a plate-like body 806 made of a mixture containing an inorganic filler and a thermosetting resin is prepared (FIG. 8E), and a through-hole 807 that is filled with a conductive paste and becomes an inner via 808 is formed (FIG. 8F). Next, the through-hole 807 is filled with a conductive paste (FIG. 8G). Next, an electrically insulating substrate 804 on which a semiconductor chip 801 is flip-chip mounted, a plate-like body 806 on which an inner via 808 filled with a conductive paste is formed, and another metal wiring of the plate-like body 806 are formed. The electrically insulating substrate 805 is aligned so as to be electrically connected by the inner via 808 (FIG. 8H). Next, by applying heat and pressure, the electrically insulating substrate 804, the plate-like body 806, and the electrically insulating substrate 805 are bonded, and the semiconductor chip 801 is embedded and integrated in the plate-like body 806, and the plate-like body 806 and the inner body are integrated. The conductive paste filled in the via 808 is cured to manufacture the semiconductor device of this embodiment (FIG. 81). As described above, the existing flip chip mounting technique and the photolithography method can be used as they are, and a highly reliable semiconductor device can be manufactured. In addition, when the semiconductor chip is embedded in the plate-like body by the heating and pressurizing process, the metal wiring electrically connected to the inner via filled with the conductive paste is roughened, and the inner via is not easily displaced. Even if miniaturization of the metal wiring and narrowing of the via pitch of the inner via progress, in this semiconductor device, the inner via filled with the conductive paste made of the conductive resin composition can be formed with high positional accuracy.

以下、実施例により本発明をさらに具体的に説明する。  Hereinafter, the present invention will be described more specifically with reference to examples.

（実施例１）
実施例１では上述の実施の形態５の部品内蔵モジュールの形態の半導体装置を、次の（ｉ）〜（ｉｖ）の手順に従って製造した。
（ｉ）電気絶縁性基板における電極端子の金層の形成
半導体チップを実装する電気絶縁性基板としてガラスエポキシ基板を準備した。ガラスエポキシ基板は厚さ２００μｍ、半導体チップを実装する電極端子、導電性樹脂組成物からなる導電性ペーストが充填されたインナービアを接続するビアランド、及びそれらを電気接続する金属配線が形成されており、それらの金属配線の厚さは１８μｍで、表面の粗化度合いは平均十点粗さＲｚ５μｍに粗化されている。フォトリソグラフィー法を用いてガラスエポキシ基板の半導体チップが実装される電極端子を除く部分にフォトレジストを形成した。フォトレジストには旭化成社製ＡＱ−１５５８を用いた。次に、このガラスエポキシ基板に無電解ニッケルメッキを１μｍ、引き続いて無電解金メッキ０．０４μｍを形成した。メッキ浴にはウエムラ・インターナショナル・シンガポール社製のニムデンＮＰＲ−Ｍ、オーリカルＴＫＫ５１ Ｍ２０を用いた。以上の工程により、半導体チップを実装する電極端子の表面のみに金を形成したガラスエポキシ基板を作製した。
（ｉｉ）半導体チップの実装
１０ｍｍ角、厚さ０．３ｍｍの半導体チップを準備し、半導体チップの１００個の素子電極に予め金ワイヤボンディング法によって高さ７０μｍの金バンプを突起状電極として形成した。フリップチップ実装に用いる封止樹脂には、日立化成社製の厚さ４０μｍのシート状封止樹脂ＵＦ−５１１を用いた。このシート状封止樹脂を面積が１００平方ｍｍとなるように加工した後、ガラスエポキシ基板の半導体チップが実装される領域に貼り付けた。次に、半導体チップを素子電極が形成されていない背面から加熱加圧し、ガラスエポキシ基板にフリップチップ実装した。加熱温度は２００℃、圧力は３ＭＰａ、加熱加圧時間は１５秒とした。その結果、半導体チップの素子電極とガラスエポキシ基板の無電解金メッキされた電極端子が、金バンプを介して電気接続され、封止樹脂が硬化した。
（ｉｉｉ）無機フィラーと熱硬化性樹脂とを含む混合物からなる板状体の準備
まず無機フィラーと熱硬化性樹脂の混合を、板状体を構成する材料を、必要に応じて粘度調整のための微量の溶剤を投入し、混合攪拌機を用いて混合し調整した。本実施例では、エポキシ樹脂１０重量％、シリカフィラー９０重量％を含む混合物を１０分間攪拌して調整した。次に、この混合物から、ドクターブレード法によって厚さ１００μｍの板状体を作製した。次に、この板状体を４枚重ねてラミネートし、厚さ４００μｍの板状体を形成した後、パンチャーを用いてインナービアとなる直径１６０μｍの貫通孔を形成し、この貫通孔に導電性ペーストをスクリーン印刷法により充填した。ここで使用した導電性ペーストは、球形状の銅粒子８５重量％と、樹脂成分としてビスフェノールＡ型エポキシ樹脂（油化シェルエポキシ社製「エピコート８２８」）３重量％と、グリシジルエステル系エポキシ樹脂（東都化成社製「ＹＤ−１７１」）９重量％と、硬化剤としてアミンアダクト硬化剤（味の素社製「ＭＹ−２４」）３重量％とを三本ロールを用いて混錬して調整した。
（ｉｖ）半導体チップの内蔵、一体化
次に（ｉｉ）で得た半導体チップをフリップチップ実装したガラスエポキシ基板と、（ｉｉｉ）で得た導電性ペーストを充填したインナービアが形成された板状体、そして板状体のもう一方の主面の金属配線を形成するためのガラスエポキシ基板を準備し、これらを半導体チップが板状体に内蔵されるよう、板状体のインナービアによって２つのガラスエポキシ基板及び板状体が電気接続されるよう、位置合わせした後、加熱加圧することで一体化し、本実施例の部品内蔵モジュールをした半導体装置を得た。加熱加圧は熱プレス機を用いて、加熱温度は２００℃、圧力は３ＭＰａ、加熱加圧時間は２時間とした。板状体に含まれるエポキシ樹脂は、粘度が一旦低下した後、硬化し、板状体とガラスエポキシ基板が接着された。導電性ペーストが充填されたインナービアに含まれるエポキシ樹脂も硬化し、板状体を通して２つのガラスエポキシ基板が電気接続された。(Example 1)
In Example 1, the semiconductor device in the form of the component built-in module of the above-described fifth embodiment was manufactured according to the following procedures (i) to (iv).
(I) Formation of gold layer of electrode terminal on electrically insulating substrate A glass epoxy substrate was prepared as an electrically insulating substrate for mounting a semiconductor chip. The glass epoxy substrate has a thickness of 200 μm, an electrode terminal for mounting a semiconductor chip, a via land for connecting an inner via filled with a conductive paste made of a conductive resin composition, and a metal wiring for electrically connecting them. The thickness of these metal wirings is 18 μm, and the roughness of the surface is roughened to an average ten-point roughness Rz of 5 μm. Photoresist was used to form a photoresist on the portion excluding the electrode terminals on which the semiconductor chip of the glass epoxy substrate was mounted. As a photoresist, AQ-1558 manufactured by Asahi Kasei Corporation was used. Next, 1 μm of electroless nickel plating was formed on the glass epoxy substrate, and subsequently 0.04 μm of electroless gold plating was formed. Nimuden NPR-M and Orical TKK51 M20 manufactured by Uemura International Singapore were used for the plating bath. Through the above steps, a glass epoxy substrate in which gold was formed only on the surface of the electrode terminal on which the semiconductor chip was mounted was produced.
(Ii) Mounting of semiconductor chip A 10 mm square semiconductor chip having a thickness of 0.3 mm was prepared, and gold bumps having a height of 70 μm were formed in advance on the 100 element electrodes of the semiconductor chip by a gold wire bonding method as protruding electrodes. . As the sealing resin used for flip chip mounting, a sheet-shaped sealing resin UF-511 made by Hitachi Chemical Co., Ltd. was used. After processing this sheet-form sealing resin so that an area might become 100 square mm, it affixed on the area | region where the semiconductor chip of a glass epoxy board | substrate is mounted. Next, the semiconductor chip was heated and pressed from the back surface where the device electrode was not formed, and was flip-chip mounted on the glass epoxy substrate. The heating temperature was 200 ° C., the pressure was 3 MPa, and the heating and pressing time was 15 seconds. As a result, the element electrode of the semiconductor chip and the electrode terminal plated with electroless gold on the glass epoxy substrate were electrically connected via the gold bump, and the sealing resin was cured.
(Iii) Preparation of a plate-like body composed of a mixture containing an inorganic filler and a thermosetting resin First, the inorganic filler and the thermosetting resin are mixed to adjust the viscosity of the material constituting the plate-like body, if necessary. A small amount of the solvent was added and mixed and adjusted using a mixing stirrer. In this example, a mixture containing 10% by weight of epoxy resin and 90% by weight of silica filler was prepared by stirring for 10 minutes. Next, a plate-like body having a thickness of 100 μm was produced from this mixture by a doctor blade method. Next, after laminating and laminating four sheets of this plate-like body, a plate-like body having a thickness of 400 μm was formed, and then a through-hole having a diameter of 160 μm serving as an inner via was formed using a puncher. The paste was filled by screen printing. The conductive paste used here was 85% by weight of spherical copper particles, 3% by weight of bisphenol A type epoxy resin (“Epicoat 828” manufactured by Yuka Shell Epoxy Co., Ltd.) as a resin component, and glycidyl ester epoxy resin ( 9% by weight of “YD-171” manufactured by Tohto Kasei Co., Ltd.) and 3% by weight of an amine adduct curing agent (“MY-24” manufactured by Ajinomoto Co., Inc.) as a curing agent were kneaded and adjusted using three rolls.
(Iv) Built-in and integration of semiconductor chip Next, a glass epoxy substrate on which the semiconductor chip obtained in (ii) is flip-chip mounted, and a plate shape on which an inner via filled with the conductive paste obtained in (iii) is formed And a glass epoxy substrate for forming the metal wiring on the other main surface of the plate-like body, and two of them are formed by inner vias of the plate-like body so that the semiconductor chip is built in the plate-like body. After aligning the glass epoxy substrate and the plate-like body to be electrically connected, they were integrated by heating and pressing to obtain a semiconductor device having a component built-in module of this example. The heating and pressurization was performed using a hot press machine, the heating temperature was 200 ° C., the pressure was 3 MPa, and the heating and pressing time was 2 hours. The epoxy resin contained in the plate-like body was cured after the viscosity once decreased, and the plate-like body and the glass epoxy substrate were bonded. The epoxy resin contained in the inner via filled with the conductive paste was also cured, and the two glass epoxy substrates were electrically connected through the plate-like body.

このようにして本実施例の半導体装置を作製した。  In this manner, the semiconductor device of this example was manufactured.

比較例として、従来例と同様に前記（ｉ）の工程で、半導体チップが実装される電極端子を含む一面の全部の金属配線の表面に、同様の方法で金層を形成した半導体装置を作製した。  As a comparative example, a semiconductor device in which a gold layer is formed by the same method on the surface of all the metal wirings on one side including the electrode terminals on which the semiconductor chip is mounted is manufactured in the step (i) as in the conventional example. did.

２つの半導体装置の電気接続信頼性の評価は、吸湿リフロー試験によって行なった。具体的な条件は、８５℃、８５％ＲＨ条件下で１６８時間保持した後、最高温度２６０℃であるベルト式リフロー試験機を用いて熱衝撃を加えた。半導体装置の信頼性として、フリップチップ実装の半導体チップの素子電極とガラスエポキシ基板の電極端子との間の接続抵抗値（以下、バンプ抵抗と略）によって評価した。評価基準はバンプ抵抗が吸湿リフロー試験前後で１０％以上変化したものを不良とし、１００個の電気接続点に対する不良発生率で評価した結果、従来の半導体装置では６０％不良が発生したが、本発明の半導体装置では不良は発生しなかった。  The electrical connection reliability of the two semiconductor devices was evaluated by a moisture absorption reflow test. Specifically, after holding for 168 hours at 85 ° C. and 85% RH, thermal shock was applied using a belt-type reflow tester having a maximum temperature of 260 ° C. The reliability of the semiconductor device was evaluated by a connection resistance value (hereinafter abbreviated as bump resistance) between an element electrode of a flip-chip mounted semiconductor chip and an electrode terminal of a glass epoxy substrate. The evaluation standard is that the bump resistance changed by 10% or more before and after the moisture absorption reflow test, and the defect was evaluated as a defect occurrence rate with respect to 100 electrical connection points. As a result, 60% defect occurred in the conventional semiconductor device. No defects occurred in the semiconductor device of the invention.

このように本実施例の半導体装置は、半導体チップが実装される電極端子の表面に金層を形成し、樹脂と接着するその他の金属配線の表面に粗化処理を行なうことで、半導体チップの実装の電気接続信頼性を向上することができる。  As described above, the semiconductor device according to the present embodiment forms a gold layer on the surface of the electrode terminal on which the semiconductor chip is mounted, and performs a roughening process on the surface of the other metal wiring bonded to the resin. The electrical connection reliability of the mounting can be improved.

本発明によれば、半導体チップが実装された半導体装置を信頼性の高い電気接続で製造することができる。  According to the present invention, a semiconductor device on which a semiconductor chip is mounted can be manufactured with highly reliable electrical connection.

本発明は、半導体装置及びその製造方法に関し、とくに電気絶縁性基板の表面に金層が形成された電極端子に半導体チップが実装された半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a semiconductor chip is mounted on an electrode terminal having a gold layer formed on the surface of an electrically insulating substrate, and a manufacturing method thereof.

半導体装置は、情報通信機器、事務用電子機器、家庭用電子機器、測定装置、組み立てロボット等の産業用電子機器、医療用電子機器などの小型化、薄型化、高性能化に大きく寄与している。特に情報通信機器の分野での小型化の要求は大きく、半導体装置の高密度化、高機能化を目指し、半導体チップを積み重ねた構造の積層半導体チップを電気絶縁性基板に実装したものや、電気絶縁性基板の表面に電子部品を実装する従来の２次元的な実装方法から、電気絶縁性基板に電子部品を内蔵し、実装面積を大幅に縮小する３次元的な実装方法の開発が盛んに行なわれている。   Semiconductor devices greatly contribute to the downsizing, thinning, and high performance of industrial electronic devices such as information communication equipment, office electronic devices, home electronic devices, measuring devices, assembly robots, and medical electronic devices. Yes. In particular, there is a great demand for downsizing in the field of information and communication equipment. Aiming at higher density and higher functionality of semiconductor devices, stacked semiconductor chips stacked on an electrically insulating substrate, From the conventional two-dimensional mounting method of mounting electronic components on the surface of an insulating substrate, the development of a three-dimensional mounting method that incorporates electronic components in an electrically insulating substrate and greatly reduces the mounting area has been actively developed. It is done.

半導体装置の作製には、半導体チップとそれを搭載する電気絶縁性基板が必要である。半導体チップを電気絶縁性基板に搭載する実装技術は、大きくは、ワイヤボンディング実装とフリップチップ実装に分けられる。従来からの技術であるワイヤボンディング実装は、図９に示すように、半導体チップ９０１の素子電極９０２が形成された面と反対の面をダイボンディング材９１０を用いて電気絶縁性基板９０４にダイボンディングし、半導体チップの素子電極から電気絶縁性基板の表面に金９０８が形成された電極端子９０６の間を金ワイヤ９０３で電気接続し、半導体チップ、金ワイヤ部分をモールド樹脂９０９で全面的にモールドする方法である。   For manufacturing a semiconductor device, a semiconductor chip and an electrically insulating substrate on which the semiconductor chip is mounted are necessary. Mounting techniques for mounting a semiconductor chip on an electrically insulating substrate can be broadly divided into wire bonding mounting and flip chip mounting. As shown in FIG. 9, wire bonding mounting, which is a conventional technique, is performed by die bonding a surface opposite to the surface on which the element electrode 902 of the semiconductor chip 901 is formed on an electrically insulating substrate 904 using a die bonding material 910. Then, between the element electrode of the semiconductor chip and the electrode terminal 906 on which the gold 908 is formed on the surface of the electrically insulating substrate is electrically connected by the gold wire 903, and the semiconductor chip and the gold wire portion are entirely molded by the molding resin 909. It is a method to do.

一方、半導体チップの実装面積を小さくすることができ、最近、主流となっているフリップチップ実装は、半導体チップの素子電極面を電気絶縁性基板の電極端子に向け、電気接続する方法である。フリップチップ実装は、図１０に示すように、半導体チップ１００１の素子電極１００２と電気絶縁性基板１００４の電極端子１００６をバンプ１００３を介して電気接続する方法で、電気接続部分を封止樹脂１００９が保護している。フリップチップ実装は、封止樹脂の種類、電気接続方式によって、ＡＣＦ(Anisotropic Conductive Film)接続、ＡＣＰ(Anisotropic Conductive Paste)接続といった半導体チップの素子電極と電気絶縁性基板の電極端子間に導電性粒子を介在して接続する方法、ＮＣＦ（Non Conductive Film)接続、ＮＣＰ(Non Conductive Paste)接続、超音波接合といった半導体チップの素子電極と電気絶縁性基板の電極端子同士を直接接触させて電気接続する方法がある。   On the other hand, the mounting area of a semiconductor chip can be reduced, and flip chip mounting, which has become the mainstream in recent years, is a method in which an element electrode surface of a semiconductor chip is directed to an electrode terminal of an electrically insulating substrate and is electrically connected. As shown in FIG. 10, the flip chip mounting is a method in which the element electrodes 1002 of the semiconductor chip 1001 and the electrode terminals 1006 of the electrically insulating substrate 1004 are electrically connected via bumps 1003. Protected. Flip chip mounting is based on the type of encapsulating resin and electrical connection method. Conductive particles between the element electrode of the semiconductor chip such as ACF (Anisotropic Conductive Film) connection and ACP (Anisotropic Conductive Paste) connection and the electrode terminal of the electrically insulating substrate A method of connecting via an electrode, an NCF (Non Conductive Film) connection, an NCP (Non Conductive Paste) connection, an ultrasonic bonding, and the like. There is a way.

通常、ワイヤボンディング実装、フリップチップ実装ともに、電気絶縁性基板の半導体チップ実装面の金属配線には、半導体チップが実装される電極端子を含めて一面に、金メッキ等によって表面に金が形成され、主に表面の清浄性を保つことで、半導体チップと電気絶縁性基板の電極端子との間を良好に電気接続している。   Usually, in both wire bonding mounting and flip chip mounting, the metal wiring on the semiconductor chip mounting surface of the electrically insulating substrate is formed with gold on the surface by gold plating or the like, including the electrode terminals on which the semiconductor chip is mounted, By mainly maintaining the cleanliness of the surface, the semiconductor chip and the electrode terminal of the electrically insulating substrate are electrically connected well.

また、より半導体装置の高密度化、高機能化を実現するために、図１１に示す積層半導体チップを電気絶縁性基板に実装した半導体装置（特許文献１、２）や、図１２に示す電子部品を電気絶縁性基板に内蔵し、内蔵した半導体チップと同一の電気絶縁性基板の層内で、導電性樹脂組成物を充填したインナービアにより電気接続を行い、２次元実装に対し、飛躍的に実装密度を向上させた部品内蔵モジュール（特許文献３）がある。また、特許文献４に示すように、半導体チップがフリップチップ実装された半導体装置において、半導体チップと電気絶縁性基板間に補強用の金属配線を形成する提案もある。   In order to realize higher density and higher functionality of the semiconductor device, a semiconductor device (Patent Documents 1 and 2) in which the laminated semiconductor chip shown in FIG. 11 is mounted on an electrically insulating substrate, or an electronic device shown in FIG. Incorporating components in an electrically insulating substrate, and making electrical connections with inner vias filled with a conductive resin composition within the same electrically insulating substrate layer as the embedded semiconductor chip, a dramatic improvement over 2D packaging There is a component built-in module (Patent Document 3) with improved mounting density. In addition, as shown in Patent Document 4, there is a proposal of forming a reinforcing metal wiring between a semiconductor chip and an electrically insulating substrate in a semiconductor device on which a semiconductor chip is flip-chip mounted.

しかし、ワイヤボンディング実装及びフリップチップ実装に通常必須となる電気絶縁性基板の金属配線の表面の金層は、電気接続の信頼性に悪影響を及ぼすことがある。金層は、酸化されず清浄であり、またワイヤボンディング実装に用いる金ワイヤや、フリップチップ実装時の半導体チップのバンプを圧着するのに適度な柔軟性をもち、良好な半導体チップと電気絶縁性基板の電極端子との間の電気接続を行ないやすいが、一方で、金層は平滑で樹脂との接着性が悪く、例えば銅表面のように表面の粗化処理によって簡単に樹脂との接着性を大きくすることが難しいという課題があった。   However, the gold layer on the surface of the metal wiring of the electrically insulating substrate, which is usually essential for wire bonding mounting and flip chip mounting, may adversely affect the reliability of electrical connection. The gold layer is clean and not oxidized, and has good flexibility for crimping gold wires used for wire bonding mounting and bumps of semiconductor chips during flip chip mounting, and good semiconductor chip and electrical insulation It is easy to make electrical connection with the electrode terminals on the board, but on the other hand, the gold layer is smooth and has poor adhesion to the resin. For example, the adhesion to the resin can be easily achieved by roughening the surface, such as the copper surface. There was a problem that it was difficult to increase the size.

この金層の特性に起因する半導体装置の課題として、第１番目にＡＣＦ接続、ＡＣＰ接続、ＮＣＦ接続、ＮＣＰ接続、超音波接合のような、半導体チップの素子電極に形成した金バンプと電気絶縁性基板の金属配線の金層を圧接によって電気接続するフリップチップ実装において、半導体チップの金バンプと電気絶縁性基板の金属配線の金層との接触、電気接続部分を物理的に保持するために半導体チップと電気絶縁性基板の間に配置される封止樹脂と電気絶縁性基板との接着性が悪く、例えば吸湿リフロー試験のような半導体パッケージの信頼性試験において熱衝撃が加えられると、容易に封止樹脂、電気絶縁性基板間が剥離し、剥離した界面が電気接続部分にも拡大し接続部の電気接続不良を起こす原因になるという課題があった。   As a problem of the semiconductor device due to the characteristics of the gold layer, first, gold bumps formed on element electrodes of a semiconductor chip, such as ACF connection, ACP connection, NCF connection, NCP connection, and ultrasonic bonding, are electrically insulated. In flip chip mounting, where the gold layer of the metal wiring on the conductive substrate is electrically connected by pressure contact, the contact between the gold bump of the semiconductor chip and the gold layer of the metal wiring of the electrically insulating substrate, to physically hold the electrical connection portion Adhesion between the sealing resin and the electrically insulating substrate disposed between the semiconductor chip and the electrically insulating substrate is poor, and it is easy to apply a thermal shock in a semiconductor package reliability test such as a moisture absorption reflow test. In other words, the sealing resin and the electrically insulating substrate are peeled off, and the peeled interface expands to the electrical connection portion, causing an electrical connection failure in the connection portion.

第２番目に、金ワイヤを用いて半導体チップの素子電極と電気絶縁性基板の金属配線の金層を電気接続し、半導体チップと金ワイヤを含めて、モールド樹脂でモールドするワイヤボンディング実装において、金ワイヤと金属配線の金層の接触部分、及び金ワイヤの形状を維持し、保護するためのモールド樹脂が、吸湿リフロー試験において熱衝撃が加えられると、ワイヤボンディング実装の形態においてはモールド樹脂、電気絶縁性基板間が容易に剥離し、同様にこの剥離した界面が発端となって電気接続不良を起こす原因になるという課題があった。   Second, in wire bonding mounting in which the element electrode of the semiconductor chip and the gold layer of the metal wiring of the electrically insulating substrate are electrically connected using a gold wire, and the semiconductor chip and the gold wire are molded with a molding resin. When the thermal shock is applied in the moisture absorption reflow test when the mold resin for maintaining and protecting the contact portion of the gold layer and the gold layer of the metal wiring and the shape of the gold wire is molded resin in the form of wire bonding mounting, There was a problem that the electrically insulating substrates were easily separated, and similarly, the separated interface was the origin and caused electrical connection failure.

第３番目に、複数の半導体チップを積層した積層半導体チップを電気絶縁性基板の電極端子にワイヤボンディング実装、もしくはワイヤボンディング実装とフリップチップ実装によって電気接続した形態でも、吸湿リフロー試験において、第１〜２番目の例と同様にワイヤボンディング実装のモールド樹脂やフリップチップ実装の封止樹脂の電気絶縁性基板との接着力不足に起因する剥離が生じ、半導体実装の電気接続不良が発生しやすいという課題があった。   Third, even in a form in which a laminated semiconductor chip in which a plurality of semiconductor chips are stacked is electrically connected to an electrode terminal of an electrically insulating substrate by wire bonding mounting or wire bonding mounting and flip chip mounting, ~ Similar to the second example, peeling due to insufficient adhesion of the mold resin for wire bonding mounting and the sealing resin for flip chip mounting to the electrically insulating substrate is likely to cause poor electrical connection in semiconductor mounting. There was a problem.

第４番目にフリップチップ実装された半導体を内蔵した部品内蔵モジュールの形態では、通常の半導体チップの実装形態のように表面に露出しておらず、電気絶縁性基板に内蔵されている。そのため、吸湿リフロー試験において熱衝撃が加えられると、半導体チップと電気絶縁性基板間に、第１〜３番目の例以上に、より大きな剥離応力が加えられ、容易に封止樹脂、電気絶縁性基板間が剥離し、電気接続不良を起こす原因となるという課題があった。また、電気絶縁性基板の金属配線の表面金層が平滑で非常に樹脂が滑りやすいため、部品内蔵モジュールに形成された導電性樹脂組成物からなる導電性ペーストが充填されたインナービアが滑って位置ずれを起こしやすいという課題があった。さらに導電性ペースト中の熱硬化性樹脂と金層との充分な接着性を得ることが難しく、容易に導電性ペーストが充填されたインナービアの剥離断線が起きやすかった。   In the form of a component built-in module that contains a fourth flip-chip mounted semiconductor, it is not exposed on the surface as in the case of a normal semiconductor chip mounting, but is built in an electrically insulating substrate. Therefore, when a thermal shock is applied in the moisture absorption reflow test, a larger peeling stress is applied between the semiconductor chip and the electrically insulating substrate than in the first to third examples, and the sealing resin and the electrical insulating property can be easily applied. There was a problem that the substrates were peeled off, causing electrical connection failure. Also, since the surface gold layer of the metal wiring of the electrically insulating substrate is smooth and the resin is very slippery, the inner via filled with the conductive paste made of the conductive resin composition formed on the component built-in module slips. There was a problem that it was easy to cause a positional shift. Furthermore, it was difficult to obtain sufficient adhesion between the thermosetting resin and the gold layer in the conductive paste, and the inner vias filled with the conductive paste were easily peeled off.

また、上記の課題は、金層の金属配線の面積に依存しやすく、同一作製条件でも、電気絶縁性基板の金属配線の設計パターンで信頼性が変わることがあり、確実な信頼性確保が非常に難しかった。   In addition, the above problem is likely to depend on the area of the metal wiring of the gold layer, and the reliability may vary depending on the design pattern of the metal wiring of the electrically insulating substrate even under the same manufacturing conditions. It was difficult.

また、特許文献４に示すように、半導体チップがフリップチップ実装された半導体装置において、半導体チップと電気絶縁性基板間に補強用の金属配線を形成する手法もあるが、余分な金属配線が必要となるため、金属配線の設計パターンの自由度が減るという問題を含んでいた。
特開２０００−３４９２２８号公報 特開２００４−２２８３２３号公報 特開平１１−２２０２６２号公報 特開２００４−１５３２１０号公報 In addition, as shown in Patent Document 4, in a semiconductor device in which a semiconductor chip is flip-chip mounted, there is a method of forming a reinforcing metal wiring between the semiconductor chip and the electrically insulating substrate, but an extra metal wiring is required. Therefore, there is a problem that the degree of freedom of the metal wiring design pattern is reduced.
JP 2000-349228 A JP 2004-228323 A Japanese Patent Laid-Open No. 11-220262 JP 2004-153210 A

本発明は、前記従来の問題を解決するため、半導体チップが実装された半導体装置の電気接続の信頼性を向上させた半導体装置及びその製造方法を提供する。   In order to solve the above-described conventional problems, the present invention provides a semiconductor device in which the reliability of electrical connection of a semiconductor device mounted with a semiconductor chip is improved, and a method for manufacturing the same.

本発明の半導体装置は、複数の金属配線を備えた電気絶縁性基板の表面に半導体チップが実装され、少なくとも前記複数の金属配線の一部を樹脂が覆っている半導体装置であって、前記電気絶縁性基板に形成された複数の金属配線のうち、少なくとも前記半導体チップと電気的に接続される金属配線の表面には金層を形成し、前記電気絶縁性基板に形成された複数の金属配線のうち、前記樹脂と接触する金属配線の表面には粗化部を形成することを特徴とする。   The semiconductor device of the present invention is a semiconductor device in which a semiconductor chip is mounted on the surface of an electrically insulating substrate having a plurality of metal wirings, and at least a part of the plurality of metal wirings is covered with a resin. Among the plurality of metal wirings formed on the insulating substrate, a gold layer is formed on at least the surface of the metal wiring electrically connected to the semiconductor chip, and the plurality of metal wirings formed on the electric insulating substrate Of these, a roughened portion is formed on the surface of the metal wiring in contact with the resin.

本発明の半導体装置の製造方法は、半導体チップと、前記半導体チップがフリップチップ実装される電極端子を含む複数の粗化処理された表面の金属配線が形成された主面をもつ電気絶縁性基板とを準備する工程（ａ）と、フォトリソグラフィー法によって、前記電気絶縁性基板の前記半導体チップがフリップチップ実装される主面の、前記電極端子以外の部分に、フォトレジストを形成する工程（ｂ）と、前記電気絶縁性基板のフリップチップ実装される主面に無電解金メッキを行なって、前記電極端子表面に金を形成した後、フォトレジストを除去する工程（ｃ）と、前記半導体チップの素子電極面と前記電気絶縁性基板の電極端子面との間に封止樹脂を介して、前記半導体チップを前記電気絶縁性基板にフリップチップ実装する工程（ｄ）とを含むことを特徴とする。   A method of manufacturing a semiconductor device according to the present invention includes a semiconductor chip and an electrically insulating substrate having a main surface on which a plurality of roughened metal wirings including electrode terminals on which the semiconductor chip is flip-chip mounted are formed. And (b) forming a photoresist on a portion other than the electrode terminals on the main surface of the electrically insulating substrate on which the semiconductor chip is flip-chip mounted by a photolithography method (b) And (c) removing the photoresist after forming gold on the surface of the electrode terminal by performing electroless gold plating on the main surface of the electrically insulating substrate to be flip-chip mounted; and A step of flip-chip mounting the semiconductor chip on the electrically insulating substrate via a sealing resin between the element electrode surface and the electrode terminal surface of the electrically insulating substrate ( Characterized in that it comprises a) and.

本発明の別の半導体装置の製造方法は、半導体チップと、前記半導体チップがワイヤボンディング実装される電極端子を含む複数の粗化処理された表面の金属配線が形成された主面をもつ電気絶縁性基板とを準備する工程（ａ）と、フォトリソグラフィー法によって、前記電気絶縁性基板の前記半導体チップがワイヤボンディング実装される主面の、前記電極端子以外の部分に、フォトレジストを形成する工程（ｂ）と、前記電気絶縁性基板のワイヤボンディング実装される主面に無電解金メッキを行なって、前記電極端子表面に金を形成した後、フォトレジストを除去する工程（ｃ）と、前記半導体チップの素子電極が形成されている面の反対の主面を前記電気絶縁性基板に接合する工程（ｄ）と、前記半導体チップを前記電気絶縁性基板にワイヤボンディング実装する工程（ｅ）と、前記半導体チップと前記ワイヤボンディング実装部分を樹脂モールドする工程（ｆ）とを含むことを特徴とする。   According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a semiconductor chip; and an electrical insulation having a main surface on which a plurality of roughened surface metal wirings including electrode terminals on which the semiconductor chip is wire bonded and mounted are formed. A step of preparing a conductive substrate, and a step of forming a photoresist on a portion other than the electrode terminals on a main surface of the electrically insulating substrate on which the semiconductor chip is wire-bonded and mounted by photolithography. (B), a step (c) of removing the photoresist after performing electroless gold plating on the main surface of the electrically insulating substrate to be wire-bonded and mounted to form the electrode terminal surface, and the semiconductor A step (d) of bonding a main surface opposite to a surface on which an element electrode of a chip is formed to the electrically insulating substrate; and the semiconductor chip is bonded to the electrically insulating substrate. A wire bonding mounting to step (e), the semiconductor chip and the wire bonding mounting portion, characterized in that it comprises a step of resin molding (f).

本発明のさらに別の半導体装置の製造方法は、半導体チップと、前記半導体チップがフリップチップ実装される電極端子を含む複数の粗化処理された表面の金属配線が形成された主面をもつ第１の電気絶縁性基板と、複数の金属配線が形成された主面をもつ第２の電気絶縁性基板と、無機フィラーと熱硬化性樹脂とを含む混合物からなる第３の電気絶縁性基板である板状体を準備する工程（ａ）と、フォトリソグラフィー法によって、前記第１の電気絶縁性基板の前記半導体チップがフリップチップ実装される主面の、前記電極端子以外の部分に、フォトレジストを形成する工程（ｂ）と、前記第１の電気絶縁性基板のフリップチップ実装される主面に無電解金メッキを行なって、前記電極端子表面に金を形成した後、フォトレジストを除去する工程（ｃ）と、前記半導体チップの素子電極面と前記電気絶縁性基板の電極端子面との間に封止樹脂を介して、前記半導体チップを前記電気絶縁性基板にフリップチップ実装する工程（ｄ）と、前記板状体に貫通孔を形成し、前記貫通孔に導電性樹脂組成物からなる導電性ペーストを充填する工程（ｅ）と、前記第１と第２の電気絶縁性基板及び前記板状体を、前記板状体の一方の主面に前記第１の電気絶縁性基板の前記半導体チップがフリップチップ実装された主面が向くように、もう一方の主面に前記第２の電気絶縁性基板の金属配線が形成された主面が向くように位置あわせし、積層する工程（ｆ）と、加熱加圧して、前記第１と第２の電気絶縁性基板を前記板状体に接着し、前記半導体チップを前記板状体に埋設して一体化し、前記板状体及び前記導電性樹脂組成物からなる導電性ペーストを硬化させる工程（ｇ）とを含むことを特徴とする。   According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device having a main surface on which a plurality of roughened surface metal wirings including a semiconductor chip and electrode terminals on which the semiconductor chip is flip-chip mounted are formed. A third electrically insulating substrate made of a mixture comprising an electrically insulating substrate, a second electrically insulating substrate having a main surface on which a plurality of metal wirings are formed, and an inorganic filler and a thermosetting resin; Step (a) of preparing a plate-like body, and a photoresist on a portion other than the electrode terminals on the main surface of the first electrically insulating substrate on which the semiconductor chip is flip-chip mounted by photolithography. And forming the gold on the electrode terminal surface by performing electroless gold plating on the flip chip mounted main surface of the first electrically insulating substrate, and then removing the photoresist (C) and flip-chip mounting the semiconductor chip on the electrically insulating substrate via a sealing resin between the element electrode surface of the semiconductor chip and the electrode terminal surface of the electrically insulating substrate (D), a step (e) of forming a through hole in the plate-like body, and filling the through hole with a conductive paste made of a conductive resin composition, and the first and second electrically insulating substrates. The plate-like body is placed on the other main surface so that the main surface on which the semiconductor chip of the first electrically insulating substrate is flip-chip mounted faces one main surface of the plate-like body. Step (f) of aligning and laminating the main surface on which the metal wiring of the electrically insulating substrate of 2 is formed, and laminating and heating and pressing the first and second electrically insulating substrates to the plate Adhering to a body, the semiconductor chip is embedded in the plate body and integrated, Comprise a serial plate-like body and curing the conductive paste comprising the conductive resin composition (g) and said.

本発明によれば、半導体チップが実装された半導体装置を信頼性の高い電気接続で製造することができる。   According to the present invention, a semiconductor device on which a semiconductor chip is mounted can be manufactured with highly reliable electrical connection.

本発明の半導体装置は、半導体チップが実装された電気絶縁性基板の金属配線において、半導体チップが実装された電極端子の表面に金層を形成し、その他の金属配線には金層を形成せず表面を粗化することで、フリップチップ実装における封止樹脂と電気絶縁性基板間、ワイヤボンディング実装におけるモールド樹脂と電気絶縁性基板間の接着強度を大きくしたものである。接着強度を大きくすることで、吸湿リフロー試験等の信頼性試験における電気接続の信頼性を向上させることができる。また、フリップチップ実装における封止樹脂部分、ワイヤボンディング実装におけるモールド樹脂部分の電気絶縁性基板の金属配線の設計パターンが、電気接続信頼性へ与える影響を低減することができる。   In the semiconductor device of the present invention, in the metal wiring of the electrically insulating substrate on which the semiconductor chip is mounted, a gold layer is formed on the surface of the electrode terminal on which the semiconductor chip is mounted, and the gold layer is not formed on the other metal wiring. By roughening the surface, the adhesive strength between the sealing resin and the electrically insulating substrate in flip chip mounting and between the mold resin and the electrically insulating substrate in wire bonding mounting is increased. By increasing the adhesive strength, the reliability of electrical connection in a reliability test such as a moisture absorption reflow test can be improved. Moreover, the influence which the design pattern of the metal wiring of the electrically insulating board | substrate of the sealing resin part in flip chip mounting and the mold resin part in wire bonding mounting has on electrical connection reliability can be reduced.

また、複数の半導体チップを積層した積層半導体チップを電気絶縁性基板にワイヤボンディング実装、もしくはワイヤボンディング実装とフリップチップ実装によって電気接続した形態において、ワイヤボンディング実装のモールド樹脂と電気絶縁性基板間やフリップチップ実装の封止樹脂と電気絶縁性基板間の接着強度を大きくし、吸湿リフロー試験等の信頼性試験における信頼性を向上させることができる。積層半導体チップの形態では、一枚の半導体チップに比べ、樹脂との接着面数や面積が多くなり、また形状的にコーナー部や半導体チップ間の積層界面等に局所的により大きな応力がかかりやすい。そのため、積層半導体チップの実装信頼性の確保は、通常の一枚の半導体チップの実装信頼性の確保以上に難しいものであったが、電気絶縁性基板の実装面の接着強度を大きくすることで、積層半導体チップの実装信頼性を改善することができる。   Also, in a form in which a laminated semiconductor chip in which a plurality of semiconductor chips are stacked is electrically connected to an electrically insulating substrate by wire bonding mounting or wire bonding mounting and flip chip mounting, the wire bonding mounting between the mold resin and the electrically insulating substrate The adhesive strength between the flip-chip mounting sealing resin and the electrically insulating substrate can be increased, and the reliability in a reliability test such as a moisture absorption reflow test can be improved. In the form of the laminated semiconductor chip, the number and area of the adhesive surface with the resin are larger than that of a single semiconductor chip, and a larger stress is likely to be applied locally to the corner portion or the laminated interface between the semiconductor chips due to the shape. . For this reason, securing the mounting reliability of the laminated semiconductor chip was more difficult than securing the mounting reliability of a single semiconductor chip, but by increasing the adhesive strength of the mounting surface of the electrically insulating substrate. The mounting reliability of the laminated semiconductor chip can be improved.

また、フリップチップ実装された半導体を内蔵した部品内蔵モジュールの形態において、フリップチップ実装の封止樹脂と電気絶縁性基板間の接着強度を向上させ、表面実装された半導体チップより封止樹脂と電気絶縁性基板間の剥離応力が大きく、信頼性の高い電気接続の実現が難しい部品内蔵モジュールの形態の半導体装置の吸湿リフロー試験等の信頼性試験における電気接続信頼性を向上させることができる。また、部品内蔵モジュールに形成された導電性樹脂組成物が充填されたインナービアの電気接続される金属配線の表面が粗化処理されているので、平滑で樹脂が滑りやすい金層で発生しやすいインナービアの位置ずれを抑制することができ、またインナービアと金属配線との接着強度が大きくなるため、各種の信頼性試験において、剥離の発生がなく、高信頼な電気接続を保つことができる。   Also, in the form of a component built-in module containing a flip-chip mounted semiconductor, the adhesive strength between the flip-chip mounting sealing resin and the electrically insulating substrate is improved, and the sealing resin and electrical It is possible to improve electrical connection reliability in a reliability test such as a moisture absorption reflow test of a semiconductor device in the form of a component built-in module in which peeling stress between insulating substrates is large and it is difficult to realize highly reliable electrical connection. Moreover, since the surface of the metal wiring electrically connected to the inner via filled with the conductive resin composition formed in the component built-in module is roughened, it is easy to generate a smooth and slippery gold layer. The displacement of the inner vias can be suppressed, and the adhesive strength between the inner vias and the metal wiring is increased. Therefore, in various reliability tests, no peeling occurs and a highly reliable electrical connection can be maintained. .

半導体チップが実装される電気絶縁性基板の電極端子を含む一部の金属配線の表面に金層が形成されており、他の金属配線の表面に金層が形成されておらず、粗化処理されている形態が好ましい。金属配線の表面の選択的な金層の形成を行なうことができる。半導体チップの実装のために金層の形成が必須の電極端子を除いて、金層の形成を行なう金属配線表面の選択は、簡単な設計パターンで金層形成のフォトレジストを形成できるように、また、半導体チップの実装の電気接続信頼性が悪化しない面積であるよう、選択するのがよい。   A gold layer is formed on the surface of some of the metal wiring including the electrode terminals of the electrically insulating substrate on which the semiconductor chip is mounted, and no gold layer is formed on the surface of the other metal wiring. The form is preferred. A selective gold layer can be formed on the surface of the metal wiring. With the exception of electrode terminals that require the formation of a gold layer for mounting a semiconductor chip, the selection of the metal wiring surface on which the gold layer is to be formed can be used to form a gold layer-forming photoresist with a simple design pattern. Further, it is preferable to select an area that does not deteriorate the electrical connection reliability of the mounting of the semiconductor chip.

電極端子表面の金層の形成方法は、無電解メッキ、電解メッキ、蒸着、又はスパッタのいずれかが好ましい。既存の金層の形成技術をそのまま用いて本発明の半導体装置を作製することができる。特に、蒸着、スパッタはドライプロセスで形成することができ、簡易な手法としてより好ましい。   The method for forming the gold layer on the electrode terminal surface is preferably any one of electroless plating, electrolytic plating, vapor deposition, and sputtering. The semiconductor device of the present invention can be manufactured using an existing gold layer forming technique as it is. In particular, vapor deposition and sputtering can be formed by a dry process, which is more preferable as a simple method.

フリップチップ実装は、ACF(Anisotropic Conductive Film),ACP(Anisotropic Conductive Paste),NCF(Non Conductive Film),NCP(Non Conductive Paste)のいずれかを用いた熱圧着工法、又は半導体チップの素子電極に形成された金バンプと電気絶縁性基板の電極端子表面に形成された金の超音波接合によって行なわれることが好ましい。既存のフリップチップ実装技術をそのまま用いることができる。また、上記の既存のフリップチップ実装技術のみに限定されるのでなく、電気絶縁性基板の半導体チップを実装する電極端子に金配線を用い、封止樹脂、モールド樹脂等によって実装部を保護する形態の実装技術には、同様の効果を得ることができる。   Flip chip mounting is formed on the thermocompression bonding method using any of ACF (Anisotropic Conductive Film), ACP (Anisotropic Conductive Paste), NCF (Non Conductive Film), NCP (Non Conductive Paste), or on the element electrode of a semiconductor chip. Preferably, this is performed by ultrasonic bonding of the gold bumps formed on the electrode terminal surface of the electrically insulating substrate. Existing flip chip mounting technology can be used as it is. Also, the present invention is not limited to the above existing flip chip mounting technology, and a form in which gold wiring is used for an electrode terminal for mounting a semiconductor chip on an electrically insulating substrate and the mounting portion is protected by a sealing resin, a mold resin, or the like. The same effect can be obtained in the mounting technology.

配線は粗化した銅とすることが好ましい。銅配線基板は、安価に作製することができ、多種多様な市販品を入手しやすい。また、表面の粗化処理を行ないやすい。銅以外にも銅を含む合金であっても良い。粗化した銅箔は市販品を用いてもよいし、平滑な銅箔をエッチング液によるエッチング処理、プラズマ処理、研磨剤による研磨処理、電解などの処理により形成できる。   The wiring is preferably roughened copper. The copper wiring board can be manufactured at low cost, and a wide variety of commercially available products are easily available. Moreover, it is easy to roughen the surface. An alloy containing copper other than copper may be used. A commercially available product may be used as the roughened copper foil, or a smooth copper foil may be formed by an etching process using an etching solution, a plasma process, a polishing process using an abrasive, or an electrolysis process.

前記第３の電気絶縁性基板は、無機フィラーと熱硬化性樹脂とを含む混合物からなることが好ましい。また第１〜３に含まれる熱可塑性樹脂は同一の材料としてもよい。これにより、電気絶縁性基板１、３間及び２、３間の樹脂同士の接着強度を大きくすることで、それぞれの電気絶縁性基板の接着面の接着強度を大きくし、吸湿リフロー試験等の信頼性試験において、電気接続の信頼性を向上させることができる。また、異なる材料の異種積層の形態からなる半導体装置に比べ、応力が小さくなることで、電気接続の信頼性が向上する効果がある。   The third electrically insulating substrate is preferably made of a mixture containing an inorganic filler and a thermosetting resin. The thermoplastic resins included in the first to third may be the same material. As a result, the adhesive strength between the electrically insulating substrates 1 and 3 and between the resins 2 and 3 is increased, thereby increasing the adhesive strength of the adhesive surfaces of the respective electrically insulating substrates, and reliability such as a moisture absorption reflow test. In the reliability test, the reliability of the electrical connection can be improved. In addition, since the stress is reduced as compared with a semiconductor device formed of different layers of different materials, there is an effect of improving the reliability of electrical connection.

無機フィラーは７０重量％〜９５重量％含まれることが好ましい。９５重量％以上であると、粉体量に対し、液体量が少なすぎ、シート化することが難しい。また、７０重量％以下であると、無機フィラーを混合したことによる放熱性の向上等の効果が少なくなる。加熱加圧して半導体チップを電気絶縁性基板に内蔵する時に、半導体チップに損傷を与えない粘度であれば、無機フィラーの配合率は大きい方がより好ましい。   The inorganic filler is preferably contained in an amount of 70% to 95% by weight. If it is 95% by weight or more, the amount of liquid is too small relative to the amount of powder, making it difficult to form a sheet. On the other hand, when it is 70% by weight or less, effects such as improvement of heat dissipation due to mixing of the inorganic filler are reduced. When the viscosity is such that the semiconductor chip is not damaged when the semiconductor chip is built in the electrically insulating substrate by heating and pressurizing, it is more preferable that the blending ratio of the inorganic filler is large.

無機フィラーは、Ａｌ2Ｏ3、ＭｇＯ、ＢＮ、ＡｌＮ及びＳｉＯ2から選ばれる少なくとも一つの無機フィラーであることが好ましい。これらの無機フィラーを用いることで、放熱性に優れた半導体装置となる。また、無機フィラーとして、ＳｉＯ2を用いた場合、誘電率を小さくすることができる。 The inorganic filler is preferably at least one inorganic filler selected from Al 2 O 3 , MgO, BN, AlN and SiO 2 . By using these inorganic fillers, a semiconductor device having excellent heat dissipation is obtained. Further, when SiO 2 is used as the inorganic filler, the dielectric constant can be reduced.

熱硬化性樹脂は、エポキシ樹脂、フェノール樹脂、及びシアネート樹脂から選ばれる少なくとも一つの熱硬化性樹脂であることが好ましい。これらの樹脂は多種多様な種類が市販されており、これらの樹脂を用いることで耐熱性や電気絶縁性に優れた半導体装置となる。   The thermosetting resin is preferably at least one thermosetting resin selected from an epoxy resin, a phenol resin, and a cyanate resin. A wide variety of these resins are commercially available, and by using these resins, a semiconductor device having excellent heat resistance and electrical insulation can be obtained.

導電性樹脂組成物は金、銀、銅、及びニッケルから選ばれる少なくとも一つの金属を含む金属粒子を導電性成分として含み、エポキシ樹脂を樹脂成分として含むことが好ましい。上記金属は電気抵抗が低く、また、エポキシ樹脂は、耐熱性や電気絶縁性に優れているからである。特に、銅粉をコア材に表面を銀でコートした金属粒子は、機械的強度が強く安価である銅粉と酸化しにくい銀粉の両方の特性を併せもち、好適である。   The conductive resin composition preferably contains metal particles containing at least one metal selected from gold, silver, copper, and nickel as a conductive component, and an epoxy resin as a resin component. This is because the metal has a low electrical resistance, and the epoxy resin is excellent in heat resistance and electrical insulation. In particular, metal particles obtained by coating copper powder on a core material with silver on the surface are suitable because they have both characteristics of copper powder having high mechanical strength and low cost and silver powder that is difficult to oxidize.

本発明の製造方法においては、半導体チップと、前記半導体チップがフリップチップ実装される電極端子を含む複数の表面に粗化処理が行なわれた金属配線が形成された主面をもつ電気絶縁性基板とを準備する工程（ａ）と、フォトリソグラフィー法によって、前記電気絶縁性基板の前記半導体チップがフリップチップ実装される主面の、前記電極端子以外の部分に、フォトレジストを形成する工程（ｂ）と、前記電気絶縁性基板のフリップチップ実装される主面に無電解金メッキを行なって前記電極端子表面に金を形成した後、フォトレジストを除去する工程（ｃ）と、前記半導体チップの素子電極面と前記電気絶縁性基板の電極端子面との間に封止樹脂を介して、前記半導体チップを前記電気絶縁性基板にフリップチップ実装する工程（ｄ）とを含むのが好ましい。既存のフリップチップ実装技術とフォトリソグラフィー法をそのまま使用することができ、本発明の信頼性の高い半導体装置を作製することができる。   In the manufacturing method of the present invention, an electrically insulating substrate having a main surface on which a plurality of surfaces including a semiconductor chip and an electrode terminal on which the semiconductor chip is flip-chip mounted is provided with a roughened metal wiring. And (b) forming a photoresist on a portion other than the electrode terminals on the main surface of the electrically insulating substrate on which the semiconductor chip is flip-chip mounted by a photolithography method (b) And (c) removing the photoresist after forming gold on the surface of the electrode terminal by performing electroless gold plating on the flip-chip mounted main surface of the electrically insulating substrate, and the element of the semiconductor chip A step of flip-chip mounting the semiconductor chip on the electrically insulating substrate via a sealing resin between the electrode surface and the electrode terminal surface of the electrically insulating substrate ( ) And preferably includes a. Existing flip chip mounting technology and photolithography can be used as they are, and a highly reliable semiconductor device of the present invention can be manufactured.

また、半導体チップと、前記半導体チップがワイヤボンディング実装される電極端子を含む複数の表面に粗化処理が行なわれた金属配線が形成された主面をもつ電気絶縁性基板とを準備する工程（ａ）と、フォトリソグラフィー法によって、前記電気絶縁性基板の前記半導体チップがワイヤボンディング実装される主面の、前記電極端子以外の部分に、フォトレジストを形成する工程（ｂ）と、前記電気絶縁性基板のワイヤボンディング実装される主面に無電解金メッキを行なって前記電極端子表面に金を形成した後、フォトレジストを除去する工程（ｃ）と、前記半導体チップの素子電極が形成されている面の反対の主面を前記電気絶縁性基板に接合する工程（ｄ）と、前記半導体チップを前記電気絶縁性基板にワイヤボンディング実装する工程（ｅ）と、前記半導体チップと前記ワイヤボンディング実装部分を樹脂モールドする工程（ｆ）とを含むのが好ましい。既存のワイヤボンディング実装技術とフォトリソグラフィー法をそのまま使用することができ、本発明の信頼性の高い半導体装置を作製することができる。   A step of preparing a semiconductor chip and an electrically insulating substrate having a main surface on which a plurality of surfaces including a metal wire subjected to a roughening process are formed, including electrode terminals on which the semiconductor chip is wire-bonded and mounted ( a), a step (b) of forming a photoresist on a portion other than the electrode terminals on a main surface of the electrically insulating substrate on which the semiconductor chip is wire-bonded and mounted by photolithography, and the electrical insulation Forming a gold on the electrode terminal surface by performing electroless gold plating on the main surface of the conductive substrate to be wire-bonded and mounted, and then removing the photoresist (c), and the element electrode of the semiconductor chip is formed A step (d) of bonding a main surface opposite to the surface to the electrically insulating substrate; and wire bonding mounting the semiconductor chip to the electrically insulating substrate. And step (e), preferably contains said semiconductor chip and the wire bonding mounting portions to the resin molding step (f). Existing wire bonding mounting technology and photolithography can be used as they are, and a highly reliable semiconductor device of the present invention can be manufactured.

また、複数の半導体チップが積層された積層半導体チップをワイヤボンディング実装、もしくはフリップチップ実装及びワイヤボンディング実装によって前記電気絶縁性基板に実装したものである。積層半導体チップを実装した形態の作製は、２段の高さの異なるワイヤボンディング実装を行なったり、ワイヤボンディング実装とフリップチップ実装の２種の実装を行なったり、非常に複雑な作製工程となり、既存の技術をそのまま用いて信頼性の高い半導体装置を作製することができる。   Also, a laminated semiconductor chip in which a plurality of semiconductor chips are laminated is mounted on the electrically insulating substrate by wire bonding mounting, or flip chip mounting and wire bonding mounting. Fabrication of a form in which a laminated semiconductor chip is mounted is a very complicated fabrication process, such as wire bonding mounting with two different heights, or wire bonding mounting and flip chip mounting. A highly reliable semiconductor device can be manufactured using this technique as it is.

また、導電性ペーストが充填されたインナービアと電気接続される金属配線が粗化されているため、加熱加圧工程において、半導体チップを板状体に埋設する際に、板状体を構成する熱硬化性樹脂の流動に抗してインナービアの位置ずれが起きにくい。このため、半導体チップにより近い領域にインナービアを形成したり、より狭ピッチにインナービアを配置したりすることができる。   Further, since the metal wiring electrically connected to the inner via filled with the conductive paste is roughened, the plate-like body is formed when the semiconductor chip is embedded in the plate-like body in the heating and pressing step. The inner via is less likely to be displaced against the flow of the thermosetting resin. For this reason, inner vias can be formed in a region closer to the semiconductor chip, or inner vias can be arranged at a narrower pitch.

電気絶縁性基板の電極端子表面の金の形成方法は、電解メッキ、蒸着、又はスパッタのいずれかからなることが好ましい。既存の技術をそのまま使用して、電極端子表面への金の形成を行なうことができる。また、蒸着、スパッタによる電極端子表面への金の形成では、メッキのように薬品を使わないため、薬液の処理の必要がなく、簡単なドライプロセスで行なうことができる。   The method for forming gold on the electrode terminal surface of the electrically insulating substrate is preferably one of electrolytic plating, vapor deposition, and sputtering. The existing technology can be used as it is, and gold can be formed on the electrode terminal surface. Further, in the formation of gold on the electrode terminal surface by vapor deposition or sputtering, since no chemical is used unlike plating, there is no need for chemical treatment, and a simple dry process can be performed.

本発明において、前記金を形成しない金属配線表面の粗化の程度は、ＪＩＳ Ｂ ０６０１に規定の十点平均粗さＲｚにおいて、１〜１０μｍの範囲が好ましく、より好ましくは３〜６μｍの範囲である。前記範囲であれば、樹脂との接着性を高く維持できる。ここでＪＩＳ Ｂ ０６０１に規定の十点平均粗さ(ten point average height, peak to valley average)は、任意の基準長さの粗さ曲線において、その平均線から高いほうの５個の山及び低いほうの５個の谷間での距離を平均した値の差で算出する（単位はμｍ）。   In the present invention, the degree of roughening of the surface of the metal wiring not forming the gold is preferably in the range of 1 to 10 μm, more preferably in the range of 3 to 6 μm, in the ten-point average roughness Rz defined in JIS B 0601. is there. If it is the said range, adhesiveness with resin can be maintained highly. Here, the ten point average height (peak to valley average) specified in JIS B 0601 is the highest five peaks and low in the roughness curve of an arbitrary reference length. The difference between the average values of the distances between the five valleys is calculated (unit: μm).

本発明によれば、半導体チップが実装された半導体装置において、電気絶縁性基板の金属配線の半導体チップが実装される電極端子の表面に金層が形成され、その他の金属配線の表面を粗化することにより、電気絶縁性基板の半導体チップ実装面とフリップチップ実装の封止樹脂、ワイヤボンディング実装のモールド樹脂との接着強度が大きくなり、半導体チップ実装の電気接続の信頼性を向上することができる。   According to the present invention, in a semiconductor device mounted with a semiconductor chip, a gold layer is formed on the surface of the electrode terminal on which the semiconductor chip of the metal wiring of the electrically insulating substrate is mounted, and the surface of the other metal wiring is roughened. As a result, the bonding strength between the semiconductor chip mounting surface of the electrically insulating substrate and the sealing resin for flip chip mounting and the mold resin for wire bonding mounting is increased, and the reliability of electrical connection for semiconductor chip mounting can be improved. it can.

以下、本発明の実施の形態について、図１乃至図８を用いて説明する。なお、本発明は下記の実施形態に限定されるものではない。   Hereinafter, embodiments of the present invention will be described with reference to FIGS. In addition, this invention is not limited to the following embodiment.

（実施形態１）
本発明の半導体装置の一実施形態を、図１の模式的な断面図を参照して説明する。１０１は半導体チップ、１０２は半導体チップの素子電極、１０３はバンプ、１０４は電気絶縁性基板、１０５は金属配線、１０６は半導体チップが実装される電極端子、１０７は金属配線の粗化部分、１０８は電極端子の金層、１０９は封止樹脂である。 (Embodiment 1)
An embodiment of the semiconductor device of the present invention will be described with reference to the schematic cross-sectional view of FIG. 101 is a semiconductor chip, 102 is an element electrode of the semiconductor chip, 103 is a bump, 104 is an electrically insulating substrate, 105 is a metal wiring, 106 is an electrode terminal on which the semiconductor chip is mounted, 107 is a roughened portion of the metal wiring, 108 Is a gold layer of the electrode terminal, and 109 is a sealing resin.

電気絶縁性基板１０４の金属配線１０５の中で、半導体チップ１０１がフリップチップ実装される電極端子１０６の表面に金１０８を０．０１〜３μｍの厚みに形成し、その他の金属配線１０５の表面には金を形成せずに粗化（１０７）処理することにより、封止樹脂１０９と電気絶縁性基板１０４の接着強度が大きくし、封止樹脂１０９によって保持されている半導体チップ１０１のフリップチップ実装の電気接続信頼性を向上させる。実際の半導体装置では、封止樹脂1０９に接触している金属配線１０５の面積によって、電気接続信頼性が影響を受けやすいが、電極端子１０６以外の金属配線の表面に金を形成せず粗化処理することで、金属配線１０５の面積の影響を低減し、電気接続の信頼性を向上させることができる。   Gold 108 is formed to a thickness of 0.01 to 3 μm on the surface of the electrode terminal 106 on which the semiconductor chip 101 is flip-chip mounted in the metal wiring 105 of the electrically insulating substrate 104, and on the surface of the other metal wiring 105. By performing roughening (107) treatment without forming gold, the bonding strength between the sealing resin 109 and the electrically insulating substrate 104 is increased, and the flip chip mounting of the semiconductor chip 101 held by the sealing resin 109 is performed. Improve the electrical connection reliability. In an actual semiconductor device, the electrical connection reliability is easily affected by the area of the metal wiring 105 that is in contact with the sealing resin 109, but the surface of the metal wiring other than the electrode terminal 106 is roughened without forming gold. By processing, the influence of the area of the metal wiring 105 can be reduced, and the reliability of electrical connection can be improved.

本発明の実施形態において、市販されているもともと粗化された銅配線基板に選択的に金メッキを施すことで粗化部と平滑な金表面部を形成してもよいし、光沢銅箔を用いて後から粗化してもよい。後から粗化する手段として、化学的なエッチングによる表面の微粗化処理等が用いられる。   In an embodiment of the present invention, a roughened portion and a smooth gold surface portion may be formed by selectively performing gold plating on an originally roughened copper wiring board that is commercially available, or a bright copper foil is used. It may be roughened later. As a means for roughening later, surface roughening treatment by chemical etching or the like is used.

前記金を形成しない金属配線表面の粗化の程度は、ＪＩＳ Ｂ ０６０１に規定の十点平均粗さＲｚにおいて、１〜１０μｍの範囲が好ましく、より好ましくは３〜６μｍの範囲である。前記範囲であれば、樹脂との接着性を高く維持できる。   The degree of roughening of the surface of the metal wiring not forming gold is preferably in the range of 1 to 10 μm, more preferably in the range of 3 to 6 μm, in the ten-point average roughness Rz defined in JIS B 0601. If it is the said range, adhesiveness with resin can be maintained highly.

（実施形態２）
本発明の半導体装置の別の一実施形態を、図２の模式的な断面図を参照して説明する。２０１は半導体チップ、２０２は半導体チップの素子電極、２０３は金ワイヤ、２０４は電気絶縁性基板、２０５は金属配線、２０６は半導体チップが実装される電極端子、２０７は金属配線の粗化部分、２０８は電極端子の金層、２０９はモールド樹脂、２１０は半導体チップのダイボンディング材である。 (Embodiment 2)
Another embodiment of the semiconductor device of the present invention will be described with reference to the schematic cross-sectional view of FIG. 201 is a semiconductor chip, 202 is an element electrode of the semiconductor chip, 203 is a gold wire, 204 is an electrically insulating substrate, 205 is a metal wiring, 206 is an electrode terminal on which the semiconductor chip is mounted, 207 is a roughened portion of the metal wiring, 208 is a gold layer of electrode terminals, 209 is a mold resin, and 210 is a die bonding material of a semiconductor chip.

電気絶縁性基板２０４の金属配線の中で、半導体チップ２０１がワイヤボンディング実装される電極端子２０６の表面に金を形成し、その他の金属配線２０５の表面には金を形成せずに粗化（２０７）処理することにより、モールド樹脂２０９と電気絶縁性基板２０４の接着強度を大きくし、モールド樹脂２０９によって保持されている半導体チップ２０１のワイヤボンディング実装の電気接続信頼性を向上させることができる。粗化の程度は実施形態１と同程度が好ましい。   In the metal wiring of the electrically insulating substrate 204, gold is formed on the surface of the electrode terminal 206 on which the semiconductor chip 201 is mounted by wire bonding, and the surface of the other metal wiring 205 is roughened without forming gold ( 207) By processing, the adhesive strength between the mold resin 209 and the electrically insulating substrate 204 can be increased, and the electrical connection reliability of the wire bonding mounting of the semiconductor chip 201 held by the mold resin 209 can be improved. The degree of roughening is preferably the same as in the first embodiment.

（実施形態３）
本発明の半導体装置の別の一実施形態を、図３の模式的な断面図を参照して説明する。３０１は積層半導体チップ、３０２は積層半導体チップの素子電極、３０３は金ワイヤ、３０４は電気絶縁性基板、３０５は金属配線、３０６は積層半導体チップが実装される電極端子、３０７は金属配線の粗化部分、３０８は電極端子の金層、３０９はモールド樹脂、３１０は半導体チップのダイボンディング材である。 (Embodiment 3)
Another embodiment of the semiconductor device of the present invention will be described with reference to the schematic cross-sectional view of FIG. Reference numeral 301 is a laminated semiconductor chip, 302 is an element electrode of the laminated semiconductor chip, 303 is a gold wire, 304 is an electrically insulating substrate, 305 is a metal wiring, 306 is an electrode terminal on which the laminated semiconductor chip is mounted, and 307 is a rough metal wiring. 308 is a gold layer of an electrode terminal, 309 is a mold resin, and 310 is a die bonding material of a semiconductor chip.

２個の半導体チップが積層された積層半導体チップ３０１がワイヤボンディング実装された半導体装置においても、実施形態１〜２と同様に、電気絶縁性基板３０４の金属配線の中で、積層半導体チップ３０１がワイヤボンディング実装される電極端子３０６の表面に金を形成し、その他の金属配線３０５の表面には金を形成せず粗化（３０７）処理することにより、モールド樹脂３０９と電気絶縁性基板３０４の接着強度を大きくし、モールド樹脂３０９によって保持されている積層半導体チップ３０１のワイヤボンディング実装の電気接続信頼性を向上させることができる。また、積層する半導体チップ数が３枚に増えても、同様の効果を得ることができる。粗化の程度は実施形態１と同程度が好ましい。   Also in the semiconductor device in which the laminated semiconductor chip 301 in which two semiconductor chips are laminated is wire-bonded, the laminated semiconductor chip 301 is included in the metal wiring of the electrically insulating substrate 304 as in the first and second embodiments. Gold is formed on the surface of the electrode terminal 306 to be mounted by wire bonding, and the surface of the other metal wiring 305 is roughened (307) without forming gold, so that the mold resin 309 and the electrically insulating substrate 304 are formed. The adhesive strength can be increased, and the electrical connection reliability of the wire bonding mounting of the laminated semiconductor chip 301 held by the mold resin 309 can be improved. The same effect can be obtained even when the number of stacked semiconductor chips is increased to three. The degree of roughening is preferably the same as in the first embodiment.

（実施形態４）
本発明の半導体装置の別の一実施形態を、図４の模式的な断面図を参照して説明する。４０１は積層半導体チップ、４０２は積層半導体チップの素子電極、４０３は金ワイヤ、４０４はバンプ、４０５は電気絶縁性基板、４０６は金属配線、４０７は積層半導体チップが実装される電極端子、４０８は金属配線の粗化部分、４０９は電極端子の金層、４１０はモールド樹脂、４１１は封止樹脂、４１２は積層半導体チップのダイボンディング材である。 (Embodiment 4)
Another embodiment of the semiconductor device of the present invention will be described with reference to the schematic cross-sectional view of FIG. 401 is a laminated semiconductor chip, 402 is an element electrode of the laminated semiconductor chip, 403 is a gold wire, 404 is a bump, 405 is an electrically insulating substrate, 406 is a metal wiring, 407 is an electrode terminal on which the laminated semiconductor chip is mounted, and 408 is A roughened portion of the metal wiring, 409 is a gold layer of an electrode terminal, 410 is a mold resin, 411 is a sealing resin, and 412 is a die bonding material of a laminated semiconductor chip.

２個の半導体チップが積層された積層半導体チップ４０１がフリップチップ実装及びワイヤボンディング実装によって電気接続された半導体装置においても、実施形態１〜３と同様に電気絶縁性基板４０５の金属配線の中で、積層半導体チップ４０１がワイヤボンディング実装及びフリップチップ実装によって電気接続される電極端子４０７の表面に金を形成し、その他の金属配線４０６の表面には金を形成せずに粗化（４０８）処理することにより、モールド樹脂４１０及び封止樹脂４１１と電気絶縁性基板４０５の接着強度を大きくし、モールド樹脂４１０及び封止樹脂４１１によって保持されている積層半導体チップ４０１のワイヤボンディング実装及びフリップチップ実装の電気接続信頼性を向上させることができる。また、積層する半導体チップ数が３枚に増えても、最下段の半導体チップをフリップチップ実装、上二段の半導体チップをワイヤボンディングすることで作製することができる。粗化の程度は実施形態１と同程度が好ましい。   Also in a semiconductor device in which a laminated semiconductor chip 401 in which two semiconductor chips are laminated is electrically connected by flip chip mounting and wire bonding mounting, in the metal wiring of the electrically insulating substrate 405 as in the first to third embodiments. The gold is formed on the surface of the electrode terminal 407 to which the laminated semiconductor chip 401 is electrically connected by wire bonding mounting and flip chip mounting, and the surface of the other metal wiring 406 is roughened without forming gold (408). By doing so, the bonding strength between the mold resin 410 and the sealing resin 411 and the electrically insulating substrate 405 is increased, and the wire bonding mounting and flip chip mounting of the laminated semiconductor chip 401 held by the mold resin 410 and the sealing resin 411 are performed. The electrical connection reliability can be improved. Further, even if the number of stacked semiconductor chips is increased to three, it can be manufactured by flip-chip mounting the lowermost semiconductor chip and wire bonding the upper two semiconductor chips. The degree of roughening is preferably the same as in the first embodiment.

（実施形態５）
本発明の半導体装置の別の一実施形態を、図５の模式的な断面図を参照して説明する。５０１は半導体チップ、５０２は半導体チップの素子電極、５０３はバンプ、５０４は電気絶縁性基板、５０５は金属配線、５０６は半導体チップが実装される電極端子、５０７は金属配線の粗化部分、５０８は電極端子の金層、５０９は封止樹脂、５１０は無機フィラーと熱硬化性樹脂とを含む混合物からなる電気絶縁性基板、５１１は導電性樹脂組成物が充填されたインナービアである。 (Embodiment 5)
Another embodiment of the semiconductor device of the present invention will be described with reference to the schematic cross-sectional view of FIG. 501 is a semiconductor chip, 502 is an element electrode of the semiconductor chip, 503 is a bump, 504 is an electrically insulating substrate, 505 is a metal wiring, 506 is an electrode terminal on which the semiconductor chip is mounted, 507 is a roughened portion of the metal wiring, 508 Is an electrode terminal gold layer, 509 is a sealing resin, 510 is an electrically insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin, and 511 is an inner via filled with a conductive resin composition.

フリップチップ実装された半導体を電気絶縁性基板に内蔵した部品内蔵モジュールの形態の半導体装置において、電気絶縁性基板５０４の金属配線の中で、半導体チップ５０１がフリップチップ実装される電極端子５０６の表面に金を形成し、その他の金属配線５０５の表面には金を形成せず粗化（５０７）処理することにより、封止樹脂５０９と電気絶縁性基板５０４の接着強度及び無機フィラーと熱硬化性樹脂とを含む混合物からなる電気絶縁性基板５１０と電気絶縁性基板５０４の接着強度を大きくできる。また、これにより封止樹脂５０９によって保持され、電気絶縁性基板５１０に内蔵されている半導体チップ５０１のフリップチップ実装の電気接続信頼性を向上させることができる。この実施形態５のような半導体チップ５０１が電気絶縁性基板５１０に内蔵された形態においては、表面実装された半導体チップの形態より封止樹脂５０９、電気絶縁性基板５０４間の剥離応力が大きく、信頼性の高い電気接続の実現が難しいが、本実施形態の半導体装置によって、半導体チップの電気接続の信頼性を大きく向上させることができる。また、導電性樹脂組成物が充填されたインナービア５１１の電気接続される金属配線の表面が粗化処理されており、平滑な金層の場合、導電性樹脂組成物が充填されたインナービア５１１が金層上を滑って位置ずれを起こしやすかったが、本実施形態の半導体装置では、位置ずれを抑制することができる。また、インナービアと電気絶縁性基板の金属配線の接着強度が大きくなり、部品内蔵モジュールの形態の半導体装置における信頼性の高いインナービア接続を実現することができる。粗化の程度は実施形態１と同程度が好ましい。   In a semiconductor device in the form of a component built-in module in which a flip-chip mounted semiconductor is embedded in an electrically insulating substrate, the surface of the electrode terminal 506 on which the semiconductor chip 501 is flip-chip mounted in the metal wiring of the electrically insulating substrate 504 By forming gold on the surface and roughening (507) the surface of the other metal wiring 505 without forming gold, the adhesive strength between the sealing resin 509 and the electrically insulating substrate 504 and the inorganic filler and thermosetting The adhesive strength between the electrically insulating substrate 510 and the electrically insulating substrate 504 made of a mixture containing resin can be increased. In addition, the electrical connection reliability of the flip chip mounting of the semiconductor chip 501 held by the sealing resin 509 and built in the electrically insulating substrate 510 can thereby be improved. In the embodiment in which the semiconductor chip 501 is embedded in the electrically insulating substrate 510 as in the fifth embodiment, the peeling stress between the sealing resin 509 and the electrically insulating substrate 504 is larger than that of the surface-mounted semiconductor chip, Although it is difficult to realize highly reliable electrical connection, the reliability of electrical connection of a semiconductor chip can be greatly improved by the semiconductor device of this embodiment. In addition, the surface of the metal wiring electrically connected to the inner via 511 filled with the conductive resin composition is roughened, and in the case of a smooth gold layer, the inner via 511 filled with the conductive resin composition. However, in the semiconductor device of this embodiment, it is possible to suppress the positional deviation. Further, the adhesive strength between the inner via and the metal wiring of the electrically insulating substrate is increased, and a highly reliable inner via connection in the semiconductor device in the form of a component built-in module can be realized. The degree of roughening is preferably the same as in the first embodiment.

（実施形態６）
本発明の半導体装置の製造方法の一実施形態を、図６Ａ−Ｄの模式的な工程断面図を参照して説明する。６０１は半導体チップ、６０２は半導体チップの素子電極、６０３はバンプ、６０４は電気絶縁性基板、６０５は金属配線、６０６は半導体チップが実装される電極端子、６０７は金属配線の粗化部分、６０８は電極端子の金層、６０９は封止樹脂、６１０はフォトレジストである。 (Embodiment 6)
One embodiment of a method for manufacturing a semiconductor device of the present invention will be described with reference to schematic process cross-sectional views of FIGS. 6A to 6D. 601 is a semiconductor chip, 602 is an element electrode of the semiconductor chip, 603 is a bump, 604 is an electrically insulating substrate, 605 is a metal wiring, 606 is an electrode terminal on which the semiconductor chip is mounted, 607 is a roughened portion of the metal wiring, 608 Is a gold layer of electrode terminals, 609 is a sealing resin, and 610 is a photoresist.

まず、金属配線６０５の表面が粗化された電気絶縁性基板６０４を用意する（図６Ａ）。次に、フォトリソグラフィー法により半導体チップ６０１（図６Ｄ）がフリップチップ実装される電極端子６０６を除く部分にフォトレジスト６１０を形成する（図６Ｂ）。次に、電極端子６０６の表面に金６０８を形成する。金層６０８は金メッキにより形成する。その後、フォトレジスト６１０を除去する（図６Ｃ）。次に、封止樹脂６０９を介して半導体チップ６０１を電気絶縁性基板６０４にフリップチップ実装して、本実施形態の半導体装置を作製する（図６Ｄ）。以上のとおり、既存のフリップチップ実装技術とフォトリソグラフィー法をそのまま使用することができ、信頼性の高い半導体装置を作製することができる。   First, an electrically insulating substrate 604 whose surface of the metal wiring 605 is roughened is prepared (FIG. 6A). Next, a photoresist 610 is formed on the portion excluding the electrode terminal 606 on which the semiconductor chip 601 (FIG. 6D) is flip-chip mounted by photolithography (FIG. 6B). Next, gold 608 is formed on the surface of the electrode terminal 606. The gold layer 608 is formed by gold plating. Thereafter, the photoresist 610 is removed (FIG. 6C). Next, the semiconductor chip 601 is flip-chip mounted on the electrically insulating substrate 604 via the sealing resin 609 to manufacture the semiconductor device of this embodiment (FIG. 6D). As described above, the existing flip chip mounting technique and the photolithography method can be used as they are, and a highly reliable semiconductor device can be manufactured.

（実施形態７）
本発明の半導体装置の製造方法の別の一実施形態を、図７Ａ−Ｅの模式的な工程断面図を参照して説明する。７０１は半導体チップ、７０２は半導体チップの素子電極、７０３は金ワイヤ、７０４は電気絶縁性基板、７０５は金属配線、７０６は半導体チップが実装される電極端子、７０７は金属配線の粗化部分、７０８は電極端子の金層、７０９はモールド樹脂、７１０は半導体チップのダイボンディング材、７１１はフォトレジストである。 (Embodiment 7)
Another embodiment of the method for manufacturing a semiconductor device of the present invention will be described with reference to schematic process sectional views of FIGS. 701 is a semiconductor chip, 702 is an element electrode of the semiconductor chip, 703 is a gold wire, 704 is an electrically insulating substrate, 705 is a metal wiring, 706 is an electrode terminal on which the semiconductor chip is mounted, 707 is a roughened portion of the metal wiring, 708 is a gold layer of electrode terminals, 709 is a mold resin, 710 is a die bonding material of a semiconductor chip, and 711 is a photoresist.

まず、金属配線７０５の表面が粗化された電気絶縁性基板７０４を用意する（図７Ａ）。次に、フォトリソグラフィー法により半導体チップがワイヤボンディング実装される電極端子７０６を除く部分にフォトレジスト７１１を形成する（図７Ｂ）。次に、電極端子７０６の表面に金を形成し、フォトレジスト７１０を除去する（図７Ｃ）。次に、半導体チップ７０１の素子電極７０２が形成されていない面をダイボンディング材７１０を介して絶縁性基板７０４に接合し、金ワイヤ７０３を用いて半導体チップ７０１をワイヤボンディング実装する（図７Ｄ）。その後、半導体チップ７０１及び金ワイヤ７０３を含むワイヤボンディング実装部をモールド樹脂７０９でモールドし、本実施形態の半導体装置を作製する（図７Ｅ）。以上のようにして既存のワイヤボンディング実装技術とフォトリソグラフィー法をそのまま使用することができ、信頼性の高い半導体装置を作製することができる。   First, an electrically insulating substrate 704 whose surface of the metal wiring 705 is roughened is prepared (FIG. 7A). Next, a photoresist 711 is formed on the portion excluding the electrode terminal 706 where the semiconductor chip is mounted by wire bonding by photolithography (FIG. 7B). Next, gold is formed on the surface of the electrode terminal 706, and the photoresist 710 is removed (FIG. 7C). Next, the surface of the semiconductor chip 701 where the element electrode 702 is not formed is bonded to the insulating substrate 704 via the die bonding material 710, and the semiconductor chip 701 is wire-bonded and mounted using the gold wire 703 (FIG. 7D). . Thereafter, the wire bonding mounting portion including the semiconductor chip 701 and the gold wire 703 is molded with a mold resin 709 to manufacture the semiconductor device of this embodiment (FIG. 7E). As described above, the existing wire bonding mounting technique and the photolithography method can be used as they are, and a highly reliable semiconductor device can be manufactured.

（実施形態８）
本発明の半導体装置の製造方法の別の一実施形態を、図８Ａ−Ｉの模式的な工程断面図を参照して説明する。８０１は半導体チップ、８０２は半導体チップの素子電極、８０３はバンプ、８０４は半導体チップが電気接続される電気絶縁性基板、８０５は電気絶縁性基板、８０６は無機フィラーと熱硬化性樹脂とを含む混合物からなる板状体、８０７は貫通孔、８０８は導電性樹脂組成物からなる導電性ペーストが充填されたインナービア、８０９は金属配線、８１０は半導体チップが実装される電極端子、８１１は金属配線の粗化部分、８１２は電極端子の金層、８１３は封止樹脂、８１４はフォトレジストである。 (Embodiment 8)
Another embodiment of the method for manufacturing a semiconductor device of the present invention will be described with reference to schematic process sectional views of FIGS. 8A-I. 801 is a semiconductor chip, 802 is an element electrode of the semiconductor chip, 803 is a bump, 804 is an electrically insulating substrate to which the semiconductor chip is electrically connected, 805 is an electrically insulating substrate, and 806 includes an inorganic filler and a thermosetting resin. A plate-like body made of a mixture, 807 is a through hole, 808 is an inner via filled with a conductive paste made of a conductive resin composition, 809 is a metal wiring, 810 is an electrode terminal on which a semiconductor chip is mounted, and 811 is a metal A roughened portion of the wiring, 812 is a gold layer of the electrode terminal, 813 is a sealing resin, and 814 is a photoresist.

まず、金属配線８０９の表面が粗化された電気絶縁性基板８０４を用意する（図８Ａ）。次に、フォトリソグラフィー法により半導体チップがフリップチップ実装される電極端子８１０を除く部分にフォトレジスト８１４を形成する（図８Ｂ）。次に、電極端子８１０の表面に金層８１２を形成し、フォトレジスト８１４を除去する（図８Ｃ）。次に、封止樹脂８１３を介して半導体チップ８０１を電気絶縁性基板８０４にフリップチップ実装する（図８Ｄ）。一方、無機フィラーと熱硬化性樹脂とを含む混合物からなる板状体８０６を準備し（図８Ｅ）、導電性ペーストが充填されインナービア８０８となる貫通孔８０７を形成する（図８Ｆ）。次に、貫通孔８０７に導電性ペーストを充填する（図８Ｇ）。次に、半導体チップ８０１をフリップチップ実装した電気絶縁性基板８０４と、導電性ペーストが充填されたインナービア８０８が形成された板状体８０６と、板状体８０６のもう一方の金属配線を形成するための電気絶縁性基板８０５を、インナービア８０８によって電気接続するように位置あわせする（図８Ｈ）。次に、加熱加圧して、電気絶縁性基板８０４と板状体８０６と電気絶縁性基板８０５を接着して、半導体チップ８０１を板状体８０６に埋設して一体化し、板状体８０６及びインナービア８０８に充填された導電性ペーストを硬化して、本実施形態の半導体装置を作製する（図８Ｉ）。以上のように、既存のフリップチップ実装技術とフォトリソグラフィー法をそのまま使用することができ、信頼性の高い半導体装置を作製することができる。また、加熱加圧工程による半導体チップの板状体への埋設時に、導電性ペーストが充填されたインナービアと電気接続される金属配線が粗化されており、インナービアの位置ずれが置きにくいため、金属配線の微細化、インナービアのビアピッチの狭ピッチ化が進んでも、この半導体装置では、導電性樹脂組成物からなる導電性ペーストが充填されたインナービアを位置精度良く形成することができる。   First, an electrically insulating substrate 804 whose surface of the metal wiring 809 is rough is prepared (FIG. 8A). Next, a photoresist 814 is formed on the portion excluding the electrode terminal 810 on which the semiconductor chip is flip-chip mounted by photolithography (FIG. 8B). Next, a gold layer 812 is formed on the surface of the electrode terminal 810, and the photoresist 814 is removed (FIG. 8C). Next, the semiconductor chip 801 is flip-chip mounted on the electrically insulating substrate 804 via the sealing resin 813 (FIG. 8D). On the other hand, a plate-like body 806 made of a mixture containing an inorganic filler and a thermosetting resin is prepared (FIG. 8E), and a through-hole 807 that is filled with a conductive paste and becomes an inner via 808 is formed (FIG. 8F). Next, the through-hole 807 is filled with a conductive paste (FIG. 8G). Next, an electrically insulating substrate 804 on which a semiconductor chip 801 is flip-chip mounted, a plate-like body 806 on which an inner via 808 filled with a conductive paste is formed, and another metal wiring of the plate-like body 806 are formed. The electrically insulating substrate 805 is aligned so as to be electrically connected by the inner via 808 (FIG. 8H). Next, by applying heat and pressure, the electrically insulating substrate 804, the plate-like body 806, and the electrically insulating substrate 805 are bonded, and the semiconductor chip 801 is embedded and integrated in the plate-like body 806, and the plate-like body 806 and the inner body are integrated. The conductive paste filled in the via 808 is cured to manufacture the semiconductor device of this embodiment (FIG. 8I). As described above, the existing flip chip mounting technique and the photolithography method can be used as they are, and a highly reliable semiconductor device can be manufactured. In addition, when the semiconductor chip is embedded in the plate-like body by the heating and pressurizing process, the metal wiring electrically connected to the inner via filled with the conductive paste is roughened, and the inner via is not easily displaced. Even if miniaturization of the metal wiring and narrowing of the via pitch of the inner via progress, in this semiconductor device, the inner via filled with the conductive paste made of the conductive resin composition can be formed with high positional accuracy.

以下、実施例により本発明をさらに具体的に説明する。   Hereinafter, the present invention will be described more specifically with reference to examples.

（実施例１）
実施例１では上述の実施の形態５の部品内蔵モジュールの形態の半導体装置を、次の（i）〜（iv）の手順に従って製造した。
（i）電気絶縁性基板における電極端子の金層の形成
半導体チップを実装する電気絶縁性基板としてガラスエポキシ基板を準備した。ガラスエポキシ基板は厚さ２００μｍ、半導体チップを実装する電極端子、導電性樹脂組成物からなる導電性ペーストが充填されたインナービアを接続するビアランド、及びそれらを電気接続する金属配線が形成されており、それらの金属配線の厚さは１８μｍで、表面の粗化度合いは平均十点粗さRz５μmに粗化されている。フォトリソグラフィー法を用いてガラスエポキシ基板の半導体チップが実装される電極端子を除く部分にフォトレジストを形成した。フォトレジストには旭化成社製ＡＱ−１５５８を用いた。次に、このガラスエポキシ基板に無電解ニッケルメッキを１μｍ、引き続いて無電解金メッキ０.０４μｍを形成した。メッキ浴にはウエムラ・インターナショナル・シンガポール社製のニムデンＮＰＲ−Ｍ、オーリカルＴＫＫ５１ Ｍ２０を用いた。以上の工程により、半導体チップを実装する電極端子の表面のみに金を形成したガラスエポキシ基板を作製した。
（ii）半導体チップの実装
１０ｍｍ角、厚さ０.３ｍｍの半導体チップを準備し、半導体チップの１００個の素子電極に予め金ワイヤボンディング法によって高さ７０μｍの金バンプを突起状電極として形成した。フリップチップ実装に用いる封止樹脂には、日立化成社製の厚さ４０μｍのシート状封止樹脂ＵＦ−５１１を用いた。このシート状封止樹脂を面積が１００平方ｍｍとなるように加工した後、ガラスエポキシ基板の半導体チップが実装される領域に貼り付けた。次に、半導体チップを素子電極が形成されていない背面から加熱加圧し、ガラスエポキシ基板にフリップチップ実装した。加熱温度は２００℃、圧力は３ＭＰａ、加熱加圧時間は１５秒とした。その結果、半導体チップの素子電極とガラスエポキシ基板の無電解金メッキされた電極端子が、金バンプを介して電気接続され、封止樹脂が硬化した。
（iii）無機フィラーと熱硬化性樹脂とを含む混合物からなる板状体の準備
まず無機フィラーと熱硬化性樹脂の混合を、板状体を構成する材料を、必要に応じて粘度調整のための微量の溶剤を投入し、混合攪拌機を用いて混合し調整した。本実施例では、エポキシ樹脂１０重量％、シリカフィラー９０重量％を含む混合物を１０分間攪拌して調整した。次に、この混合物から、ドクターブレード法によって厚さ１００μｍの板状体を作製した。次に、この板状体を４枚重ねてラミネートし、厚さ４００μｍの板状体を形成した後、パンチャーを用いてインナービアとなる直径１６０μｍの貫通孔を形成し、この貫通孔に導電性ペーストをスクリーン印刷法により充填した。ここで使用した導電性ペーストは、球形状の銅粒子８５重量％と、樹脂成分としてビスフェノールＡ型エポキシ樹脂（油化シェルエポキシ社製「エピコート８２８」）３重量％と、グリシジルエステル系エポキシ樹脂（東都化成社製「ＹＤ−１７１」）９重量％と、硬化剤としてアミンアダクト硬化剤（味の素社製「ＭＹ−２４」）３重量％とを三本ロールを用いて混錬して調整した。
（iv）半導体チップの内蔵、一体化
次に（ii）で得た半導体チップをフリップチップ実装したガラスエポキシ基板と、（iii）で得た導電性ペーストを充填したインナービアが形成された板状体、そして板状体のもう一方の主面の金属配線を形成するためのガラスエポキシ基板を準備し、これらを半導体チップが板状体に内蔵されるよう、板状体のインナービアによって２つのガラスエポキシ基板及び板状体が電気接続されるよう、位置合わせした後、加熱加圧することで一体化し、本実施例の部品内蔵モジュールをした半導体装置を得た。加熱加圧は熱プレス機を用いて、加熱温度は２００℃、圧力は３ＭＰａ、加熱加圧時間は２時間とした。板状体に含まれるエポキシ樹脂は、粘度が一旦低下した後、硬化し、板状体とガラスエポキシ基板が接着された。導電性ペーストが充填されたインナービアに含まれるエポキシ樹脂も硬化し、板状体を通して２つのガラスエポキシ基板が電気接続された。 (Example 1)
In Example 1, the semiconductor device in the form of the component built-in module of the above-described fifth embodiment was manufactured according to the following procedures (i) to (iv).
(I) Formation of the gold layer of the electrode terminal in an electrically insulating board | substrate The glass epoxy board | substrate was prepared as an electrically insulating board | substrate which mounts a semiconductor chip. The glass epoxy substrate has a thickness of 200 μm, an electrode terminal for mounting a semiconductor chip, a via land for connecting an inner via filled with a conductive paste made of a conductive resin composition, and a metal wiring for electrically connecting them. The thickness of these metal wirings is 18 μm, and the roughness of the surface is roughened to an average ten-point roughness Rz of 5 μm. Photoresist was used to form a photoresist on the portion excluding the electrode terminals on which the semiconductor chip of the glass epoxy substrate was mounted. As a photoresist, AQ-1558 manufactured by Asahi Kasei Corporation was used. Next, 1 μm of electroless nickel plating was formed on the glass epoxy substrate, and subsequently 0.04 μm of electroless gold plating was formed. Nimuden NPR-M and Orical TKK51 M20 manufactured by Uemura International Singapore were used for the plating bath. Through the above steps, a glass epoxy substrate in which gold was formed only on the surface of the electrode terminal on which the semiconductor chip was mounted was produced.
(Ii) Mounting of semiconductor chip A 10 mm square semiconductor chip with a thickness of 0.3 mm was prepared, and gold bumps with a height of 70 μm were previously formed as protruding electrodes on 100 element electrodes of the semiconductor chip by a gold wire bonding method. . As the sealing resin used for flip chip mounting, a sheet-shaped sealing resin UF-511 made by Hitachi Chemical Co., Ltd. was used. After processing this sheet-form sealing resin so that an area might become 100 square mm, it affixed on the area | region where the semiconductor chip of a glass epoxy board | substrate is mounted. Next, the semiconductor chip was heated and pressed from the back surface where the device electrode was not formed, and was flip-chip mounted on the glass epoxy substrate. The heating temperature was 200 ° C., the pressure was 3 MPa, and the heating and pressing time was 15 seconds. As a result, the element electrode of the semiconductor chip and the electrode terminal plated with electroless gold on the glass epoxy substrate were electrically connected via the gold bump, and the sealing resin was cured.
(Iii) Preparation of a plate-like body composed of a mixture containing an inorganic filler and a thermosetting resin First, mixing the inorganic filler and the thermosetting resin, adjusting the material constituting the plate-like body, and adjusting the viscosity as necessary A small amount of the solvent was added and mixed and adjusted using a mixing stirrer. In this example, a mixture containing 10% by weight of epoxy resin and 90% by weight of silica filler was prepared by stirring for 10 minutes. Next, a plate-like body having a thickness of 100 μm was produced from this mixture by a doctor blade method. Next, after laminating and laminating four sheets of this plate-like body, a plate-like body having a thickness of 400 μm was formed, and then a through-hole having a diameter of 160 μm serving as an inner via was formed using a puncher. The paste was filled by screen printing. The conductive paste used here was 85% by weight of spherical copper particles, 3% by weight of bisphenol A type epoxy resin (“Epicoat 828” manufactured by Yuka Shell Epoxy Co., Ltd.) as a resin component, and glycidyl ester epoxy resin ( 9% by weight of “YD-171” manufactured by Tohto Kasei Co., Ltd.) and 3% by weight of an amine adduct curing agent (“MY-24” manufactured by Ajinomoto Co., Inc.) as a curing agent were kneaded and adjusted using three rolls.
(Iv) Built-in and integrated semiconductor chip Next, a glass epoxy substrate on which the semiconductor chip obtained in (ii) is flip-chip mounted, and a plate shape on which an inner via filled with the conductive paste obtained in (iii) is formed And a glass epoxy substrate for forming the metal wiring on the other main surface of the plate-like body, and two of them are formed by inner vias of the plate-like body so that the semiconductor chip is built in the plate-like body. After aligning the glass epoxy substrate and the plate-like body to be electrically connected, they were integrated by heating and pressing to obtain a semiconductor device having a component built-in module of this example. The heating and pressurization was performed using a hot press machine, the heating temperature was 200 ° C., the pressure was 3 MPa, and the heating and pressing time was 2 hours. The epoxy resin contained in the plate-like body was cured after the viscosity once decreased, and the plate-like body and the glass epoxy substrate were bonded. The epoxy resin contained in the inner via filled with the conductive paste was also cured, and the two glass epoxy substrates were electrically connected through the plate-like body.

このようにして本実施例の半導体装置を作製した。   In this manner, the semiconductor device of this example was manufactured.

比較例として、従来例と同様に前記（ｉ）の工程で、半導体チップが実装される電極端子を含む一面の全部の金属配線の表面に、同様の方法で金層を形成した半導体装置を作製した。   As a comparative example, a semiconductor device in which a gold layer is formed by the same method on the surface of all the metal wirings on one side including the electrode terminals on which the semiconductor chip is mounted is manufactured in the step (i) as in the conventional example. did.

２つの半導体装置の電気接続信頼性の評価は、吸湿リフロー試験によって行なった。具体的な条件は、８５℃、８５％ＲＨ条件下で１６８時間保持した後、最高温度２６０℃であるベルト式リフロー試験機を用いて熱衝撃を加えた。半導体装置の信頼性として、フリップチップ実装の半導体チップの素子電極とガラスエポキシ基板の電極端子との間の接続抵抗値（以下、バンプ抵抗と略）によって評価した。評価基準はバンプ抵抗が吸湿リフロー試験前後で１０％以上変化したものを不良とし、１００個の電気接続点に対する不良発生率で評価した結果、従来の半導体装置では６０％不良が発生したが、本発明の半導体装置では不良は発生しなかった。   The electrical connection reliability of the two semiconductor devices was evaluated by a moisture absorption reflow test. Specifically, after holding for 168 hours at 85 ° C. and 85% RH, thermal shock was applied using a belt-type reflow tester having a maximum temperature of 260 ° C. The reliability of the semiconductor device was evaluated by a connection resistance value (hereinafter abbreviated as bump resistance) between an element electrode of a flip-chip mounted semiconductor chip and an electrode terminal of a glass epoxy substrate. The evaluation standard is that the bump resistance changed by 10% or more before and after the moisture absorption reflow test, and the defect was evaluated as a defect occurrence rate with respect to 100 electrical connection points. As a result, 60% defect occurred in the conventional semiconductor device. No defects occurred in the semiconductor device of the invention.

このように本実施例の半導体装置は、半導体チップが実装される電極端子の表面に金層を形成し、樹脂と接着するその他の金属配線の表面に粗化処理を行なうことで、半導体チップの実装の電気接続信頼性を向上することができる。   As described above, the semiconductor device according to the present embodiment forms a gold layer on the surface of the electrode terminal on which the semiconductor chip is mounted, and performs a roughening process on the surface of the other metal wiring bonded to the resin. The electrical connection reliability of the mounting can be improved.

図１は本発明の実施形態１における半導体装置の断面図である。FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention. 図２は本発明の実施形態２における半導体装置の断面図である。FIG. 2 is a cross-sectional view of a semiconductor device according to Embodiment 2 of the present invention. 図３は本発明の実施形態３における半導体装置の断面図である。FIG. 3 is a cross-sectional view of a semiconductor device according to Embodiment 3 of the present invention. 図４は本発明の実施形態４における半導体装置の断面図である。FIG. 4 is a cross-sectional view of a semiconductor device according to Embodiment 4 of the present invention. 図５は本発明の実施形態５及び実施例１における半導体装置の断面図である。FIG. 5 is a cross-sectional view of the semiconductor device according to Embodiment 5 and Example 1 of the present invention. 図６Ａ−Ｄは本発明の実施形態６における半導体装置の製造方法を示す工程断面図である。6A to 6D are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 6 of the present invention. 図７Ａ−Ｅは本発明の実施形態７における半導体装置の製造方法を示す工程断面図である。7A to 7E are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 7 of the present invention. 図８Ａ−Ｉは本発明の実施形態８における半導体装置の製造方法を示す工程断面図である。8A to 8I are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 8 of the present invention. 図９は従来の半導体装置の一例を示す断面図である。FIG. 9 is a cross-sectional view showing an example of a conventional semiconductor device. 図１０は従来の半導体装置の別の一例を示す断面図である。FIG. 10 is a cross-sectional view showing another example of a conventional semiconductor device. 図１１は従来の半導体装置の別の一例を示す断面図である。FIG. 11 is a cross-sectional view showing another example of a conventional semiconductor device. 図１２は従来の半導体装置の別の一例を示す断面図である。FIG. 12 is a cross-sectional view showing another example of a conventional semiconductor device.

Claims (21)

複数の金属配線を備えた電気絶縁性基板の表面に半導体チップが実装され、少なくとも前記複数の金属配線の一部を樹脂が覆っている半導体装置であって、
前記電気絶縁性基板に形成された複数の金属配線のうち、少なくとも前記半導体チップと電気的に接続される金属配線の表面には金層を形成し、
前記電気絶縁性基板に形成された複数の金属配線のうち、前記樹脂と接触する金属配線の表面には粗化部を形成することを特徴とする半導体装置。A semiconductor device in which a semiconductor chip is mounted on the surface of an electrically insulating substrate provided with a plurality of metal wirings, and at least a part of the plurality of metal wirings is covered with a resin,
A gold layer is formed on the surface of at least the metal wiring electrically connected to the semiconductor chip among the plurality of metal wirings formed on the electrically insulating substrate,
Of the plurality of metal wires formed on the electrically insulating substrate, a roughened portion is formed on the surface of the metal wire in contact with the resin. 前記半導体チップの実装はフリップチップ実装であり、前記半導体チップの素子電極面と前記電気絶縁性基板の電極端子面との間に封止樹脂が位置している請求項１に記載の半導体装置。  The semiconductor device according to claim 1, wherein the mounting of the semiconductor chip is flip chip mounting, and a sealing resin is located between an element electrode surface of the semiconductor chip and an electrode terminal surface of the electrically insulating substrate. 前記半導体チップの実装はワイヤボンディング実装であり、
前記半導体チップの素子電極面の反対の主面が前記電気絶縁性基板のワイヤボンディング実装される主面に接合され、前記半導体チップ、前記ワイヤボンディング実装部分が樹脂モールドされている請求項１に記載の半導体装置。The mounting of the semiconductor chip is wire bonding mounting,
The main surface opposite to the element electrode surface of the semiconductor chip is bonded to a main surface of the electrically insulating substrate on which wire bonding is mounted, and the semiconductor chip and the wire bonding mounting portion are resin-molded. Semiconductor device. 前記半導体チップは複数の半導体チップが積層された積層半導体チップであり、
前記積層半導体チップがワイヤボンディング実装された電極端子を含む複数の金属配線が形成された主面をもつ電気絶縁性基板とを備え、
前記積層半導体チップのうち一つの半導体チップの素子電極面の反対の主面が前記電気絶縁性基板のワイヤボンディング実装される主面に接合され、前記積層半導体チップ、前記ワイヤボンディング実装部分が樹脂モールドされている請求項１に記載の半導体装置。The semiconductor chip is a laminated semiconductor chip in which a plurality of semiconductor chips are laminated,
An electrically insulating substrate having a main surface on which a plurality of metal wirings including electrode terminals on which the laminated semiconductor chip is wire-bonded and mounted are formed;
The main surface opposite to the element electrode surface of one of the stacked semiconductor chips is bonded to the main surface of the electrically insulating substrate on which wire bonding is mounted, and the stacked semiconductor chip and the wire bonding mounting portion are resin molded. The semiconductor device according to claim 1. 前記半導体チップは複数の半導体チップが積層された積層半導体チップであり、
前記積層半導体チップがワイヤボンディング実装及びフリップチップ実装された電極端子を含む複数の金属配線が形成された主面をもつ電気絶縁性基板とを備え、
前記積層半導体チップのフリップチップ実装された半導体チップの素子電極面と前記電気絶縁性基板の電極端子面との間に封止樹脂が位置しており、
前記積層半導体チップ、前記ワイヤボンディング実装部分が樹脂モールドされている請求項１に記載の半導体装置。The semiconductor chip is a laminated semiconductor chip in which a plurality of semiconductor chips are laminated,
An electrical insulating substrate having a principal surface on which a plurality of metal wirings including electrode terminals on which the laminated semiconductor chip is wire-bonded and flip-chip mounted are formed;
A sealing resin is located between the element electrode surface of the flip-chip mounted semiconductor chip of the laminated semiconductor chip and the electrode terminal surface of the electrically insulating substrate;
The semiconductor device according to claim 1, wherein the laminated semiconductor chip and the wire bonding mounting part are resin-molded. 前記半導体チップの実装はフリップチップ実装であり、
前記半導体チップがフリップチップ実装された第１の電気絶縁性基板と、
複数の金属配線が形成された主面をもつ第２の電気絶縁性基板と、
前記第１の電気的絶縁基板と前記第２の電気的絶縁基板との間に配置されている、複数の金属配線が形成された主面をもつ無機フィラーと熱硬化性樹脂とを含む混合物からなる第３の電気絶縁性基板と、
前記第３の電気絶縁性基板内に形成された導電性樹脂組成物が充填されたインナービアとを備え、
前記半導体チップの素子電極面と前記第１の電気絶縁性基板の電極端子面との間に封止樹脂が位置しており、
前記第１と第２の電気絶縁性基板は前記第３の電気絶縁性基板を介して一体化しており、
前記第１〜第３の電気絶縁性基板の少なくとも一部の金属配線は前記インナービアを介して電気接続されている請求項１に記載の半導体装置。The mounting of the semiconductor chip is flip chip mounting,
A first electrically insulating substrate on which the semiconductor chip is flip-chip mounted;
A second electrically insulating substrate having a main surface on which a plurality of metal wirings are formed;
From a mixture including an inorganic filler having a main surface on which a plurality of metal wirings are formed and a thermosetting resin, which is disposed between the first electrically insulating substrate and the second electrically insulating substrate. A third electrically insulating substrate comprising:
An inner via filled with a conductive resin composition formed in the third electrically insulating substrate,
A sealing resin is located between the element electrode surface of the semiconductor chip and the electrode terminal surface of the first electrically insulating substrate;
The first and second electrically insulating substrates are integrated via the third electrically insulating substrate;
2. The semiconductor device according to claim 1, wherein at least some of the metal wirings of the first to third electrically insulating substrates are electrically connected via the inner via. 前記半導体チップが実装された主面の金属配線において、前記電極端子表面を含む前記金属配線の一部の表面に金層が形成されており、他の金属配線の表面は粗化処理されている請求項１〜６のいずれかに記載の半導体装置。  In the metal wiring on the main surface on which the semiconductor chip is mounted, a gold layer is formed on a part of the surface of the metal wiring including the electrode terminal surface, and the surface of the other metal wiring is roughened. The semiconductor device according to claim 1. 前記金層は、無電解メッキ、電解メッキ、蒸着及びスパッタから選ばれる少なくとも一つの手段で形成されている請求項１〜７のいずれかに記載の半導体装置。  The semiconductor device according to claim 1, wherein the gold layer is formed by at least one means selected from electroless plating, electrolytic plating, vapor deposition, and sputtering. 前記半導体チップのフリップチップ実装は、ＡＣＦ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）、ＡＣＰ（Ａｎｉｓｏｔｒｏｐｉｃ Ｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）、ＮＣＦ（Ｎｏｎ Ｃｏｎｄｕｃｔｉｖｅ Ｆｉｌｍ）、ＮＣＰ（Ｎｏｎ Ｃｏｎｄｕｃｔｉｖｅ Ｐａｓｔｅ）のいずれかを用いた熱圧着工法、又は前記半導体チップの素子電極に形成された金バンプと前記電気絶縁性基板の電極端子表面に形成された金の超音波接合によってなされている請求項２、５又は６に記載の半導体装置。  The flip-chip mounting of the semiconductor chip may be performed by using any one of the above-described semiconductor chip methods using an ACF (Anisotropic Conductive Film), ACP (Anisotropic Conductive Paste), NCF (Non Conductive Film), NCP (Non Conductive Paste), or the above-mentioned semiconductor chip. The semiconductor device according to claim 2, 5, or 6, wherein the semiconductor device is formed by ultrasonic bonding of gold bumps formed on the element electrode and gold formed on an electrode terminal surface of the electrically insulating substrate. 前記金属配線は、表面が粗化された銅を含む請求項１〜９のいずれかに記載の半導体装置。  The semiconductor device according to claim 1, wherein the metal wiring includes copper whose surface is roughened. 前記金属配線表面の粗化の程度は、ＪＩＳ Ｂ ０６０１記載の十点平均粗さＲｚにおいて、１〜１０μｍの範囲である請求項１〜１０のいずれかに記載の半導体装置。  11. The semiconductor device according to claim 1, wherein the degree of roughening of the surface of the metal wiring is in a range of 1 to 10 μm in ten-point average roughness Rz described in JIS B 0601. 前記第３の電気絶縁性基板の無機フィラーは７０重量％〜９５重量％の範囲である請求項６に記載の半導体装置。  The semiconductor device according to claim 6, wherein the inorganic filler of the third electrically insulating substrate is in the range of 70 wt% to 95 wt%. 前記無機フィラーは、Ａｌ２Ｏ３、ＭｇＯ、ＢＮ、ＡｌＮ及びＳｉＯ２から選ばれる少なくとも一つの無機フィラーを含む請求項６又は１２に記載の半導体装置。The semiconductor device according to claim 6, wherein the inorganic filler includes at least one inorganic filler selected from Al 2 O 3 , MgO, BN, AlN, and SiO 2 . 前記熱硬化性樹脂は、エポキシ樹脂、フェノール樹脂及びシアネート樹脂から選ばれる少なくとも一つの熱硬化性樹脂を含む請求項６又は１２に記載の半導体装置。  The semiconductor device according to claim 6, wherein the thermosetting resin includes at least one thermosetting resin selected from an epoxy resin, a phenol resin, and a cyanate resin. 前記導電性樹脂組成物が金、銀、銅及びニッケルから選ばれる少なくとも一つの金属を含む金属粒子を導電性成分として含み、エポキシ樹脂を樹脂成分として含む請求項６に記載の半導体装置。  The semiconductor device according to claim 6, wherein the conductive resin composition includes metal particles including at least one metal selected from gold, silver, copper, and nickel as a conductive component, and includes an epoxy resin as a resin component. 半導体チップと、前記半導体チップがフリップチップ実装される電極端子を含む複数の粗化処理された表面の金属配線が形成された主面をもつ電気絶縁性基板とを準備する工程（ａ）と、
フォトリソグラフィー法によって、前記電気絶縁性基板の前記半導体チップがフリップチップ実装される主面の、前記電極端子以外の部分に、フォトレジストを形成する工程（ｂ）と、
前記電気絶縁性基板のフリップチップ実装される主面に無電解金メッキを行なって、前記電極端子表面に金を形成した後、フォトレジストを除去する工程（ｃ）と、
前記半導体チップの素子電極面と前記電気絶縁性基板の電極端子面との間に封止樹脂を介して、前記半導体チップを前記電気絶縁性基板にフリップチップ実装する工程（ｄ）とを含む半導体装置の製造方法。Preparing a semiconductor chip and an electrically insulating substrate having a main surface on which a plurality of roughened surface metal wirings including electrode terminals on which the semiconductor chip is flip-chip mounted is formed (a);
A step (b) of forming a photoresist on a portion other than the electrode terminals on a main surface of the electrically insulating substrate on which the semiconductor chip is flip-chip mounted by a photolithography method;
(C) removing the photoresist after performing electroless gold plating on the main surface of the electrically insulating substrate to be flip-chip mounted to form gold on the electrode terminal surface;
A step (d) of flip-chip mounting the semiconductor chip on the electrically insulating substrate via a sealing resin between an element electrode surface of the semiconductor chip and an electrode terminal surface of the electrically insulating substrate. Device manufacturing method. 半導体チップと、前記半導体チップがワイヤボンディング実装される電極端子を含む複数の粗化処理された表面の金属配線が形成された主面をもつ電気絶縁性基板とを準備する工程（ａ）と、
フォトリソグラフィー法によって、前記電気絶縁性基板の前記半導体チップがワイヤボンディング実装される主面の、前記電極端子以外の部分に、フォトレジストを形成する工程（ｂ）と、
前記電気絶縁性基板のワイヤボンディング実装される主面に無電解金メッキを行なって、前記電極端子表面に金を形成した後、フォトレジストを除去する工程（ｃ）と、
前記半導体チップの素子電極が形成されている面の反対の主面を前記電気絶縁性基板に接合する工程（ｄ）と、
前記半導体チップを前記電気絶縁性基板にワイヤボンディング実装する工程（ｅ）と、
前記半導体チップと前記ワイヤボンディング実装部分を樹脂モールドする工程（ｆ）とを含む半導体装置の製造方法。Preparing a semiconductor chip and an electrically insulating substrate having a main surface on which a plurality of roughened surface metal wirings including electrode terminals on which the semiconductor chip is wire-bonded and mounted are formed (a);
A step (b) of forming a photoresist on a portion other than the electrode terminals of the main surface of the electrically insulating substrate on which the semiconductor chip of the electrically insulating substrate is mounted by photolithography;
(C) removing the photoresist after performing electroless gold plating on the main surface of the electrically insulating substrate to be wire-bonded and mounted to form gold on the electrode terminal surface;
Bonding the principal surface opposite to the surface on which the element electrodes of the semiconductor chip are formed to the electrically insulating substrate (d);
A step (e) of wire bonding mounting the semiconductor chip to the electrically insulating substrate;
A method of manufacturing a semiconductor device, comprising: a step (f) of resin-molding the semiconductor chip and the wire bonding mounting portion. 複数の半導体チップが積層された積層半導体チップをワイヤボンディング実装、もしくはフリップチップ実装及びワイヤボンディング実装によって前記電気絶縁性基板に実装した請求項１６又は１７に記載の半導体装置の製造方法。  18. The method of manufacturing a semiconductor device according to claim 16, wherein a laminated semiconductor chip in which a plurality of semiconductor chips are laminated is mounted on the electrically insulating substrate by wire bonding mounting, or flip chip mounting and wire bonding mounting. 半導体チップと、前記半導体チップがフリップチップ実装される電極端子を含む複数の粗化処理された表面の金属配線が形成された主面をもつ第１の電気絶縁性基板と、複数の金属配線が形成された主面をもつ第２の電気絶縁性基板と、無機フィラーと熱硬化性樹脂とを含む混合物からなる第３の電気絶縁性基板である板状体を準備する工程（ａ）と、
フォトリソグラフィー法によって、前記第１の電気絶縁性基板の前記半導体チップがフリップチップ実装される主面の、前記電極端子以外の部分に、フォトレジストを形成する工程（ｂ）と、
前記第１の電気絶縁性基板のフリップチップ実装される主面に無電解金メッキを行なって、前記電極端子表面に金を形成した後、フォトレジストを除去する工程（ｃ）と、
前記半導体チップの素子電極面と前記電気絶縁性基板の電極端子面との間に封止樹脂を介して、前記半導体チップを前記電気絶縁性基板にフリップチップ実装する工程（ｄ）と、
前記板状体に貫通孔を形成し、前記貫通孔に導電性樹脂組成物からなる導電性ペーストを充填する工程（ｅ）と、
前記第１と第２の電気絶縁性基板及び前記板状体を、前記板状体の一方の主面に前記第１の電気絶縁性基板の前記半導体チップがフリップチップ実装された主面が向くように、もう一方の主面に前記第２の電気絶縁性基板の金属配線が形成された主面が向くように位置あわせし、積層する工程（ｆ）と、
加熱加圧して、前記第１と第２の電気絶縁性基板を前記板状体に接着し、前記半導体チップを前記板状体に埋設して一体化し、前記板状体及び前記導電性樹脂組成物からなる導電性ペーストを硬化させる工程（ｇ）とを含む半導体装置の製造方法。A first electrically insulating substrate having a main surface on which a plurality of roughened surface metal wirings including an electrode terminal on which the semiconductor chip is flip-chip mounted; and a plurality of metal wirings; A step (a) of preparing a plate-like body which is a second electrically insulating substrate having a formed main surface and a third electrically insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin;
A step (b) of forming a photoresist on a portion other than the electrode terminals on a main surface of the first electrically insulating substrate on which the semiconductor chip is flip-chip mounted by a photolithography method;
(C) removing the photoresist after performing electroless gold plating on the main surface of the first electrically insulating substrate to be flip-chip mounted to form gold on the electrode terminal surface;
A step (d) of flip-chip mounting the semiconductor chip on the electrically insulating substrate via a sealing resin between an element electrode surface of the semiconductor chip and an electrode terminal surface of the electrically insulating substrate;
A step (e) of forming a through hole in the plate-like body and filling the through hole with a conductive paste made of a conductive resin composition;
The first and second electrically insulating substrates and the plate-like body face the main surface on which one of the main surfaces of the plate-like body is flip-chip mounted with the semiconductor chip of the first electrically insulating substrate. A step (f) of aligning and laminating the main surface on which the metal wiring of the second electrically insulating substrate is formed on the other main surface,
The first and second electrically insulating substrates are bonded to the plate-like body by heating and pressurizing, and the semiconductor chip is embedded and integrated in the plate-like body. The plate-like body and the conductive resin composition A step (g) of curing a conductive paste made of a product. 前記電極端子表面の金の形成方法は、電解メッキ、蒸着又はスパッタである請求項１６〜１９のいずれかに記載の半導体装置の製造方法。  The method of forming a gold on the electrode terminal surface is electrolytic plating, vapor deposition, or sputtering, according to any one of claims 16 to 19. 前記第３の電気絶縁性基板は、前記無機フィラーと熱硬化性樹脂とを含む混合物からなる請求項１９に記載の半導体装置の製造方法。  The method for manufacturing a semiconductor device according to claim 19, wherein the third electrically insulating substrate is made of a mixture containing the inorganic filler and a thermosetting resin.
JP2006526475A 2005-03-23 2006-03-08 Semiconductor device and manufacturing method thereof Pending JPWO2006100909A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2005084656 2005-03-23
JP2005084656 2005-03-23
PCT/JP2006/304443 WO2006100909A1 (en) 2005-03-23 2006-03-08 Semiconductor device and method for manufacturing same

Publications (1)

Publication Number Publication Date
JPWO2006100909A1 true JPWO2006100909A1 (en) 2008-09-04

Family

ID=37023583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006526475A Pending JPWO2006100909A1 (en) 2005-03-23 2006-03-08 Semiconductor device and manufacturing method thereof

Country Status (4)

Country Link
JP (1) JPWO2006100909A1 (en)
KR (1) KR20070117991A (en)
CN (1) CN1943029A (en)
WO (1) WO2006100909A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220254571A1 (en) * 2021-02-05 2022-08-11 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4803060B2 (en) * 2007-02-09 2011-10-26 凸版印刷株式会社 Electronic component built-in substrate, electronic module, electronic device, and method of manufacturing electronic component built-in substrate
US9214442B2 (en) * 2007-03-19 2015-12-15 Infineon Technologies Ag Power semiconductor module, method for producing a power semiconductor module, and semiconductor chip
JP2010258277A (en) * 2009-04-27 2010-11-11 Dainippon Printing Co Ltd Wiring board with built-in component
JP2010267845A (en) * 2009-05-15 2010-11-25 Dainippon Printing Co Ltd Component built-in wiring board and method of manufacturing the component built-in wiring board
US8358002B2 (en) 2009-12-23 2013-01-22 Marvell World Trade Ltd. Window ball grid array (BGA) semiconductor packages
JP5590097B2 (en) * 2012-10-29 2014-09-17 大日本印刷株式会社 Component built-in wiring board
WO2015013399A1 (en) * 2013-07-24 2015-01-29 Cooledge Lighting Inc. Light-emitting dies incorporating wavelength-conversion materials and related methods
KR102207273B1 (en) * 2014-01-29 2021-01-25 삼성전기주식회사 Package substrate
CN105826295B (en) * 2015-01-07 2019-01-29 中芯国际集成电路制造(上海)有限公司 Interconnection structure and forming method thereof
KR101971493B1 (en) * 2017-09-29 2019-04-23 서울과학기술대학교 산학협력단 Ag-coated Cu pillar bonding structure and bonding method using the Ag-coated Cu pillars
TWI646877B (en) * 2018-03-12 2019-01-01 Chipbond Technology Corporation Wiring circuit structure of flexible circuit board
CN113594151A (en) * 2021-06-25 2021-11-02 苏州汉天下电子有限公司 Semiconductor package and method of manufacturing the same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000236037A (en) * 1999-02-15 2000-08-29 Sumitomo Metal Mining Co Ltd Solder resist forming method
JP2001313314A (en) * 2000-04-28 2001-11-09 Sony Corp Semiconductor device using bump, its manufacturing method, and method for forming bump
JP2002184811A (en) * 2000-12-11 2002-06-28 Sony Corp Electronic circuit device and its manufacturing method
JP2003218148A (en) * 2002-01-18 2003-07-31 Seiko Epson Corp Semiconductor integrated circuit and its manufacturing method, circuit board, and electronic instrument
JP2003318363A (en) * 2002-04-25 2003-11-07 Sharp Corp Salient electrode bonded type semiconductor device and method of manufacturing the same
JP2004193392A (en) * 2002-12-12 2004-07-08 Matsushita Electric Ind Co Ltd Circuit component incorporating module and its manufacturing method

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3381602B2 (en) * 1998-01-27 2003-03-04 松下電器産業株式会社 Electronic component manufacturing method
JP3561209B2 (en) * 2000-05-24 2004-09-02 株式会社三井ハイテック Flip chip mounting binder and method of manufacturing semiconductor device using the same
JP3547423B2 (en) * 2000-12-27 2004-07-28 松下電器産業株式会社 Component built-in module and manufacturing method thereof
JP3688249B2 (en) * 2002-04-05 2005-08-24 Ｎｅｃエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP2005039227A (en) * 2003-07-03 2005-02-10 Matsushita Electric Ind Co Ltd Module with built-in semiconductor, and its manufacturing method

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000236037A (en) * 1999-02-15 2000-08-29 Sumitomo Metal Mining Co Ltd Solder resist forming method
JP2001313314A (en) * 2000-04-28 2001-11-09 Sony Corp Semiconductor device using bump, its manufacturing method, and method for forming bump
JP2002184811A (en) * 2000-12-11 2002-06-28 Sony Corp Electronic circuit device and its manufacturing method
JP2003218148A (en) * 2002-01-18 2003-07-31 Seiko Epson Corp Semiconductor integrated circuit and its manufacturing method, circuit board, and electronic instrument
JP2003318363A (en) * 2002-04-25 2003-11-07 Sharp Corp Salient electrode bonded type semiconductor device and method of manufacturing the same
JP2004193392A (en) * 2002-12-12 2004-07-08 Matsushita Electric Ind Co Ltd Circuit component incorporating module and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20220254571A1 (en) * 2021-02-05 2022-08-11 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component

Also Published As

Publication number Publication date
CN1943029A (en) 2007-04-04
WO2006100909A1 (en) 2006-09-28
KR20070117991A (en) 2007-12-13

Similar Documents

Publication Publication Date Title
JPWO2006100909A1 (en) Semiconductor device and manufacturing method thereof
US9226382B2 (en) Printed wiring board
US7022399B2 (en) Semiconductor device integrated multilayer wiring board
US9338886B2 (en) Substrate for mounting semiconductor, semiconductor device and method for manufacturing semiconductor device
JP2004335641A (en) Method of manufacturing substrate having built-in semiconductor element
KR101055509B1 (en) Electronic component embedded printed circuit board
JP2008218926A (en) Semiconductor and method of manufacturing the same
US8288865B2 (en) Semiconductor module having semiconductor device mounted on device mounting substrate
TW200908262A (en) Mounting substrate and manufacturing method thereof
KR100642356B1 (en) Semiconductor device and mu1ti1ayer substrate therefor
JP4337358B2 (en) Intermediate wiring member for stacking, wiring board, and manufacturing method thereof
JP4242777B2 (en) CONNECTION BOARD, MULTILAYER WIRING BOARD, SEMICONDUCTOR PACKAGE BOARD AND SEMICONDUCTOR PACKAGE USING THE CONNECTION SUBSTRATE, AND MANUFACTURING METHOD THEREOF
JP2005109307A (en) Board with built-in circuit part, and manufacturing method of the same
JP4449975B2 (en) Connection board, multilayer wiring board using the connection board, and methods of manufacturing the same
KR20040070190A (en) Anisotropically electroconductive adhesive film, method for the production thereof, and semiconductor devices
JP5176676B2 (en) Manufacturing method of component-embedded substrate
WO2020090601A1 (en) Semiconductor packaging wiring substrate and method of manufacturing semiconductor packaging wiring substrate
JP2004179647A (en) Wiring board, semiconductor package, and method for producing base insulating film and wiring board
JP2009004813A (en) Wiring substrate for mounting semiconductor
JPH10335528A (en) Semiconductor package and manufacture thereof
JP2011204811A (en) Module with built-in circuit part and manufacturing method thereof
JP4324732B2 (en) Manufacturing method of semiconductor device
JP2004071946A (en) Wiring substrate, substrate for semiconductor package, semiconductor package, and their manufacturing method
JP2008147266A (en) Semiconductor device and its manufacturing method
KR20150043135A (en) printed circuit board which includes metal layer and semiconductor package including the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20081107

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110705

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110810

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20111108

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120403

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060830