CN113594151A - Semiconductor package and method of manufacturing the same - Google Patents

Semiconductor package and method of manufacturing the same Download PDF

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Publication number
CN113594151A
CN113594151A CN202110714994.3A CN202110714994A CN113594151A CN 113594151 A CN113594151 A CN 113594151A CN 202110714994 A CN202110714994 A CN 202110714994A CN 113594151 A CN113594151 A CN 113594151A
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China
Prior art keywords
substrate
chip
semiconductor package
sealant
structures
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Pending
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CN202110714994.3A
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Chinese (zh)
Inventor
郜振豪
杨清华
唐兆云
赖志国
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Suzhou Huntersun Electronics Co Ltd
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Suzhou Huntersun Electronics Co Ltd
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Priority to CN202110714994.3A priority Critical patent/CN113594151A/en
Publication of CN113594151A publication Critical patent/CN113594151A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Abstract

The invention provides a semiconductor package and a method of manufacturing the same, comprising: a substrate including a plurality of barrier structures surrounding a chip mounting area; a chip flip-chip bonded on the chip mounting region; a first sealant covering the chip on the chip mounting region; and a second sealant covering the first sealant on the substrate. According to the semiconductor package and the method of manufacturing the same of the present invention, the barrier structure is employed around each chip on the substrate to prevent moisture penetration, enhance adhesion, and simultaneously prevent the sealant from overflowing, thereby effectively improving the reliability of the package.

Description

Semiconductor package and method of manufacturing the same
Technical Field
The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package and a method of manufacturing the same capable of effectively preventing moisture from penetrating and simultaneously preventing an overflow of a sealant.
Background
The rapid development of microelectronic technology and the increasing complexity of integrated circuits, most functions of an electronic system may be integrated in a single chip (i.e., system-on-chip), which in turn requires microelectronic packages with higher performance, more leads, denser interconnections, smaller size or larger chip cavities, greater heat dissipation capability, better electrical performance, higher reliability, lower individual lead cost, etc.
With the increasing development of semiconductor technology, the wafer process technology is also continuously improved to meet the demands of the semiconductor industry. On the other hand, due to the continuous improvement of the wafer process technology, the conventional package testing technology is gradually eliminated from the market, so that the package testing technology is also developed to cope with the change of the semiconductor industry.
Specifically, in the prior art, more than one semiconductor component, especially different kinds of chips, such as a memory chip and a logic control chip, a light emitting chip (LED, laser, etc.) and a light sensor chip (photodiode, etc.), a digital IC and an analog IC, an active device and a passive device (e.g., a network formed by R, L, C, etc.) are often mounted in the same semiconductor package. These components operate under different application conditions, and different requirements for individual packaging performance are provided, so that sealants with different performances need to be adopted in the same package.
In the device temperature and humidity environment reliability experiments performed on these packages, moisture infiltration is one of the important causes of failure due to the influence on the airtightness. There are two main ways moisture can penetrate into the device: the plastic packaging material is used for encapsulating the layer body, or a gap between the plastic packaging material encapsulating layer and the packaging substrate is used. In the conventional packaging technology, due to the difference of chip mounting processes, the existing sealant used for one chip is easily affected by temperature and pressure during the subsequent packaging process of other chips to reduce the adhesive force between the chip and the substrate, and moisture is easy to intrude from the slits to cause the failure of the semiconductor element. In addition, the flowing performance of different sealants is different, the previous sealant is easily overflowed by the influence of the subsequent sealing process, and the flowing sealant may cause the pads on the substrate where the chip is not mounted to be polluted or shielded, thereby influencing the interconnection reliability of the subsequent semiconductor element.
Disclosure of Invention
Accordingly, an object of the present invention is to overcome the above technical obstacles and to provide an innovative semiconductor package and a method of manufacturing the same, which employs a barrier structure around each chip on a substrate to prevent moisture penetration, enhance adhesive force, and simultaneously prevent an overflow of a sealant, thereby effectively improving reliability of the package.
The present invention provides a semiconductor package, comprising:
a substrate including a plurality of barrier structures surrounding a chip mounting area;
a chip flip-chip bonded on the chip mounting region;
a first sealant covering the chip on the chip mounting region;
and a second sealant covering the first sealant on the substrate.
Wherein the chips comprise a plurality of chips of the same or different types, and a plurality of barrier structures surround each chip. Wherein different additives are added to the barrier structures around the chips of different types or on the surfaces thereof, or to the first encapsulant on the chips of different types. Wherein the additive comprises electrically conductive particles, colored particles, light reflective particles, chemical modifiers, refractory agent particles, high hardness particles, wavelength converting particles, or thermally conductive particles.
The plurality of barrier structures are rough surfaces or concave-convex structures obtained by processing the surface of the substrate, or bank structures formed on the surface of the substrate.
Wherein the plurality of barrier structures are horizontal periodic or non-periodic structures having a thickness on a substrate normal line or curved distribution structures having a height difference on the substrate normal line.
The barrier structures are line segments or curves which are parallel to each other in a plan view, or a grid formed by cross-linking a plurality of line segments or curves.
Wherein the chip or the first encapsulant partially overlaps the plurality of barrier structures in a plan view.
The invention further provides a semiconductor package manufacturing method, which comprises the following steps:
forming a plurality of barrier structures on the substrate surrounding one or more chip mounting regions;
flip-chip mounting the one or more chips on the one or more chip mounting areas of the substrate;
forming one or more first encapsulants to cover the one or more chips within the one or more chip mounting areas;
a second sealant is formed on the substrate to cover all of the first sealant.
Wherein the thickness of the plurality of barrier structures is 10 to 100 microns.
According to the semiconductor package and the method of manufacturing the same of the present invention, the barrier structure is employed around each chip on the substrate to prevent moisture penetration, enhance adhesion, and simultaneously prevent the sealant from overflowing, thereby effectively improving the reliability of the package.
The stated objects of the invention, as well as other objects not listed here, are met within the scope of the independent claims of the present application. Embodiments of the invention are defined in the independent claims, with specific features being defined in the dependent claims.
Drawings
The technical solution of the present invention is explained in detail below with reference to the accompanying drawings, in which:
FIG. 1 shows a cross-sectional view of a semiconductor package according to one embodiment of the present invention;
FIG. 2 shows a plan view of a surface of a substrate in the semiconductor package of FIG. 1;
fig. 3 shows a cross-sectional view of a semiconductor package according to another embodiment of the present invention;
FIG. 4 shows a plan view of a surface of a substrate in the semiconductor package of FIG. 3; and
fig. 5 shows a flow chart of a method of manufacturing a semiconductor package according to an embodiment of the invention.
Detailed Description
Features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings in conjunction with exemplary embodiments, disclosing a semiconductor package and a method of manufacturing the same that effectively improves package reliability. It is noted that like reference numerals refer to like structures and that the terms "first", "second", "upper", "lower", and the like as used herein may be used to modify various device structures. These modifications do not imply a spatial, sequential, or hierarchical relationship to the structures of the modified devices unless specifically stated.
As shown in fig. 1 and 2, a semiconductor package according to a preferred embodiment of the present invention includes a substrate 1, one or more chips 2, a first sealant 6A, and a second sealant 6B. The substrate 1 is, for example, a Printed Circuit Board (PCB) including a plurality of insulating layers made of an organic (e.g., resin) or inorganic material, a metal interconnection layer or a redistribution layer (RDL) disposed between the respective insulating layers as required for wiring, and a plurality of pads 1B on a top surface of the substrate. In addition, the substrate 1 may also be a lead frame (lead frame) with metal traces encapsulated by an encapsulant and pads on the top surface of the traces.
The chip 2 may be a variety of commonly used semiconductor chips such as silicon-based logic/memory circuits fabricated on a CMOS process, power devices fabricated on a bipolar or BiMOS process, Light Emitting Diodes (LEDs) or photodiodes (LDs) based on III-V or II-VI compounds, and the like. The bottom of the chip 2 includes a plurality of metal traces or pads 3, for example made of Al, Cu, Mo, W, Pt, Ni and alloys thereof, which serve as input/output of electrical signals inside the chip 2.
A suction nozzle is adopted to core from the wafer and simultaneously paste the bumps 4 of the chip on the chip mounting area or the substrate welding area. Specifically, metal bumps (bump)4, preferably Cu, Sn, Al, Ag, Ni, Au, Pt, Pd, and alloys thereof, are provided on the pads 3 of the chip 2 by plating, electroless plating, bonding, pressing, conductive adhesive bonding, or the like, for providing sufficient mechanical support during flip-chip reflow soldering of the chip 2, preventing solder ball displacement, and at the same time, a solderable material is also preferable to promote bonding strength with solder balls. The metal bump 4 is formed with a solder ball 5, and the solder ball 5 is brought into contact with and soldered to a pad 1B on the surface of the substrate 1 to realize physical and electrical connection. The metal bumps 4 are generally circular in cross-section so that the solder balls 5 are evenly distributed over the bump surface during reflow without overflowing from the sharp corners or protrusions to the sidewalls. The material of the solder balls 5 may be a lead-based solder or a lead-free solder. Preferably, a flux or solder paste (not shown) may be further provided between the solder balls 5 and the pads 1B on the top surface of the substrate 1, so as to improve the reliability of the soldering with the substrate.
In the case where a semiconductor package includes a plurality of chips 2 of different kinds, the sealing environment required for each chip 2 may be different, and chips such as LEDs, LDs, etc. have high requirements for optical functions such as light transmittance, wavelength conversion, etc. of the sealant, while control logic, memories, etc. have high requirements for prevention of permeation of the sealant and resistance to electromagnetic interference, and thus it is necessary to perform successive sealing with the same kind of sealant after the chips of the same kind are mounted, and then perform batch sealing with another kind of sealant for another kind of chips. In the process, due to different flowability of the sealant, the pad 1B on the substrate is easily polluted or shielded, and due to different thermal stability of the sealant, the sealant in the first step is easily peeled off in the subsequent process.
For this reason, in the present application, during the step of providing the substrate 1 before the chip 2 is mounted, a plurality of barrier structures 1A are provided at least at the periphery of each chip mounting area for enhancing the adhesive force between the substrate and the sealant to prevent the sealant from peeling off, and the permeation of moisture from the interface gap between the package and the substrate can be effectively reduced. In addition, the barrier structure 1A can also prevent the sealant from overflowing outwards, and can effectively ensure that the substrate pad is not affected and ensure the reliability of electrical interconnection.
The plurality of barrier structures 1A may be, for example, a rough surface or a concave-convex structure formed by a subtractive process such as mechanical cutting or laser ablation directly on the substrate 1, or may be a bank or dam structure formed by an additive process of coating or printing a barrier material (for example, an epoxy resin) on a flat surface of the substrate 1. As shown in fig. 1, the plurality of barrier structures 1A may be a horizontal periodic or non-periodic structure having a thickness on the substrate normal line (for example, less than 5% of the thickness of the sealant 6A, such as 10 to 100 micrometers and preferably 20 to 70 micrometers, although shown as a substantially horizontal band-like structure in fig. 1, but may actually have a height difference in the normal direction, such as various curved distributions of a central bump and two side depressions, two side bumps and a central depression, or a staggered repetition of a portion of a bump and another portion of a depression, thereby enhancing the moisture barrier ability by effectively extending the moisture permeation path length, whereas as shown in fig. 2, the plurality of barrier structures 1A surround at least the chip mounting region (shown as a box outside the pad 1B in the figure, corresponding to the sealant 6A distribution region in fig. 1) as viewed from the top surface, the planar shape is not limited to that shown in fig. 2 and may be various straight or curved line segments or periodic or non-periodic structures formed therefrom, such as an array. Preferably, the plurality of barrier structures 1A are distributed at the edge of the substrate 1, thereby effectively shortening the distance of moisture penetration from the side. Preferably, the plurality of barrier structures 1A extend inwardly from the chip mounting area (corresponding to the area where the first encapsulant 6A is distributed in fig. 1) for a distance (for example, 50% or less of the distance between the encapsulant 6A and the outer side of the substrate pad 1B), thereby allowing the first encapsulant 6A (or even the chip 2) to partially overlap the plurality of barrier structures 1A in plan view, thereby further enhancing the adhesive force between the substrate 1 and the first encapsulant 6A and avoiding the peeling problem that may exist with different kinds of first encapsulants 6A during different processes.
Preferably, in order to meet individual requirements of different kinds of chips 2 for packaging, additives may also be added in or on the surfaces of the plurality of barrier structures 1A: in order to effectively improve the anti-electromagnetic interference capability, graphite powder, graphene segments, silver powder and other conductive particles are added to form a grounding loop; in order to prevent light leakage at the side surface or the bottom surface of the top-emitting LED, colored particles such as melanin and dye are added to form a light absorption layer, or reflective particles such as silver powder, magnesium powder, zinc oxide and titanium oxide are added to form a reflective layer so as to improve the light extraction efficiency of the bottom-emitting or side-emitting LED; in order to improve the adhesive strength between the substrate and the sealant, a proper cross-linking agent, a coupling agent or a surface modifier can be selected for the organic insulating material adopted by the substrate and the organic insulating material adopted by the sealant, so that cross-linked molecular chains are generated between the substrate and the sealant; in order to improve heat resistance or pressure resistance, refractory particles or high hardness particles such as zirconia, titania, manganese oxide, ceria, and the like may be added.
After flip-chip mounting of the chip 2, the first encapsulant 6A is applied by a low or normal temperature process such as spin coating, spray coating, screen printing, etc., completely encapsulating the chip 2, the pads 3, the bumps 4 and the solder balls 5, and simultaneously covering the pads 1B on the substrate 1 (and preferably partially covering a portion of the plurality of barrier structures 1A on the substrate 1), securing the chip 2 on the substrate. The first sealing agent 6A may be various commonly used sealing organic materials such as epoxy resin, phenol resin, amide resin, polyester resin, and the like. Preferably, to meet the individual requirements of different kinds of chips 2 for packaging, different additives are added in the first encapsulant 6A on different chips 2: adding electrically conductive particles to combat electromagnetic interference, adding wavelength converting particles (organic dyes or pigments, quantum dots, phosphors or phosphors, etc.) to change the color of the light emitted by the LED, adding thermally conductive particles (insulating thermally conductive ceramic particles of alumina, aluminum nitride, titanium nitride, etc.) to improve heat dissipation, adding colored or reflective particles to change the optical properties of the LED, etc.
After the flip-chip bonding of the respective semiconductor chips 2 is completed, the second sealant 6B is applied over the entire substrate 1, completely covering the remaining area of the substrate 1 and all of the first sealant 6A, completing the final semiconductor package. Preferably, the width of the barrier structure 1A covered by the second sealant 6B is greater than or equal to 5 times and less than or equal to 30 times the width of the barrier structure 1A covered by the first sealant 6A, so as to effectively enhance the bonding strength between the second sealant 6B and the substrate 1 as a whole and coordinate the stress distribution at the interface between the first sealant 6A and the second sealant 6B, thereby preventing the peeling phenomenon possibly existing at the interface between the two.
And then, according to the electrical function realized by the packaging structure, cutting each packaging body into semi-finished products by adopting mechanical saw blade cutting or laser scanning cutting, carrying out reliability test such as environment temperature-humidity/bias test on each semi-finished product, selecting qualified products and finishing final finished product packaging. In this process, it is preferable to use a plurality of barrier structures as the dicing area, since the barrier structures have various additives according to the requirement of the encapsulant 6A, and these additives can effectively reduce the damage at the dicing cuts, and ensure the reliability of the package.
Fig. 3 and 4 show a cross-sectional view and a top view of a semiconductor package according to further embodiments of the present invention, wherein a substrate 1 has a plurality of semiconductor chips 2 thereon, each semiconductor chip 2 being surrounded by a respective first encapsulant 6A, and a second encapsulant 6B covering all of the first encapsulant 6A and the remaining substrate 1, wherein a plurality of barrier structures 1A are distributed not only around the periphery of the substrate 1, but also between the individual semiconductor chips 2 on the substrate 1 so as to surround the individual semiconductor chips 2 in plan view.
As shown in fig. 5, the method for manufacturing the semiconductor package according to the above preferred embodiment of the present invention includes the steps of:
forming a plurality of barrier structures surrounding the chip mounting region(s) on the substrate 1;
flip-chip(s) 2 on substrate 1;
forming a first sealant(s) 6A inside the plurality of barrier structures 1A of the substrate 1 on the chip 2;
the second sealant 6B is formed on the substrate 1 and (all) the first sealant 6A.
According to the semiconductor package and the method of manufacturing the same of the present invention, the barrier structure is employed around each chip on the substrate to prevent moisture penetration, enhance adhesion, and simultaneously prevent the sealant from overflowing, thereby effectively improving the reliability of the package.
While the invention has been described with reference to one or more exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the disclosed device structure and its method of manufacture will include all embodiments falling within the scope of the present invention.

Claims (10)

1. A semiconductor package, comprising:
a substrate including a plurality of barrier structures surrounding a chip mounting area;
a chip flip-chip bonded on the chip mounting region;
a first sealant covering the chip on the chip mounting region;
and a second sealant covering the first sealant on the substrate.
2. The semiconductor package of claim 1, wherein the chip comprises a plurality of chips of the same or different types, a plurality of barrier structures surrounding each chip.
3. The semiconductor package of claim 2, wherein different additives are added to the plurality of barrier structures around the plurality of chips of different types or to the first encapsulant on the plurality of chips of different types.
4. A semiconductor package according to claim 3, wherein the additive comprises electrically conductive particles, colored particles, light reflecting particles, chemical modifiers, refractory agent particles, high hardness particles, wavelength converting particles, or thermally conductive particles.
5. The semiconductor package according to claim 1, wherein the plurality of barrier structures are rough surfaces or concave-convex structures processed on the surface of the substrate, or bank structures formed on the surface of the substrate.
6. The semiconductor package of claim 1, wherein the plurality of barrier structures are horizontally periodic or aperiodic structures with thickness on the substrate normal, or curvilinear profile structures with height differences on the substrate normal.
7. The semiconductor package of claim 1, wherein the plurality of barrier structures have a thickness of 10 to 100 microns.
8. The semiconductor package of claim 1, wherein the chip or the first encapsulant partially overlaps the plurality of barrier structures in a plan view.
9. A semiconductor package manufacturing method, comprising the steps of:
forming a plurality of barrier structures on the substrate surrounding one or more chip mounting regions;
flip-chip mounting the one or more chips on the one or more chip mounting areas of the substrate;
forming one or more first encapsulants to cover the one or more chips within the one or more chip mounting areas;
a second sealant is formed on the substrate to cover all of the first sealant.
10. The semiconductor package manufacturing method according to claim 9, wherein after the second sealant is formed, the respective chips are cut and separated using a part of the plurality of barrier structures as a dicing area.
CN202110714994.3A 2021-06-25 2021-06-25 Semiconductor package and method of manufacturing the same Pending CN113594151A (en)

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