WO2006100909A1 - Semiconductor device and method for manufacturing same - Google Patents

Semiconductor device and method for manufacturing same Download PDF

Info

Publication number
WO2006100909A1
WO2006100909A1 PCT/JP2006/304443 JP2006304443W WO2006100909A1 WO 2006100909 A1 WO2006100909 A1 WO 2006100909A1 JP 2006304443 W JP2006304443 W JP 2006304443W WO 2006100909 A1 WO2006100909 A1 WO 2006100909A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating substrate
electrically insulating
semiconductor chip
chip
semiconductor device
Prior art date
Application number
PCT/JP2006/304443
Other languages
French (fr)
Japanese (ja)
Inventor
Shingo Komatsu
Seiichi Nakatani
Koichi Hirano
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Priority to JP2006526475A priority Critical patent/JPWO2006100909A1/en
Publication of WO2006100909A1 publication Critical patent/WO2006100909A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0652—Bump or bump-like direct electrical connections from substrate to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01045—Rhodium [Rh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/183—Connection portion, e.g. seal
    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device in which a semiconductor chip is mounted on an electrode terminal having a gold layer formed on the surface of an electrically insulating substrate, and a method of manufacturing the same.
  • Semiconductor devices are smaller in size, thinner and higher in performance for information communication devices, office electronic devices, home electronic devices, measuring devices, industrial electronic devices such as assembly robots, medical electronic devices and the like. Greatly contribute to In particular, in the field of information and communication equipment, the demand for miniaturization is large. With the aim of achieving high density and high functionality of semiconductor devices, stacked semiconductor chips with stacked semiconductor chips mounted on an electrically insulating substrate, From the conventional two-dimensional mounting method of mounting electronic components on the surface of an electrically insulating substrate, the development of a three-dimensional mounting method that incorporates electronic components in the electrically insulating substrate and significantly reduces the mounting area It is actively conducted.
  • the manufacture of a semiconductor device requires a semiconductor chip and an electrically insulating substrate on which the semiconductor chip is mounted.
  • the mounting technology for mounting a semiconductor chip on an electrically insulating substrate can be roughly divided into wire bonding mounting and flip chip mounting.
  • wire bonding mounting which is a conventional technology, as shown in FIG. 9, a surface opposite to the surface on which the element electrode 902 of the semiconductor chip 901 is formed is bonded to the electrically insulating substrate 904 using a die bonding material 910.
  • the element electrode force of the semiconductor chip is gold 908 formed on the surface of the electrically insulating substrate.
  • the electrode terminal 906 is electrically connected with the gold wire 903, and the semiconductor chip and the gold wire part are molded resin 909 overall. Molding method.
  • the mounting area of the semiconductor chip can be reduced, and has recently become mainstream!
  • Flip chip mounting in which the element electrode surface of the semiconductor chip faces the electrode terminal of the electrically insulating substrate , Electrical connection method.
  • Sealing resin 1009 protects the electrical connection portion by means of electrical connection via
  • the flip chip mounting is conducted between the element electrode of the semiconductor chip such as ACF (Anisotropic Conductive Film) connection and ACP (Anisotropic Conductive Paste) connection depending on the type of sealing resin and the electrical connection method, and between the electrode terminals of the electrically insulating substrate.
  • the metal wiring on the semiconductor chip mounting surface of the electrically insulating substrate, including the electrode terminals on which the semiconductor chip is mounted is surface-plated by gold plating or the like. Gold is formed, and by maintaining the cleanliness of the surface mainly, good electrical connection is made between the semiconductor chip and the electrode terminal of the electrically insulating substrate.
  • Patent Documents 1 and 2 a semiconductor device in which the laminated semiconductor chip shown in FIG. 11 is mounted on an electrically insulating substrate
  • Patent Documents 1 and 2 a semiconductor device in which the laminated semiconductor chip shown in FIG. 11 is mounted on an electrically insulating substrate
  • Patent Document 3 The electronic component shown in FIG. 1 is incorporated in an electrically insulating substrate, and electrical connection is made by an inner via filled with a conductive resin composition in the same layer of the insulating substrate as the incorporated semiconductor chip.
  • Patent Document 3 component built-in module which dramatically improves the mounting density with respect to mounting.
  • Patent Document 4 there is also a proposal for forming a reinforcing metal wiring between a semiconductor chip and an electrically insulating substrate in a semiconductor device in which the semiconductor chip is flip-chip mounted.
  • the gold layer on the surface of the metal wiring of the electrically insulating substrate which is usually essential for wire bonding mounting and flip chip mounting, may adversely affect the reliability of the electrical connection.
  • the gold layer is not oxidized and clean, and has adequate flexibility for crimping a gold wire used for wire bonding mounting and a bump of a semiconductor chip at flip chip mounting, and has good electrical insulation with a semiconductor chip
  • the gold layer is smooth and the adhesion to the resin is poor, for example, simply by roughening the surface as in the case of a copper surface. It is difficult to increase adhesion to resin, and there are problems with o
  • ACF connection, ACP is the first problem of semiconductor devices caused by the characteristics of this gold layer.
  • NCF connection, NCP connection, ultrasonic bonding, etc. gold chip formed on the element electrode of the semiconductor chip and gold layer of metal wiring of the electrical insulating substrate are connected electrically by pressure welding.
  • the adhesion between the resin and the electrically insulating substrate is poor.
  • the element electrodes of the semiconductor chip and the gold layer of the metal wiring of the electrical insulating substrate are electrically connected using a gold wire, and the semiconductor chip and the gold wire are molded with a mold resin.
  • a mold resin for maintaining and protecting the contact between the gold wire and the gold layer of the metal wiring and the shape of the gold wire is subjected to a thermal shock in the moisture absorption reflow test.
  • the mold resin and the electrically insulating substrate are easily peeled off, and the peeled interface similarly causes an electric connection failure due to the onset. there were.
  • the above problems may depend on the area of the metal wiring of the gold layer, and the reliability may change depending on the design pattern of the metal wiring of the electrically insulating substrate even under the same manufacturing conditions immediately. It was very difficult to secure sex.
  • Patent Document 4 in a semiconductor device in which a semiconductor chip is flip-chip mounted, there is also a method of forming a reinforcing metal wire between the semiconductor chip and the electrically insulating substrate, It is necessary to reduce the degree of freedom in the design pattern of the metal wiring because it requires various metal wiring.
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2000-349228
  • Patent Document 2 Japanese Patent Application Laid-Open No. 2004-228323
  • Patent Document 3 Japanese Patent Application Laid-Open No. 11-220262
  • Patent Document 4 Japanese Patent Application Publication No. 2004-153210
  • the present invention provides a semiconductor device in which the reliability of electrical connection of a semiconductor device mounted with a semiconductor chip is improved, and a method of manufacturing the same.
  • a semiconductor chip is mounted on the surface of an electrically insulating substrate provided with a plurality of metal wires, and a semiconductor chip covers at least a part of the plurality of metal wires.
  • a gold layer is formed on the surface of at least a metal wire electrically connected to the semiconductor chip among the plurality of metal wires formed on the electrically insulating substrate, and the electric insulating property Among the plurality of metal wires formed on the substrate, a roughened portion is formed on the surface of the metal wire in contact with the resin.
  • a method of manufacturing a semiconductor device has a semiconductor chip, and a main surface on which a plurality of roughened surface metal wires including an electrode terminal on which the semiconductor chip is flip-chip mounted are formed.
  • the semiconductor chip is electrically connected through the sealing resin between the element electrode surface of the semiconductor chip and the electrode terminal surface of the electrically insulating substrate. And (f) mounting a flip chip on the insulating substrate.
  • a main surface on which a plurality of roughened surface metal wires including a semiconductor chip and electrode terminals on which the semiconductor chip is mounted by die bonding is formed.
  • Step (b) of forming a resist, and electroless gold plating is performed on the main surface of the electrically insulating substrate on which wire bonding is mounted to form gold on the surface of the electrode terminal, and then the step of removing the photoresist ( c) bonding the principal surface opposite to the surface on which the element electrode of the semiconductor chip is formed to the electrically insulating substrate (d), and using the semiconductor chip as the electrically insulating substrate
  • the ear bonding mounting to step (e) characterized in that it comprises a said semiconductor chip and the wire bonding mounting portions ⁇ mode one field to step (f).
  • a metal wire is formed on a plurality of roughened surfaces including a semiconductor chip and an electrode terminal on which the semiconductor chip is flip-chip mounted.
  • Step (b) of forming a photoresist on a portion other than the electrode terminal electroless gold plating is performed on the main surface of the first electrically insulating substrate flip-chip mounted, and gold is applied to the surface of the electrode terminal.
  • Do (D) forming a through hole in the plate-like body, and filling the through hole with a conductive paste comprising a conductive resin composition ( e ), the first and second electrical insulation Conductive substrate and the plate-like body, and the other main surface of the first electrically insulating substrate is flip-chip mounted on one main surface of the plate so that the main surface of the semiconductor chip of the first electrically insulating substrate faces the other main surface.
  • FIG. 1 is a cross-sectional view of a semiconductor device in Embodiment 1 of the present invention.
  • FIG. 2 is a cross-sectional view of a semiconductor device in Embodiment 2 of the present invention.
  • FIG. 3 is a cross-sectional view of a semiconductor device in Embodiment 3 of the present invention.
  • FIG. 4 is a cross-sectional view of a semiconductor device in Embodiment 4 of the present invention.
  • FIG. 5 is a cross-sectional view of the semiconductor device in Embodiment 5 and Example 1 of the present invention.
  • 6A to 6D are sectional views showing steps of a method of manufacturing a semiconductor device in a sixth embodiment of the present invention.
  • FIGS. 7A to 7E are process sectional views showing a method of manufacturing a semiconductor device according to Embodiment 7 of the present invention.
  • FIGS. 8A to 8I are process sectional views showing a method of manufacturing a semiconductor device in Embodiment 8 of the present invention.
  • FIG. 9 is a cross-sectional view showing an example of a conventional semiconductor device.
  • FIG. 10 is a cross sectional view showing another example of the conventional semiconductor device.
  • FIG. 11 is a cross-sectional view showing another example of the conventional semiconductor device.
  • FIG. 12 is a cross-sectional view showing another example of a conventional semiconductor device.
  • a gold layer is formed on the surface of the electrode terminal on which the semiconductor chip is mounted. Sealing in flip chip mounting by roughening the surface without forming a layer The bonding strength between the resin and the electrically insulating substrate, and between the mold resin and the electrically insulating substrate in wire bonding mounting is increased. By increasing the adhesive strength, the reliability of the electrical connection in the reliability test such as the moisture absorption reflow test can be improved. In addition, it is possible to reduce the influence of the design pattern of the metal wiring of the electrically insulating substrate of the sealing resin portion in flip chip mounting and the molded resin portion in wire bonding mounting on the electrical connection reliability.
  • the laminated semiconductor chip in which a plurality of semiconductor chips are laminated is electrically connected to the electrically insulating substrate by wire bonding or wire bonding mounting and flip chip mounting, so that the mold for wire bonding mounting is used.
  • the adhesive strength between the resin and the electrically insulating substrate and the sealing resin of the flip chip mounting can be increased, and the reliability in the reliability test such as the moisture absorption reflow test can be improved.
  • the number of bonded surfaces with resin and the area increase as compared with a single semiconductor chip, and locally larger stresses are generated at the corners and laminated interfaces between semiconductor chips in shape. It is easy to take.
  • securing the mounting reliability of the laminated semiconductor chip can be achieved by increasing the adhesive strength of the mounting surface of the force-electrically insulating substrate, which was more difficult than securing the mounting reliability of a single semiconductor chip.
  • the mounting reliability of the laminated semiconductor chip can be improved.
  • the adhesive strength between the flip chip mounting sealing resin and the electrically insulating substrate is improved to provide a surface mounted semiconductor chip.
  • the peeling stress between the sealing resin and the electrically insulating substrate is large, the reliability is high, the realization of the electrical connection is difficult, and the electrical connection in the reliability test such as the moisture absorption reflow test of the semiconductor device in the form of a module with a built-in component. Reliability can be improved.
  • the surface of the metal wiring electrically connected to the inner via filled with the conductive resin composition formed in the component built-in module is roughened, the resin is smooth and slippery, and the gold layer is formed. It is possible to suppress the positional deviation of the inner vias and to increase the adhesive strength between the inner vias and the metal wiring, so that it is possible to prevent the occurrence of peeling in various reliability tests. You can stay connected.
  • a portion of metal wiring including an electrode terminal of an electrically insulating substrate on which a semiconductor chip is mounted A gold layer is formed on the surface, and no gold layer is formed on the surface of the other metal wiring, and roughened! Is preferred.
  • Selective gold layer formation can be performed on the surface of metal wiring.
  • the selection of the metal wiring surface on which the gold layer is to be formed allows the formation of a gold layer formation photoresist with a simple design pattern.
  • electroless plating, electrolytic plating, vapor deposition, or sputtering is preferred.
  • the semiconductor device of the present invention can be manufactured using the existing gold layer forming technology as it is.
  • vapor deposition and sputtering can be formed by a dry process, which is more preferable as a simple method.
  • the flip chip mounting may be performed by a thermocompression bonding method using any of an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), a non conductive film (NCF), and a non conductive paste (NCP), or a semiconductor chip It is preferable that ultrasonic bonding be performed between a gold bump formed on the element electrode and a gold formed on the surface of the electrode terminal of the electrically insulating substrate.
  • the existing flip chip mounting technology can be used as it is.
  • gold wiring is used for the electrode terminal for mounting the semiconductor chip of the electrically insulating substrate to be mounted, and mounting is performed using sealing resin, molding resin, etc. A similar effect can be obtained in the mounting technology in the form of protecting the part.
  • the wiring is preferably roughened copper U ⁇ .
  • Copper wiring substrates can be manufactured inexpensively, and a wide variety of commercial products are easily available. In addition, it is easy to carry out surface roughening treatment. Besides copper, it may be an alloy containing copper.
  • the roughened copper foil may be a commercially available product, or a smooth copper foil can be formed by etching treatment with an etching solution, plasma treatment, polishing treatment with an abrasive, electrolysis, or the like.
  • the third electrically insulating substrate is preferably made of a mixture containing an inorganic filler and a thermosetting resin.
  • the thermoplastic resins contained in the first to third may be made of the same material.
  • the inorganic filler is preferably contained in an amount of 70% by weight to 95% by weight. If it is 95% by weight or more, the amount of liquid is too small relative to the amount of powder, making sheeting difficult. Further, when the content is 70% by weight or less, the effect of improving the heat dissipation and the like by mixing the inorganic filler is reduced. When the semiconductor chip is incorporated in the electrically insulating substrate by heat and pressure, the semiconductor chip is not damaged. If it is a viscosity, the blending ratio of the inorganic filler is large, and it is more preferable U ,.
  • the inorganic filler is at least one selected from Al 2 O, MgO, BN, A 1 N and SiO
  • it is an inorganic filler.
  • these inorganic fillers By using these inorganic fillers, a semiconductor device with excellent heat dissipation can be obtained. Also, when using SiO as the inorganic filler, the dielectric constant is small.
  • thermosetting resin is preferably at least one thermosetting resin selected from epoxy resin, phenol resin and cyanate resin.
  • thermosetting resin selected from epoxy resin, phenol resin and cyanate resin.
  • a wide variety of these resins are commercially available, and the use of these resins results in semiconductor devices having excellent heat resistance and electrical insulation.
  • the conductive resin composition preferably contains metal particles containing at least one metal selected from gold, silver, copper, and nickel as a conductive component, and preferably contains epoxy resin as a resin component.
  • the above-mentioned metals have low electric resistance, and epoxy resins are excellent in heat resistance and electric insulation.
  • metal particles in which the surface is coated with silver on the core material with copper powder are preferable because they have the properties of both copper powder which is strong in mechanical strength and is inexpensive, and silver powder which is difficult to be oxidized.
  • the existing flip chip mounting technology and the photolithography method can be used as they are, and the highly reliable semiconductor device of the present invention can be manufactured.
  • a semiconductor chip and an electrically insulating substrate having a main surface on which a metal wiring having a roughening treatment formed on a plurality of surfaces including an electrode terminal on which the semiconductor chip is mounted by wire bonding are prepared. And (b) forming a photoresist on a portion other than the electrode terminal on the main surface of the electrically insulating substrate on which the semiconductor chip of the electrically insulating substrate is mounted by wire bonding by photolithography.
  • a laminated semiconductor chip in which a plurality of semiconductor chips are laminated is mounted on the electrically insulating substrate by wire bonding mounting or flip chip mounting and wire bonding mounting.
  • the fabrication of the form in which the laminated semiconductor chip is mounted is performed by wire bonding mounting with two different heights, two types of mounting such as wire bonding mounting and flip chip mounting, and a very complicated manufacturing process.
  • a high-reliability semiconductor device can be manufactured using this technology as it is.
  • the inner vias filled with the conductive paste are roughened, when the semiconductor chip is embedded in a plate in the heating and pressing step, The inner via is not easily displaced against the flow of the thermosetting resin that constitutes the body. Therefore, the inner vias can be formed in a region closer to the semiconductor chip, or the inner vias can be arranged at a narrower pitch.
  • the method of forming gold on the surface of the electrode terminal of the electrically insulating substrate is electrolytic plating, vapor deposition, or spa It is preferable that it consists of any of the cutters.
  • the existing technology can be used as it is to form gold on the electrode terminal surface.
  • the formation of gold on the surface of the electrode terminal by vapor deposition and sputtering does not use chemicals as in the case of plating, so it can be carried out by a simple dry process which eliminates the need for treatment of chemical solution.
  • the degree of roughening of the metal wiring surface not forming gold is preferably in the range of 1 to: LO / zm in terms of the ten-point average roughness Rz specified in JIS B 0601. More preferably, it is in the range of 3 to 6 ⁇ m. If it is the said range, adhesiveness with a resin can be maintained highly.
  • the ten point average height (peak to valley average) specified in JIS B 0601 is, in a roughness curve of any reference length, the five peaks of which the average linear force is higher and Calculated as the difference between the average of the distances between the lower and 5 valleys (in ⁇ m).
  • a gold layer is formed on the surface of the electrode terminal on which the semiconductor chip of the metal wiring of the electrically insulating substrate is mounted.
  • FIG. 101 is a semiconductor chip
  • 102 is an element electrode of the semiconductor chip
  • 103 is a bump
  • 104 is an electrically insulating substrate
  • 105 is a metal wiring
  • 106 is an electrode terminal on which the semiconductor chip is mounted
  • 107 is a roughened portion of the metal wiring
  • 108 is a gold layer of the electrode terminal
  • 109 is a sealing resin.
  • Gold 108 is formed on the surface of the electrode terminal 106 on which the semiconductor chip 101 is flip-chip mounted among the metal wiring 105 of the electrically insulating substrate 104 to a thickness of 0.1 to 3 / ⁇ , and the other
  • the adhesion strength between the sealing resin 109 and the electrically insulating substrate 104 is increased by roughening (107) treatment without forming gold on the surface of the metal wiring 105, and the surface is held by the sealing resin 109.
  • the electrical connection reliability of flip chip mounting of the semiconductor chip 101 is improved.
  • the electrical connection reliability is easily affected by the area of the metal wire 105 in contact with the sealing resin 109, but no gold is formed on the surface of the metal wire other than the electrode terminal 106 By the conversion treatment, the influence of the area of the metal wiring 105 can be reduced, and the reliability of the electrical connection can be improved.
  • a roughened portion and a smooth gold surface portion may be formed by selectively performing gold plating on a commercially available originally roughened copper wiring substrate. / It may be roughened later using a shiny copper foil. As a means to carry out roughing later, surface roughening by chemical etching or the like is used.
  • the degree of roughness of the metal wiring surface which does not form the gold is preferably in the range of 1 to: LO / zm in the ten-point average roughness Rz specified in JIS B 0601. The range is 6 / ⁇ . If it is the said range, adhesiveness with a resin can be maintained highly.
  • FIG. 201 is a semiconductor chip
  • 202 is an element electrode of the semiconductor chip
  • 203 is a gold wire
  • 204 is an electrically insulating substrate
  • 205 is a metal wiring
  • 206 is an electrode terminal on which the semiconductor chip is mounted
  • 207 is a rough metal wiring
  • a portion 208 is a gold layer of the electrode terminal
  • 209 is a mold resin
  • 210 is a die bonding material of the semiconductor chip.
  • the metal wires of the electrically insulating substrate 204 gold is formed on the surface of the electrode terminal 206 on which the semiconductor chip 201 is mounted by wire bonding, and gold is not formed on the surface of the other metal wires 205.
  • roughening (207) treatment the adhesive strength between the mold resin 209 and the electrically insulating substrate 204 is increased, and the electrical connection reliability of the wire bonding mounting of the semiconductor chip 201 held by the mold resin 209 is achieved. Can be improved.
  • the degree of coarseness is preferably the same as in Embodiment 1.
  • Reference numeral 301 is a laminated semiconductor chip
  • 302 is an element electrode of the laminated semiconductor chip
  • 303 is a gold wire
  • 304 is an electrically insulating substrate
  • 305 is a metal wiring
  • 306 is an electrode terminal on which the laminated semiconductor chip is mounted
  • 307 is a rough metal wiring Part 308, gold layer of electrode terminal
  • 309 Lud resin 310 is a die bonding material for semiconductor chips.
  • the metal wiring of the electrically insulating substrate 304 is laminated.
  • the semiconductor chip 301 forms gold on the surface of the electrode terminal 306 on which the wire bonding is mounted, and the surface of the other metal wiring 305 does not form gold but is roughened (307) to obtain mold resin 309 and
  • the bonding strength of the electrically insulating substrate 304 can be increased, and the electrical connection reliability of the wire bonding mounting of the laminated semiconductor chip 301 held by the mold resin 309 can be improved. Further, even if the number of semiconductor chips to be stacked is increased to three, the same effect can be obtained.
  • the degree of roughening is preferably the same as in Embodiment 1.
  • FIG. 401 is a laminated semiconductor chip
  • 402 is an element electrode of the laminated semiconductor chip
  • 403 is a gold wire
  • 404 is a bump
  • 405 is an electrically insulating substrate
  • 406 is a metal wiring
  • 407 is an electrode terminal on which the laminated semiconductor chip is mounted
  • the numeral 408 is a rough portion of metal wiring
  • 409 is a gold layer of the electrode terminal
  • 410 is a mold resin
  • 411 is a sealing resin
  • 412 is a die bonding material of the laminated semiconductor chip.
  • the electrically insulating substrate 405 is the same as in the first to third embodiments.
  • gold is formed on the surface of the electrode terminal 407 to which the laminated semiconductor chip 401 is electrically connected by wire bonding mounting and flip chip mounting, and gold is not formed on the surface of the other metal interconnection 406.
  • roughening (408) treatment the adhesive strength between the mold resin 410 and the sealing resin 411 and the electrically insulating substrate 405 is increased, and the laminated semiconductor held by the mold resin 410 and the sealing resin 411 is obtained.
  • Embodiment 5 Electrical connection reliability of wire bonding mounting and flip chip mounting of the chip 401 can be improved. Further, even if the number of semiconductor chips to be stacked is increased to three, it can be manufactured by flip-chip mounting the lowermost semiconductor chip and wire bonding the upper two semiconductor chips. The same degree of coarseness as in Embodiment 1 is preferable. Embodiment 5
  • FIG. 501 is a semiconductor chip
  • 502 is an element electrode of the semiconductor chip
  • 503 is a bump
  • 504 is an electrically insulating substrate
  • 505 is a metal wiring
  • 506 is an electrode terminal on which the semiconductor chip is mounted
  • 507 is a rough surface portion of metal wiring
  • 508 is a gold layer of the electrode terminal
  • 509 is a sealing resin
  • 510 is an electrically insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin
  • 511 is filled with a conductive resin composition. It is an inner via.
  • the electrical connection reliability of flip chip mounting of the semiconductor chip 501 held by the sealing resin 509 and incorporated in the electrically insulating substrate 510 can be improved.
  • the peeling stress between the sealing resin 509 and the electrically insulating substrate 504 is smaller than the form of the surface mounted semiconductor chip.
  • the semiconductor device of this embodiment can greatly improve the reliability of the electrical connection of the semiconductor chip.
  • the surface of the metal wire electrically connected to the inner via 511 filled with the conductive resin composition is roughened, and in the case of a smooth gold layer, the conductive resin yarn is filled.
  • the semiconductor device of this embodiment can suppress the misalignment.
  • the bonding strength between the inner via and the metal wiring of the electrically insulating substrate is increased, and a highly reliable inner via connection can be realized in the semiconductor device in the form of a module with a built-in component.
  • the degree of coarseness is preferably the same as in Embodiment 1.
  • Embodiment 6 One embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to schematic process sectional views of FIGS. 6A to 6D.
  • 601 is a semiconductor chip
  • 602 is an element electrode of the semiconductor chip
  • 603 is a bump
  • 604 is an electrically insulating substrate
  • 605 is a metal wiring
  • 606 is an electrode terminal on which the semiconductor chip is mounted
  • 607 is a rough metal wiring
  • 608 is a gold layer of the electrode terminal
  • 609 is a sealing resin
  • 610 is a photoresist.
  • an electrically insulating substrate 604 in which the surface of the metal wiring 605 is roughened is prepared (FIG. 6A).
  • a photoresist 610 is formed on the portion excluding the electrode terminal 606 to which the semiconductor chip 601 (FIG. 6D) is flip-chip mounted by a photolithographic method (FIG. 6B).
  • gold 608 is formed on the surface of the electrode terminal 606. The gold layer 608 is formed by gold plating.
  • photoresist 610 is removed (FIG. 6C).
  • the semiconductor chip 601 is flip-chip mounted on the electrically insulating substrate 604 via the sealing resin 609 to fabricate the semiconductor device of this embodiment (FIG. 6D).
  • the existing flip chip mounting technology and the photolithography method can be used as they are, and a highly reliable semiconductor device can be manufactured.
  • Reference numeral 701 is a semiconductor chip
  • 702 is an element electrode of the semiconductor chip
  • 703 is a gold wire
  • 704 is an electrically insulating substrate
  • 705 is a metal wiring
  • 706 is an electrode terminal on which the semiconductor chip is mounted
  • 707 is a rough metal wiring.
  • a ridge portion 708 is a gold layer of an electrode terminal
  • 7 09 is a mold resin
  • 710 is a die bonding material of a semiconductor chip
  • 711 is a photoresist.
  • an electrically insulating substrate 704 in which the surface of the metal wiring 705 is roughened is prepared (FIG. 7A).
  • a photoresist 711 is formed on the portion excluding the electrode terminal 706 where the semiconductor chip is wire-bonded and mounted by a photolithography method (FIG. 7B).
  • gold is formed on the surface of the electrode terminal 706, and the photoresist 710 is removed (FIG. 7C).
  • the element electrode 702 of the semiconductor chip 701 is formed, and the surface is bonded to the insulating substrate 704 through the die bonding material 710, and the gold wire 703 is used to mount the semiconductor chip 701 with the wire bonding. Yes ( Figure 7D).
  • a wire bonding mounting portion including the semiconductor chip 701 and the gold wire 703 is molded with a mold resin 709 to manufacture the semiconductor device of the present embodiment. ( Figure 7E).
  • the existing wire bonding mounting technology and the photolithography method can be used as they are, and a highly reliable semiconductor device can be manufactured.
  • FIGS. 8A-I Another embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to schematic cross-sectional views of FIGS. 8A-I.
  • 801 is a semiconductor chip
  • 802 is an element electrode of the semiconductor chip
  • 803 is a bump
  • 804 is an electrically insulating substrate to which the semiconductor chip is electrically connected
  • 805 is an electrically insulating substrate
  • 806 is an inorganic filler and a thermosetting resin
  • a plate containing a mixture of metals 807 is a through hole
  • 808 is an inner via filled with a conductive paste consisting of a conductive resin composition
  • 809 is a metal wiring
  • 810 is a semiconductor chip mounted.
  • 811 is a roughened portion of the metal wiring
  • 812 is a gold layer of the electrode terminal
  • 813 is a sealing resin
  • 814 is a photoresist.
  • an electrically insulating substrate 804 in which the surface of the metal wire 809 is roughened is prepared (FIG. 8A).
  • a photoresist 814 is formed on the portion excluding the electrode terminal 810 where the semiconductor chip is flip-chip mounted by a photolithographic method (FIG. 8B).
  • a gold layer 812 is formed on the surface of the electrode terminal 810, and the photoresist 814 is removed (FIG. 8C).
  • the semiconductor chip 801 is flip-chip mounted on the electrically insulating substrate 804 via the sealing resin 813 (FIG. 8D).
  • a plate-like body 806 made of a mixture of an inorganic filler and a thermosetting resin is prepared (FIG.
  • FIG. 8E a conductive paste is filled to form through holes 807 to be inner vias 808 (FIG. 8F).
  • the through holes 807 are filled with a conductive paste (FIG. 8G).
  • an electrically insulating substrate 804 on which a semiconductor chip 801 is flip-chip mounted, a plate 806 having an inner via 808 filled with a conductive paste, and the other metal wiring of the plate 806 are used.
  • An electrically insulating substrate 805 to be formed is aligned to be electrically connected by the inner via 808 (FIG. 8H).
  • the semiconductor chip 801 is embedded in the plate-like body 806 and integrally formed.
  • the conductive paste filled in the body 806 and the inner via 808 is cured to fabricate the semiconductor device of the present embodiment (FIG. 81).
  • the semiconductor device As described above, it is possible to use the existing flip chip mounting technology and one photolithography method as it is, and a highly reliable semiconductor. The device can be made.
  • the semiconductor chip is embedded in the plate-like body by the heating and pressing process, the metal wiring electrically connected to the inner via filled with the conductive paste is roughened, and the positional deviation of the inner via is difficult to set.
  • this semiconductor device it is possible to form an inner via filled with a conductive paste made of a conductive resin composition with high positional accuracy, even if miniaturization of metal wiring and narrowing of via pitch of inner via progress. You
  • Example 1 the semiconductor device in the form of the component built-in module of the fifth embodiment described above was manufactured according to the following procedures (i) to (iv).
  • a glass epoxy substrate was prepared as an electrically insulating substrate for mounting a semiconductor chip.
  • the glass epoxy substrate has a thickness of 200 m, electrode terminals for mounting semiconductor chips, via lands for connecting inner vias filled with a conductive paste consisting of a conductive resin composition, and metal wiring for electrically connecting them.
  • the thickness of the metal wiring is 18 m, and the surface roughness is roughened to an average ten-point roughness Rz 5 m.
  • a photoresist was formed on the portion other than the electrode terminal on which the semiconductor chip of the glass epoxy substrate is mounted using the photolithographic method. As a photoresist, AQ-1558 manufactured by Asahi Kasei Corporation was used.
  • a 10 mm square semiconductor chip having a thickness of 0.3 mm was prepared, and gold bumps having a height of 70 ⁇ m were formed in advance as protruding electrodes on 100 element electrodes of the semiconductor chip by a gold wire bonding method.
  • the sealing resin used for flip chip mounting has a thickness of 40 m manufactured by Hitachi Chemical Co., Ltd.
  • Sheet-like sealing resin UF-511 was used. The sheet-like sealing resin was processed to have an area of 100 mm 2 and then attached to the area of the glass epoxy substrate on which the semiconductor chip was mounted. Next, the semiconductor chip was heated and pressurized from the back side where the device electrode was not formed, and flip chip mounting was performed on a glass epoxy substrate.
  • the heating temperature was 200 ° C.
  • the pressure was 3 MP a
  • the heating and pressurizing time was 15 seconds.
  • a mixture of an inorganic filler and a thermosetting resin was prepared, and, if necessary, a small amount of solvent for viscosity adjustment was added to the material constituting the plate, and the mixture was adjusted by mixing using a mixing stirrer.
  • a mixture containing 10% by weight of epoxy resin and 90% by weight of silica filler was adjusted by stirring for 10 minutes.
  • a plate-like body having a thickness of 100 ⁇ m was produced from this mixture by a doctor blade method.
  • four sheets of this plate-like body are laminated and laminated to form a plate-like body having a thickness of 400 m, and then a puncher is used to form a through hole having a diameter of 160 m to be an inner via.
  • the conductive paste was filled by screen printing.
  • the conductive paste used here is 85% by weight of spherical copper particles, 3% by weight of bis-phenol A-type epoxy resin (“Epicoat 828” manufactured by Yuka Shell Epoxy Co., Ltd.) as a resin component, and A triple roll of 9% by weight of an ester-based epoxy resin ("YD-171" manufactured by Tohto Kasei Co., Ltd.) and 3% by weight of an amine adduct hard coat agent ("MY- 24" manufactured by Ajinomoto Co., Ltd.) as a curing agent. It was mixed and adjusted.
  • a glass epoxy substrate on which the semiconductor chip obtained in (ii) is flip-chip mounted, a plate-like body having an inner via filled with the conductive paste obtained in (iii), and the other of the plate-like body The glass epoxy substrate for forming the metal wiring of the main surface is prepared, and the two glass epoxy substrates and the plate are electrically connected by the inner via of the plate so that the semiconductor chip is embedded in the plate. After alignment, they were integrated by heating and pressing to obtain a semiconductor device having the component built-in module of this embodiment. Heating and pressurizing using a heat press, heating temperature 200 ° C, pressure 3MPa, heating and pressurizing time 2 It was time.
  • the epoxy resin contained in the plate-like body was cured after the viscosity once decreased, and the plate-like body and the glass epoxy substrate were adhered.
  • the epoxy resin contained in the inner via filled with the conductive paste was also cured, and the two glass epoxy substrates were electrically connected through the plate.
  • the semiconductor device of this example was manufactured.
  • connection resistance value (hereinafter referred to as bump resistance) between the element electrode of the semiconductor chip of flip chip mounting and the electrode terminal of the glass epoxy substrate.
  • the evaluation criteria were that the bump resistance changed 10% or more before and after the moisture absorption reflow test as a defect, and as a result of evaluating the defect incidence rate for 100 electrical connection points, 60% failure occurred in the conventional semiconductor device. In the semiconductor device of the present invention, no failure occurred.
  • a gold layer is formed on the surface of the electrode terminal on which the semiconductor chip is mounted, and the surface of the other metal wiring to be bonded to the resin is roughened.
  • the electrical connection reliability of the mounting of the semiconductor chip can be improved.
  • a semiconductor device on which a semiconductor chip is mounted can be manufactured with high reliability and electrical connection.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

Disclosed is a semiconductor device wherein a semiconductor chip (501) is mounted on the surface of an electrically insulating substrate (504) having a plurality of metal wires (505) and at least a part of the metal wires (505) are covered with a resin (509). Among the metal wires (505) formed in the electrically insulating substrate (504), at least the surfaces of the metal wires electrically connected with the semiconductor chip (501) are provided with a gold layer (508), and the surfaces of the metal wires in contact with the resin (509) are provided with a roughened portion (507) without being provided with a gold layer. Consequently, the semiconductor device mounted with a semiconductor chip is improved in reliability of electrical connection. Also disclosed is a method for manufacturing such a semiconductor device.

Description

明 細 書  Specification
半導体装置及びその製造方法  Semiconductor device and method of manufacturing the same
技術分野  Technical field
[0001] 本発明は、半導体装置及びその製造方法に関し、とくに電気絶縁性基板の表面に 金層が形成された電極端子に半導体チップが実装された半導体装置及びその製造 方法に関する。  The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device in which a semiconductor chip is mounted on an electrode terminal having a gold layer formed on the surface of an electrically insulating substrate, and a method of manufacturing the same.
背景技術  Background art
[0002] 半導体装置は、情報通信機器、事務用電子機器、家庭用電子機器、測定装置、組 み立てロボット等の産業用電子機器、医療用電子機器などの小型化、薄型化、高性 能化に大きく寄与している。特に情報通信機器の分野での小型化の要求は大きぐ 半導体装置の高密度化、高機能化を目指し、半導体チップを積み重ねた構造の積 層半導体チップを電気絶縁性基板に実装したものや、電気絶縁性基板の表面に電 子部品を実装する従来の 2次元的な実装方法から、電気絶縁性基板に電子部品を 内蔵し、実装面積を大幅に縮小する 3次元的な実装方法の開発が盛んに行なわれ ている。  Semiconductor devices are smaller in size, thinner and higher in performance for information communication devices, office electronic devices, home electronic devices, measuring devices, industrial electronic devices such as assembly robots, medical electronic devices and the like. Greatly contribute to In particular, in the field of information and communication equipment, the demand for miniaturization is large. With the aim of achieving high density and high functionality of semiconductor devices, stacked semiconductor chips with stacked semiconductor chips mounted on an electrically insulating substrate, From the conventional two-dimensional mounting method of mounting electronic components on the surface of an electrically insulating substrate, the development of a three-dimensional mounting method that incorporates electronic components in the electrically insulating substrate and significantly reduces the mounting area It is actively conducted.
[0003] 半導体装置の作製には、半導体チップとそれを搭載する電気絶縁性基板が必要 である。半導体チップを電気絶縁性基板に搭載する実装技術は、大きくは、ワイヤボ ンデイング実装とフリップチップ実装に分けられる。従来力 の技術であるワイヤボン デイング実装は、図 9に示すように、半導体チップ 901の素子電極 902が形成された 面と反対の面をダイボンディング材 910を用いて電気絶縁性基板 904にダイボンディ ングし、半導体チップの素子電極力も電気絶縁性基板の表面に金 908が形成された 電極端子 906の間を金ワイヤ 903で電気接続し、半導体チップ、金ワイヤ部分をモ 一ルド榭脂 909で全面的にモールドする方法である。  [0003] The manufacture of a semiconductor device requires a semiconductor chip and an electrically insulating substrate on which the semiconductor chip is mounted. The mounting technology for mounting a semiconductor chip on an electrically insulating substrate can be roughly divided into wire bonding mounting and flip chip mounting. In wire bonding mounting, which is a conventional technology, as shown in FIG. 9, a surface opposite to the surface on which the element electrode 902 of the semiconductor chip 901 is formed is bonded to the electrically insulating substrate 904 using a die bonding material 910. Also, the element electrode force of the semiconductor chip is gold 908 formed on the surface of the electrically insulating substrate. The electrode terminal 906 is electrically connected with the gold wire 903, and the semiconductor chip and the gold wire part are molded resin 909 overall. Molding method.
[0004] 一方、半導体チップの実装面積を小さくすることができ、最近、主流となって!/ヽるフ リップチップ実装は、半導体チップの素子電極面を電気絶縁性基板の電極端子に向 け、電気接続する方法である。フリップチップ実装は、図 10に示すように、半導体チッ プ 1001の素子電極 1002と電気絶縁性基板 1004の電極端子 1006をバンプ 1003 を介して電気接続する方法で、電気接続部分を封止榭脂 1009が保護している。フリ ップチップ実装は、封止榭脂の種類、電気接続方式によって、 ACF(Anisotropic Co nductive Film)接続、 ACP(Anisotropic Conductive Paste)接続といった半導体チップ の素子電極と電気絶縁性基板の電極端子間に導電性粒子を介在して接続する方法 、 NCF (Non Conductive Film)接続、 NCP(Non Conductive Paste)接続、超音波接合 といった半導体チップの素子電極と電気絶縁性基板の電極端子同士を直接接触さ せて電気接続する方法がある。 On the other hand, the mounting area of the semiconductor chip can be reduced, and has recently become mainstream! Flip chip mounting, in which the element electrode surface of the semiconductor chip faces the electrode terminal of the electrically insulating substrate , Electrical connection method. In flip chip mounting, as shown in FIG. 10, bump 1003 of the device electrode 1002 of the semiconductor chip 1001 and the electrode terminal 1006 of the electrically insulating substrate 1004. Sealing resin 1009 protects the electrical connection portion by means of electrical connection via The flip chip mounting is conducted between the element electrode of the semiconductor chip such as ACF (Anisotropic Conductive Film) connection and ACP (Anisotropic Conductive Paste) connection depending on the type of sealing resin and the electrical connection method, and between the electrode terminals of the electrically insulating substrate. Method of connecting through conductive particles, NCF (Non Conductive Film) connection, NCP (Non Conductive Paste) connection, ultrasonic bonding, etc. The element electrodes of the semiconductor chip and the electrode terminals of the electrically insulating substrate are brought into direct contact with each other. There is a way to make electrical connections.
[0005] 通常、ワイヤボンディング実装、フリップチップ実装ともに、電気絶縁性基板の半導 体チップ実装面の金属配線には、半導体チップが実装される電極端子を含めて一 面に、金メッキ等によって表面に金が形成され、主に表面の清浄性を保つことで、半 導体チップと電気絶縁性基板の電極端子との間を良好に電気接続している。  Usually, in both wire bonding mounting and flip chip mounting, the metal wiring on the semiconductor chip mounting surface of the electrically insulating substrate, including the electrode terminals on which the semiconductor chip is mounted, is surface-plated by gold plating or the like. Gold is formed, and by maintaining the cleanliness of the surface mainly, good electrical connection is made between the semiconductor chip and the electrode terminal of the electrically insulating substrate.
[0006] また、より半導体装置の高密度化、高機能化を実現するために、図 11に示す積層 半導体チップを電気絶縁性基板に実装した半導体装置 (特許文献 1、 2)や、図 12に 示す電子部品を電気絶縁性基板に内蔵し、内蔵した半導体チップと同一の電気絶 縁性基板の層内で、導電性榭脂組成物を充填したインナービアにより電気接続を行 い、 2次元実装に対し、飛躍的に実装密度を向上させた部品内蔵モジュール (特許 文献 3)がある。また、特許文献 4に示すように、半導体チップがフリップチップ実装さ れた半導体装置において、半導体チップと電気絶縁性基板間に補強用の金属配線 を形成する提案もある。  Also, in order to realize higher density and higher functionality of the semiconductor device, a semiconductor device in which the laminated semiconductor chip shown in FIG. 11 is mounted on an electrically insulating substrate (Patent Documents 1 and 2), and FIG. The electronic component shown in FIG. 1 is incorporated in an electrically insulating substrate, and electrical connection is made by an inner via filled with a conductive resin composition in the same layer of the insulating substrate as the incorporated semiconductor chip. There is a component built-in module (Patent Document 3) which dramatically improves the mounting density with respect to mounting. Further, as shown in Patent Document 4, there is also a proposal for forming a reinforcing metal wiring between a semiconductor chip and an electrically insulating substrate in a semiconductor device in which the semiconductor chip is flip-chip mounted.
[0007] しかし、ワイヤボンディング実装及びフリップチップ実装に通常必須となる電気絶縁 性基板の金属配線の表面の金層は、電気接続の信頼性に悪影響を及ぼすことがあ る。金層は、酸化されず清浄であり、またワイヤボンディング実装に用いる金ワイヤや 、フリップチップ実装時の半導体チップのバンプを圧着するのに適度な柔軟性をもち 、良好な半導体チップと電気絶縁性基板の電極端子との間の電気接続を行な 、や すいが、一方で、金層は平滑で榭脂との接着性が悪ぐ例えば銅表面のように表面 の粗ィ匕処理によって簡単に榭脂との接着性を大きくすることが難 、と 、う課題があ つた o  However, the gold layer on the surface of the metal wiring of the electrically insulating substrate, which is usually essential for wire bonding mounting and flip chip mounting, may adversely affect the reliability of the electrical connection. The gold layer is not oxidized and clean, and has adequate flexibility for crimping a gold wire used for wire bonding mounting and a bump of a semiconductor chip at flip chip mounting, and has good electrical insulation with a semiconductor chip Although it is easy to make an electrical connection between the electrode terminals of the substrate, the gold layer is smooth and the adhesion to the resin is poor, for example, simply by roughening the surface as in the case of a copper surface. It is difficult to increase adhesion to resin, and there are problems with o
[0008] この金層の特性に起因する半導体装置の課題として、第 1番目に ACF接続、 ACP 接続、 NCF接続、 NCP接続、超音波接合のような、半導体チップの素子電極に形 成した金バンプと電気絶縁性基板の金属配線の金層を圧接によって電気接続する フリップチップ実装にぉ ヽて、半導体チップの金バンプと電気絶縁性基板の金属配 線の金層との接触、電気接続部分を物理的に保持するために半導体チップと電気 絶縁性基板の間に配置される封止榭脂と電気絶縁性基板との接着性が悪ぐ例えば 吸湿リフロー試験のような半導体パッケージの信頼性試験において熱衝撃が加えら れると、容易に封止榭脂、電気絶縁性基板間が剥離し、剥離した界面が電気接続部 分にも拡大し接続部の電気接続不良を起こす原因になるという課題があった。 First, ACF connection, ACP is the first problem of semiconductor devices caused by the characteristics of this gold layer. In connection, NCF connection, NCP connection, ultrasonic bonding, etc., gold chip formed on the element electrode of the semiconductor chip and gold layer of metal wiring of the electrical insulating substrate are connected electrically by pressure welding. A contact between the gold bump of the semiconductor chip and the gold layer of the metal wiring of the electrically insulating substrate, and a sealing resin disposed between the semiconductor chip and the electrically insulating substrate to physically hold the electrical connection portion. The adhesion between the resin and the electrically insulating substrate is poor. For example, when a thermal shock is applied in a reliability test of a semiconductor package such as a moisture absorption reflow test, the sealing resin and the electrically insulating substrate peel easily. There is a problem that the peeled interface is expanded to the electrical connection portion and causes the electrical connection failure of the connection portion.
[0009] 第 2番目に、金ワイヤを用いて半導体チップの素子電極と電気絶縁性基板の金属 配線の金層を電気接続し、半導体チップと金ワイヤを含めて、モールド榭脂でモー ルドするワイヤボンディング実装にぉ 、て、金ワイヤと金属配線の金層の接触部分、 及び金ワイヤの形状を維持し、保護するためのモールド榭脂が、吸湿リフロー試験に ぉ 、て熱衝撃が加えられると、ワイヤボンディング実装の形態にぉ 、てはモールド榭 脂、電気絶縁性基板間が容易に剥離し、同様にこの剥離した界面が発端となって電 気接続不良を起こす原因になるという課題があった。  Second, the element electrodes of the semiconductor chip and the gold layer of the metal wiring of the electrical insulating substrate are electrically connected using a gold wire, and the semiconductor chip and the gold wire are molded with a mold resin. During wire bonding mounting, a mold resin for maintaining and protecting the contact between the gold wire and the gold layer of the metal wiring and the shape of the gold wire is subjected to a thermal shock in the moisture absorption reflow test. Also, according to the form of wire bonding mounting, there is a problem that the mold resin and the electrically insulating substrate are easily peeled off, and the peeled interface similarly causes an electric connection failure due to the onset. there were.
[0010] 第 3番目に、複数の半導体チップを積層した積層半導体チップを電気絶縁性基板 の電極端子にワイヤボンディング実装、もしくはワイヤボンディング実装とフリップチッ プ実装によって電気接続した形態でも、吸湿リフロー試験において、第 1〜2番目の 例と同様にワイヤボンディング実装のモールド榭脂ゃフリップチップ実装の封止榭脂 の電気絶縁性基板との接着力不足に起因する剥離が生じ、半導体実装の電気接続 不良が発生しやす 、と 、う課題があった。  Third, even in a form in which a laminated semiconductor chip in which a plurality of semiconductor chips are laminated is electrically connected to the electrode terminal of the electrically insulating substrate by wire bonding or wire bonding mounting and flip chip mounting, in the moisture absorption reflow test. As in the first and second examples, peeling occurs due to lack of adhesion between the molded resin of wire bonding mounting and the sealing resin of flip chip mounting and the electrical insulating substrate of the semiconductor, resulting in poor electrical connection of semiconductor mounting. There is a problem that is likely to occur.
[0011] 第 4番目にフリップチップ実装された半導体を内蔵した部品内蔵モジュールの形態 では、通常の半導体チップの実装形態のように表面に露出しておらず、電気絶縁性 基板に内蔵されている。そのため、吸湿リフロー試験において熱衝撃が加えられると 、半導体チップと電気絶縁性基板間に、第 1〜3番目の例以上に、より大きな剥離応 力が加えられ、容易に封止榭脂、電気絶縁性基板間が剥離し、電気接続不良を起こ す原因となるという課題があった。また、電気絶縁性基板の金属配線の表面金層が 平滑で非常に榭脂が滑りやすいため、部品内蔵モジュールに形成された導電性榭 脂組成物からなる導電性ペーストが充填されたインナービアが滑って位置ずれを起 こしゃすいという課題があった。さらに導電性ペースト中の熱硬化性榭脂と金層との 充分な接着性を得ることが難しぐ容易に導電性ペーストが充填されたインナービア の剥離断線が起きやす力つた。 [0011] In the form of a component built-in module incorporating a semiconductor flip-chip mounted fourth, it is not exposed on the surface as in a typical semiconductor chip mounting form, but is built in an electrically insulating substrate . Therefore, when thermal shock is applied in the moisture absorption reflow test, a greater peeling stress is applied between the semiconductor chip and the electrically insulating substrate than the first to third examples, and sealing resin, electricity can be easily obtained. There is a problem in that the insulating substrates peel off and cause an electrical connection failure. In addition, the surface gold layer of the metal wiring of the electrically insulating substrate is smooth and the resin is very slippery. There has been a problem that the inner vias filled with the conductive paste consisting of the fat composition slip and cause displacement. Furthermore, it was difficult to obtain sufficient adhesion between the thermosetting resin in the conductive paste and the gold layer, and it was easy to cause peeling and breakage of the inner via filled with the conductive paste.
[0012] また、上記の課題は、金層の金属配線の面積に依存しやすぐ同一作製条件でも、 電気絶縁性基板の金属配線の設計パターンで信頼性が変わることがあり、確実な信 頼性確保が非常に難しかった。  [0012] Further, the above problems may depend on the area of the metal wiring of the gold layer, and the reliability may change depending on the design pattern of the metal wiring of the electrically insulating substrate even under the same manufacturing conditions immediately. It was very difficult to secure sex.
[0013] また、特許文献 4に示すように、半導体チップがフリップチップ実装された半導体装 置において、半導体チップと電気絶縁性基板間に補強用の金属配線を形成する手 法もあるが、余分な金属配線が必要となるため、金属配線の設計パターンの自由度 が減ると 、う問題を含んで ヽた。 Further, as shown in Patent Document 4, in a semiconductor device in which a semiconductor chip is flip-chip mounted, there is also a method of forming a reinforcing metal wire between the semiconductor chip and the electrically insulating substrate, It is necessary to reduce the degree of freedom in the design pattern of the metal wiring because it requires various metal wiring.
特許文献 1：特開 2000— 349228号公報  Patent Document 1: Japanese Patent Application Laid-Open No. 2000-349228
特許文献 2：特開 2004— 228323号公報  Patent Document 2: Japanese Patent Application Laid-Open No. 2004-228323
特許文献 3：特開平 11― 220262号公報  Patent Document 3: Japanese Patent Application Laid-Open No. 11-220262
特許文献 4：特開 2004— 153210号公報  Patent Document 4: Japanese Patent Application Publication No. 2004-153210
発明の開示  Disclosure of the invention
[0014] 本発明は、前記従来の問題を解決するため、半導体チップが実装された半導体装 置の電気接続の信頼性を向上させた半導体装置及びその製造方法を提供する。  In order to solve the above-mentioned conventional problems, the present invention provides a semiconductor device in which the reliability of electrical connection of a semiconductor device mounted with a semiconductor chip is improved, and a method of manufacturing the same.
[0015] 本発明の半導体装置は、複数の金属配線を備えた電気絶縁性基板の表面に半導 体チップが実装され、少なくとも前記複数の金属配線の一部を榭脂が覆っている半 導体装置であって、前記電気絶縁性基板に形成された複数の金属配線のうち、少な くとも前記半導体チップと電気的に接続される金属配線の表面には金層を形成し、 前記電気絶縁性基板に形成された複数の金属配線のうち、前記樹脂と接触する金 属配線の表面には粗化部を形成することを特徴とする。  In the semiconductor device of the present invention, a semiconductor chip is mounted on the surface of an electrically insulating substrate provided with a plurality of metal wires, and a semiconductor chip covers at least a part of the plurality of metal wires. In the device, a gold layer is formed on the surface of at least a metal wire electrically connected to the semiconductor chip among the plurality of metal wires formed on the electrically insulating substrate, and the electric insulating property Among the plurality of metal wires formed on the substrate, a roughened portion is formed on the surface of the metal wire in contact with the resin.
[0016] 本発明の半導体装置の製造方法は、半導体チップと、前記半導体チップがフリップ チップ実装される電極端子を含む複数の粗化処理された表面の金属配線が形成さ れた主面をもつ電気絶縁性基板とを準備する工程 (a)と、フォトリソグラフィ一法によ つて、前記電気絶縁性基板の前記半導体チップがフリップチップ実装される主面の、 前記電極端子以外の部分に、フォトレジストを形成する工程 (b)と、前記電気絶縁性 基板のフリップチップ実装される主面に無電解金メッキを行なって、前記電極端子表 面に金を形成した後、フォトレジストを除去する工程 (c)と、前記半導体チップの素子 電極面と前記電気絶縁性基板の電極端子面との間に封止榭脂を介して、前記半導 体チップを前記電気絶縁性基板にフリップチップ実装する工程 (d)とを含むことを特 徴とする。 A method of manufacturing a semiconductor device according to the present invention has a semiconductor chip, and a main surface on which a plurality of roughened surface metal wires including an electrode terminal on which the semiconductor chip is flip-chip mounted are formed. A step of preparing an electrically insulating substrate (a), and a main surface of the electrically insulating substrate on which the semiconductor chip is flip chip mounted by a photolithography method; A step (b) of forming a photoresist on the portion other than the electrode terminal and electroless gold plating on the main surface of the electrically insulating substrate on which flip chip mounting is performed, gold was formed on the surface of the electrode terminal. Then, in the step (c) of removing the photoresist, the semiconductor chip is electrically connected through the sealing resin between the element electrode surface of the semiconductor chip and the electrode terminal surface of the electrically insulating substrate. And (f) mounting a flip chip on the insulating substrate.
[0017] 本発明の別の半導体装置の製造方法は、半導体チップと、前記半導体チップがヮ ィャボンディング実装される電極端子を含む複数の粗化処理された表面の金属配線 が形成された主面をもつ電気絶縁性基板とを準備する工程 (a)と、フォトリソグラフィ 一法によって、前記電気絶縁性基板の前記半導体チップ力 Sワイヤボンディング実装 される主面の、前記電極端子以外の部分に、フォトレジストを形成する工程 (b)と、前 記電気絶縁性基板のワイヤボンディング実装される主面に無電解金メッキを行なって 、前記電極端子表面に金を形成した後、フォトレジストを除去する工程 (c)と、前記半 導体チップの素子電極が形成されている面の反対の主面を前記電気絶縁性基板に 接合する工程 (d)と、前記半導体チップを前記電気絶縁性基板にワイヤボンディング 実装する工程 (e)と、前記半導体チップと前記ワイヤボンディング実装部分を榭脂モ 一ルドする工程 (f)とを含むことを特徴とする。  According to another method of manufacturing a semiconductor device of the present invention, a main surface on which a plurality of roughened surface metal wires including a semiconductor chip and electrode terminals on which the semiconductor chip is mounted by die bonding is formed. (A) preparing the electrically insulating substrate and the photolithographically, the semiconductor chip force of the electrically insulating substrate S wire bonding of the main surface of the main surface other than the electrode terminal Step (b) of forming a resist, and electroless gold plating is performed on the main surface of the electrically insulating substrate on which wire bonding is mounted to form gold on the surface of the electrode terminal, and then the step of removing the photoresist ( c) bonding the principal surface opposite to the surface on which the element electrode of the semiconductor chip is formed to the electrically insulating substrate (d), and using the semiconductor chip as the electrically insulating substrate The ear bonding mounting to step (e), characterized in that it comprises a said semiconductor chip and the wire bonding mounting portions 榭脂 mode one field to step (f).
[0018] 本発明のさらに別の半導体装置の製造方法は、半導体チップと、前記半導体チッ プがフリップチップ実装される電極端子を含む複数の粗ィヒ処理された表面の金属配 線が形成された主面をもつ第 1の電気絶縁性基板と、複数の金属配線が形成された 主面をもつ第 2の電気絶縁性基板と、無機フィラーと熱硬化性榭脂とを含む混合物 力もなる第 3の電気絶縁性基板である板状体を準備する工程 (a)と、フォトリソグラフィ 一法によって、前記第 1の電気絶縁性基板の前記半導体チップがフリップチップ実 装される主面の、前記電極端子以外の部分に、フォトレジストを形成する工程 (b)と、 前記第 1の電気絶縁性基板のフリップチップ実装される主面に無電解金メッキを行な つて、前記電極端子表面に金を形成した後、フォトレジストを除去する工程 (c)と、前 記半導体チップの素子電極面と前記電気絶縁性基板の電極端子面との間に封止榭 脂を介して、前記半導体チップを前記電気絶縁性基板にフリップチップ実装するェ 程 (d)と、前記板状体に貫通孔を形成し、前記貫通孔に導電性榭脂組成物からなる 導電性ペーストを充填する工程 (e)と、前記第 1と第 2の電気絶縁性基板及び前記板 状体を、前記板状体の一方の主面に前記第 1の電気絶縁性基板の前記半導体チッ プがフリップチップ実装された主面が向くように、もう一方の主面に前記第 2の電気絶 縁性基板の金属配線が形成された主面が向くように位置あわせし、積層する工程 (f) と、加熱加圧して、前記第 1と第 2の電気絶縁性基板を前記板状体に接着し、前記半 導体チップを前記板状体に埋設して一体化し、前記板状体及び前記導電性榭脂組 成物からなる導電性ペーストを硬化させる工程 (g)とを含むことを特徴とする。 According to still another method of manufacturing a semiconductor device of the present invention, a metal wire is formed on a plurality of roughened surfaces including a semiconductor chip and an electrode terminal on which the semiconductor chip is flip-chip mounted. A first electrically insulating substrate having a major surface, a second electrically insulating substrate having a major surface on which a plurality of metal wires are formed, and a mixture comprising an inorganic filler and a thermosetting resin Step (a) of preparing a plate-like body which is the electrically insulating substrate of 3, and the main surface of the first electrically insulating substrate on which the semiconductor chip of the first electrically insulating substrate is mounted by the photolithographic method. Step (b) of forming a photoresist on a portion other than the electrode terminal, electroless gold plating is performed on the main surface of the first electrically insulating substrate flip-chip mounted, and gold is applied to the surface of the electrode terminal. After forming, remove the photoresist And (f) mounting the semiconductor chip on the electrically insulating substrate via the sealing resin between the element electrode surface of the semiconductor chip and the electrode terminal surface of the electrically insulating substrate. Do (D), forming a through hole in the plate-like body, and filling the through hole with a conductive paste comprising a conductive resin composition ( e ), the first and second electrical insulation Conductive substrate and the plate-like body, and the other main surface of the first electrically insulating substrate is flip-chip mounted on one main surface of the plate so that the main surface of the semiconductor chip of the first electrically insulating substrate faces the other main surface. Aligning and laminating so that the main surface of the second electrically insulating substrate on which the metal wiring is formed is oriented, and laminating (f), the first and second electrically insulating Bonding the substrate to the plate, embedding the semiconductor chip in the plate so as to integrate them, and curing the conductive paste comprising the plate and the conductive resin composition (g And is included.
図面の簡単な説明  Brief description of the drawings
[0019] [図 1]図 1は本発明の実施形態 1における半導体装置の断面図である。 [FIG. 1] FIG. 1 is a cross-sectional view of a semiconductor device in Embodiment 1 of the present invention.
[図 2]図 2は本発明の実施形態 2における半導体装置の断面図である。  FIG. 2 is a cross-sectional view of a semiconductor device in Embodiment 2 of the present invention.
[図 3]図 3は本発明の実施形態 3における半導体装置の断面図である。  [FIG. 3] FIG. 3 is a cross-sectional view of a semiconductor device in Embodiment 3 of the present invention.
[図 4]図 4は本発明の実施形態 4における半導体装置の断面図である。  [FIG. 4] FIG. 4 is a cross-sectional view of a semiconductor device in Embodiment 4 of the present invention.
[図 5]図 5は本発明の実施形態 5及び実施例 1における半導体装置の断面図である。  FIG. 5 is a cross-sectional view of the semiconductor device in Embodiment 5 and Example 1 of the present invention.
[図 6]図 6A— Dは本発明の実施形態 6における半導体装置の製造方法を示す工程 断面図である。  6A to 6D are sectional views showing steps of a method of manufacturing a semiconductor device in a sixth embodiment of the present invention.
[図 7]図 7A— Eは本発明の実施形態 7における半導体装置の製造方法を示す工程 断面図である。  [FIG. 7] FIGS. 7A to 7E are process sectional views showing a method of manufacturing a semiconductor device according to Embodiment 7 of the present invention.
[図 8]図 8A— Iは本発明の実施形態 8における半導体装置の製造方法を示す工程断 面図である。  [FIG. 8] FIGS. 8A to 8I are process sectional views showing a method of manufacturing a semiconductor device in Embodiment 8 of the present invention.
[図 9]図 9は従来の半導体装置の一例を示す断面図である。  [FIG. 9] FIG. 9 is a cross-sectional view showing an example of a conventional semiconductor device.
[図 10]図 10は従来の半導体装置の別の一例を示す断面図である。  [FIG. 10] FIG. 10 is a cross sectional view showing another example of the conventional semiconductor device.
[図 11]図 11は従来の半導体装置の別の一例を示す断面図である。  [FIG. 11] FIG. 11 is a cross-sectional view showing another example of the conventional semiconductor device.
[図 12]図 12は従来の半導体装置の別の一例を示す断面図である。  [FIG. 12] FIG. 12 is a cross-sectional view showing another example of a conventional semiconductor device.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0020] 本発明の半導体装置は、半導体チップが実装された電気絶縁性基板の金属配線 において、半導体チップが実装された電極端子の表面に金層を形成し、その他の金 属配線には金層を形成せず表面を粗化することで、フリップチップ実装における封止 榭脂と電気絶縁性基板間、ワイヤボンディング実装におけるモールド榭脂と電気絶 縁性基板間の接着強度を大きくしたものである。接着強度を大きくすることで、吸湿リ フロー試験等の信頼性試験における電気接続の信頼性を向上させることができる。 また、フリップチップ実装における封止榭脂部分、ワイヤボンディング実装におけるモ 一ルド榭脂部分の電気絶縁性基板の金属配線の設計パターンが、電気接続信頼性 へ与える影響を低減することができる。 In the semiconductor device of the present invention, in the metal wiring of the electrically insulating substrate on which the semiconductor chip is mounted, a gold layer is formed on the surface of the electrode terminal on which the semiconductor chip is mounted. Sealing in flip chip mounting by roughening the surface without forming a layer The bonding strength between the resin and the electrically insulating substrate, and between the mold resin and the electrically insulating substrate in wire bonding mounting is increased. By increasing the adhesive strength, the reliability of the electrical connection in the reliability test such as the moisture absorption reflow test can be improved. In addition, it is possible to reduce the influence of the design pattern of the metal wiring of the electrically insulating substrate of the sealing resin portion in flip chip mounting and the molded resin portion in wire bonding mounting on the electrical connection reliability.
[0021] また、複数の半導体チップを積層した積層半導体チップを電気絶縁性基板にワイ ャボンディング実装、もしくはワイヤボンディング実装とフリップチップ実装によって電 気接続した形態にぉ 、て、ワイヤボンディング実装のモールド榭脂と電気絶縁性基 板間ゃフリップチップ実装の封止榭脂と電気絶縁性基板間の接着強度を大きくし、 吸湿リフロー試験等の信頼性試験における信頼性を向上させることができる。積層半 導体チップの形態では、一枚の半導体チップに比べ、榭脂との接着面数や面積が 多くなり、また形状的にコーナー部や半導体チップ間の積層界面等に局所的により 大きな応力がかかりやすい。そのため、積層半導体チップの実装信頼性の確保は、 通常の一枚の半導体チップの実装信頼性の確保以上に難しいものであった力 電 気絶縁性基板の実装面の接着強度を大きくすることで、積層半導体チップの実装信 頼性を改善することができる。  In addition, the laminated semiconductor chip in which a plurality of semiconductor chips are laminated is electrically connected to the electrically insulating substrate by wire bonding or wire bonding mounting and flip chip mounting, so that the mold for wire bonding mounting is used. The adhesive strength between the resin and the electrically insulating substrate and the sealing resin of the flip chip mounting can be increased, and the reliability in the reliability test such as the moisture absorption reflow test can be improved. In the form of laminated semiconductor chips, the number of bonded surfaces with resin and the area increase as compared with a single semiconductor chip, and locally larger stresses are generated at the corners and laminated interfaces between semiconductor chips in shape. It is easy to take. Therefore, securing the mounting reliability of the laminated semiconductor chip can be achieved by increasing the adhesive strength of the mounting surface of the force-electrically insulating substrate, which was more difficult than securing the mounting reliability of a single semiconductor chip. The mounting reliability of the laminated semiconductor chip can be improved.
[0022] また、フリップチップ実装された半導体を内蔵した部品内蔵モジュールの形態にお いて、フリップチップ実装の封止榭脂と電気絶縁性基板間の接着強度を向上させ、 表面実装された半導体チップより封止榭脂と電気絶縁性基板間の剥離応力が大きく 、信頼性の高!、電気接続の実現が難 、部品内蔵モジュールの形態の半導体装置 の吸湿リフロー試験等の信頼性試験における電気接続信頼性を向上させることがで きる。また、部品内蔵モジュールに形成された導電性榭脂組成物が充填されたイン ナービアの電気接続される金属配線の表面が粗化処理されて 、るので、平滑で榭 脂が滑りやす 、金層で発生しやす 、インナービアの位置ずれを抑制することができ、 またインナービアと金属配線との接着強度が大きくなるため、各種の信頼性試験にお いて、剥離の発生がなぐ高信頼な電気接続を保つことができる。  Also, in the form of a component built-in module incorporating a flip chip mounted semiconductor, the adhesive strength between the flip chip mounting sealing resin and the electrically insulating substrate is improved to provide a surface mounted semiconductor chip. The peeling stress between the sealing resin and the electrically insulating substrate is large, the reliability is high, the realization of the electrical connection is difficult, and the electrical connection in the reliability test such as the moisture absorption reflow test of the semiconductor device in the form of a module with a built-in component. Reliability can be improved. In addition, since the surface of the metal wiring electrically connected to the inner via filled with the conductive resin composition formed in the component built-in module is roughened, the resin is smooth and slippery, and the gold layer is formed. It is possible to suppress the positional deviation of the inner vias and to increase the adhesive strength between the inner vias and the metal wiring, so that it is possible to prevent the occurrence of peeling in various reliability tests. You can stay connected.
[0023] 半導体チップが実装される電気絶縁性基板の電極端子を含む一部の金属配線の 表面に金層が形成されており、他の金属配線の表面に金層が形成されておらず、粗 化処理されて!、る形態が好ま 、。金属配線の表面の選択的な金層の形成を行なう ことができる。半導体チップの実装のために金層の形成が必須の電極端子を除いて 、金層の形成を行なう金属配線表面の選択は、簡単な設計パターンで金層形成のフ オトレジストを形成できるように、また、半導体チップの実装の電気接続信頼性が悪化 しない面積であるよう、選択するのがよい。 [0023] A portion of metal wiring including an electrode terminal of an electrically insulating substrate on which a semiconductor chip is mounted A gold layer is formed on the surface, and no gold layer is formed on the surface of the other metal wiring, and roughened! Is preferred. Selective gold layer formation can be performed on the surface of metal wiring. With the exception of electrode terminals that require the formation of a gold layer for mounting a semiconductor chip, the selection of the metal wiring surface on which the gold layer is to be formed allows the formation of a gold layer formation photoresist with a simple design pattern. In addition, it is preferable to select such an area that the electrical connection reliability of the mounting of the semiconductor chip does not deteriorate.
[0024] 電極端子表面の金層の形成方法は、無電解メツキ、電解メツキ、蒸着、又はスパッ タの 、ずれかが好まし 、。既存の金層の形成技術をそのまま用いて本発明の半導体 装置を作製することができる。特に、蒸着、スパッタはドライプロセスで形成することが でき、簡易な手法としてより好ましい。  As a method of forming a gold layer on the surface of the electrode terminal, electroless plating, electrolytic plating, vapor deposition, or sputtering is preferred. The semiconductor device of the present invention can be manufactured using the existing gold layer forming technology as it is. In particular, vapor deposition and sputtering can be formed by a dry process, which is more preferable as a simple method.
[0025] フリップチップ実装は、 ACF(Anisotropic Conductive Film),ACP(Anisotropic Condu ctive Paste),NCF(Non Conductive Film),NCP(Non Conductive Paste)のいずれかを 用いた熱圧着工法、又は半導体チップの素子電極に形成された金バンプと電気絶 縁性基板の電極端子表面に形成された金の超音波接合によって行なわれることが 好ましい。既存のフリップチップ実装技術をそのまま用いることができる。また、上記 の既存のフリップチップ実装技術のみに限定されるのでなぐ電気絶縁性基板の半 導体チップを実装する電極端子に金配線を用い、封止榭脂、モールド榭脂等によつ て実装部を保護する形態の実装技術には、同様の効果を得ることができる。  The flip chip mounting may be performed by a thermocompression bonding method using any of an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), a non conductive film (NCF), and a non conductive paste (NCP), or a semiconductor chip It is preferable that ultrasonic bonding be performed between a gold bump formed on the element electrode and a gold formed on the surface of the electrode terminal of the electrically insulating substrate. The existing flip chip mounting technology can be used as it is. In addition, since it is limited only to the above existing flip chip mounting technology, gold wiring is used for the electrode terminal for mounting the semiconductor chip of the electrically insulating substrate to be mounted, and mounting is performed using sealing resin, molding resin, etc. A similar effect can be obtained in the mounting technology in the form of protecting the part.
[0026] 配線は粗ィ匕した銅とすることが好ま Uヽ。銅配線基板は、安価に作製することができ 、多種多様な市販品を入手しやすい。また、表面の粗ィ匕処理を行ないやすい。銅以 外にも銅を含む合金であっても良い。粗ィ匕した銅箔は市販品を用いてもよいし、平滑 な銅箔をエッチング液によるエッチング処理、プラズマ処理、研磨剤による研磨処理 、電解などの処理により形成できる。  [0026] The wiring is preferably roughened copper U ヽ. Copper wiring substrates can be manufactured inexpensively, and a wide variety of commercial products are easily available. In addition, it is easy to carry out surface roughening treatment. Besides copper, it may be an alloy containing copper. The roughened copper foil may be a commercially available product, or a smooth copper foil can be formed by etching treatment with an etching solution, plasma treatment, polishing treatment with an abrasive, electrolysis, or the like.
[0027] 前記第 3の電気絶縁性基板は、無機フィラーと熱硬化性榭脂とを含む混合物から なることが好ましい。また第 1〜3に含まれる熱可塑性榭脂は同一の材料としてもよい 。これにより、電気絶縁性基板 1、 3間及び 2、 3間の榭脂同士の接着強度を大きくす ることで、それぞれの電気絶縁性基板の接着面の接着強度を大きくし、吸湿リフロー 試験等の信頼性試験において、電気接続の信頼性を向上させることができる。また、 異なる材料の異種積層の形態力もなる半導体装置に比べ、応力が小さくなることで、 電気接続の信頼性が向上する効果がある。 The third electrically insulating substrate is preferably made of a mixture containing an inorganic filler and a thermosetting resin. The thermoplastic resins contained in the first to third may be made of the same material. Thus, by increasing the adhesive strength between the electrically insulating substrates 1 and 3 and between the resins 2 and 3, the adhesive strength of the adhesive surface of each electrically insulating substrate is increased, and the moisture absorption reflow test, etc. In the reliability test of the invention, the reliability of the electrical connection can be improved. Also, Compared to a semiconductor device that also has the form force of different materials stacked together, the smaller stress has the effect of improving the reliability of the electrical connection.
[0028] 無機フイラ一は 70重量％〜95重量％含まれることが好ましい。 95重量％以上であ ると、粉体量に対し、液体量が少なすぎ、シートィ匕することが難しい。また、 70重量％ 以下であると、無機フィラーを混合したことによる放熱性の向上等の効果が少なくなる 。加熱加圧して半導体チップを電気絶縁性基板に内蔵する時に、半導体チップに損 傷を与えな 、粘度であれば、無機フィラーの配合率は大き 、方がより好ま U、。  [0028] The inorganic filler is preferably contained in an amount of 70% by weight to 95% by weight. If it is 95% by weight or more, the amount of liquid is too small relative to the amount of powder, making sheeting difficult. Further, when the content is 70% by weight or less, the effect of improving the heat dissipation and the like by mixing the inorganic filler is reduced. When the semiconductor chip is incorporated in the electrically insulating substrate by heat and pressure, the semiconductor chip is not damaged. If it is a viscosity, the blending ratio of the inorganic filler is large, and it is more preferable U ,.
[0029] 無機フイラ一は、 Al O、 MgO、 BN、 A1N及び SiOから選ばれる少なくとも一つの  [0029] The inorganic filler is at least one selected from Al 2 O, MgO, BN, A 1 N and SiO
2 3 2  2 3 2
無機フィラーであることが好ましい。これらの無機フィラーを用いることで、放熱性に優 れた半導体装置となる。また、無機フイラ一として、 SiOを用いた場合、誘電率を小さ  It is preferable that it is an inorganic filler. By using these inorganic fillers, a semiconductor device with excellent heat dissipation can be obtained. Also, when using SiO as the inorganic filler, the dielectric constant is small.
2  2
くすることがでさる。  It can be done.
[0030] 熱硬化性榭脂は、エポキシ榭脂、フエノール榭脂、及びシァネート榭脂から選ばれ る少なくとも一つの熱硬化性榭脂であることが好ましい。これらの榭脂は多種多様な 種類が市販されており、これらの榭脂を用いることで耐熱性や電気絶縁性に優れた 半導体装置となる。  [0030] The thermosetting resin is preferably at least one thermosetting resin selected from epoxy resin, phenol resin and cyanate resin. A wide variety of these resins are commercially available, and the use of these resins results in semiconductor devices having excellent heat resistance and electrical insulation.
[0031] 導電性榭脂組成物は金、銀、銅、及びニッケルカゝら選ばれる少なくとも一つの金属 を含む金属粒子を導電性成分として含み、エポキシ榭脂を榭脂成分として含むこと が好ましい。上記金属は電気抵抗が低ぐまた、エポキシ榭脂は、耐熱性や電気絶 縁性に優れているからである。特に、銅粉をコア材に表面を銀でコートした金属粒子 は、機械的強度が強く安価である銅粉と酸ィ匕しにくい銀粉の両方の特性を併せもち、 好適である。  The conductive resin composition preferably contains metal particles containing at least one metal selected from gold, silver, copper, and nickel as a conductive component, and preferably contains epoxy resin as a resin component. The above-mentioned metals have low electric resistance, and epoxy resins are excellent in heat resistance and electric insulation. In particular, metal particles in which the surface is coated with silver on the core material with copper powder are preferable because they have the properties of both copper powder which is strong in mechanical strength and is inexpensive, and silver powder which is difficult to be oxidized.
[0032] 本発明の製造方法においては、半導体チップと、前記半導体チップがフリップチッ プ実装される電極端子を含む複数の表面に粗化処理が行なわれた金属配線が形成 された主面をもつ電気絶縁性基板とを準備する工程 (a)と、フォトリソグラフィ一法に よって、前記電気絶縁性基板の前記半導体チップがフリップチップ実装される主面 の、前記電極端子以外の部分に、フォトレジストを形成する工程 (b)と、前記電気絶 縁性基板のフリップチップ実装される主面に無電解金メッキを行なって前記電極端 子表面に金を形成した後、フォトレジストを除去する工程 (c)と、前記半導体チップの 素子電極面と前記電気絶縁性基板の電極端子面との間に封止榭脂を介して、前記 半導体チップを前記電気絶縁性基板にフリップチップ実装する工程 (d)とを含むの が好まし!/、。既存のフリップチップ実装技術とフォトリソグラフィ一法をそのまま使用す ることができ、本発明の信頼性の高い半導体装置を作製することができる。 In the manufacturing method of the present invention, there is provided a semiconductor chip and an electric main surface having a metal wiring in which a roughening treatment is performed on a plurality of surfaces including an electrode terminal on which the semiconductor chip is flip-chip mounted. Step of preparing an insulating substrate (a) and a photolithographic method, a portion of the main surface of the electrically insulating substrate on which the semiconductor chip is flip chip mounted, other than the electrode terminal, a photoresist. Step of forming (b), and after performing electroless gold plating on the main surface of the insulating substrate flip-chip mounted to form gold on the surface of the electrode terminal, and then removing the photoresist (c) And the semiconductor chip And (f) mounting the semiconductor chip on the electrically insulating substrate by flip chip mounting between the element electrode surface and the electrode terminal surface of the electrically insulating substrate via a sealing resin. ! /. The existing flip chip mounting technology and the photolithography method can be used as they are, and the highly reliable semiconductor device of the present invention can be manufactured.
[0033] また、半導体チップと、前記半導体チップがワイヤボンディング実装される電極端子 を含む複数の表面に粗化処理が行なわれた金属配線が形成された主面をもつ電気 絶縁性基板とを準備する工程 (a)と、フォトリソグラフィ一法によって、前記電気絶縁 性基板の前記半導体チップがワイヤボンディング実装される主面の、前記電極端子 以外の部分に、フォトレジストを形成する工程 (b)と、前記電気絶縁性基板のワイヤボ ンデイング実装される主面に無電解金メッキを行なって前記電極端子表面に金を形 成した後、フォトレジストを除去する工程 (c)と、前記半導体チップの素子電極が形成 されている面の反対の主面を前記電気絶縁性基板に接合する工程 (d)と、前記半導 体チップを前記電気絶縁性基板にワイヤボンディング実装する工程 (e)と、前記半導 体チップと前記ワイヤボンディング実装部分を榭脂モールドする工程 (f)とを含むの が好まし!/、。既存のワイヤボンディング実装技術とフォトリソグラフィ一法をそのまま使 用することができ、本発明の信頼性の高い半導体装置を作製することができる。  In addition, a semiconductor chip and an electrically insulating substrate having a main surface on which a metal wiring having a roughening treatment formed on a plurality of surfaces including an electrode terminal on which the semiconductor chip is mounted by wire bonding are prepared. And (b) forming a photoresist on a portion other than the electrode terminal on the main surface of the electrically insulating substrate on which the semiconductor chip of the electrically insulating substrate is mounted by wire bonding by photolithography. And e) forming gold on the surface of the electrode terminal by performing electroless gold plating on the main surface of the electrically insulating substrate on which the wire bonding is to be mounted, and then removing a photoresist (c); Bonding the principal surface opposite to the surface on which the semiconductor chip is formed to the electrically insulating substrate (d), and wire bonding mounting the semiconductor chip on the electrically insulating substrate It is preferable to include approximately (e), and a step (f) of resin-molding the semiconductor chip and the wire bonding mounting portion! //. The existing wire bonding mounting technique and photolithography can be used as they are, and the highly reliable semiconductor device of the present invention can be manufactured.
[0034] また、複数の半導体チップが積層された積層半導体チップをワイヤボンディング実 装、もしくはフリップチップ実装及びワイヤボンディング実装によって前記電気絶縁性 基板に実装したものである。積層半導体チップを実装した形態の作製は、 2段の高さ の異なるワイヤボンディング実装を行なったり、ワイヤボンディング実装とフリップチッ プ実装の 2種の実装を行なったり、非常に複雑な作製工程となり、既存の技術をその まま用いて信頼性の高 、半導体装置を作製することができる。  In addition, a laminated semiconductor chip in which a plurality of semiconductor chips are laminated is mounted on the electrically insulating substrate by wire bonding mounting or flip chip mounting and wire bonding mounting. The fabrication of the form in which the laminated semiconductor chip is mounted is performed by wire bonding mounting with two different heights, two types of mounting such as wire bonding mounting and flip chip mounting, and a very complicated manufacturing process. A high-reliability semiconductor device can be manufactured using this technology as it is.
[0035] また、導電性ペーストが充填されたインナービアと電気接続される金属配線が粗ィ匕 されているため、加熱加圧工程において、半導体チップを板状体に埋設する際に、 板状体を構成する熱硬化性榭脂の流動に抗してインナービアの位置ずれが起きにく い。このため、半導体チップにより近い領域にインナービアを形成したり、より狭ピッチ にインナービアを配置したりすることができる。  In addition, since the metal wires electrically connected to the inner vias filled with the conductive paste are roughened, when the semiconductor chip is embedded in a plate in the heating and pressing step, The inner via is not easily displaced against the flow of the thermosetting resin that constitutes the body. Therefore, the inner vias can be formed in a region closer to the semiconductor chip, or the inner vias can be arranged at a narrower pitch.
[0036] 電気絶縁性基板の電極端子表面の金の形成方法は、電解メツキ、蒸着、又はスパ ッタのいずれかからなることが好ましい。既存の技術をそのまま使用して、電極端子 表面への金の形成を行なうことができる。また、蒸着、スパッタによる電極端子表面へ の金の形成では、メツキのように薬品を使わないため、薬液の処理の必要がなぐ簡 単なドライプロセスで行なうことができる。 The method of forming gold on the surface of the electrode terminal of the electrically insulating substrate is electrolytic plating, vapor deposition, or spa It is preferable that it consists of any of the cutters. The existing technology can be used as it is to form gold on the electrode terminal surface. Further, the formation of gold on the surface of the electrode terminal by vapor deposition and sputtering does not use chemicals as in the case of plating, so it can be carried out by a simple dry process which eliminates the need for treatment of chemical solution.
[0037] 本発明において、前記金を形成しない金属配線表面の粗ィ匕の程度は、 JIS B 06 01に規定の十点平均粗さ Rzにおいて、 1〜： LO /z mの範囲が好ましぐより好ましくは 3〜6 μ mの範囲である。前記範囲であれば、榭脂との接着性を高く維持できる。ここ で JIS B 0601に規定の十点平均粗さ (ten point average height, peak to valley ave rage)は、任意の基準長さの粗さ曲線において、その平均線力 高いほうの 5個の山 及び低 、ほうの 5個の谷間での距離を平均した値の差で算出する（単位は μ m)。  In the present invention, the degree of roughening of the metal wiring surface not forming gold is preferably in the range of 1 to: LO / zm in terms of the ten-point average roughness Rz specified in JIS B 0601. More preferably, it is in the range of 3 to 6 μm. If it is the said range, adhesiveness with a resin can be maintained highly. Here, the ten point average height (peak to valley average) specified in JIS B 0601 is, in a roughness curve of any reference length, the five peaks of which the average linear force is higher and Calculated as the difference between the average of the distances between the lower and 5 valleys (in μm).
[0038] 本発明によれば、半導体チップが実装された半導体装置にお!ヽて、電気絶縁性基 板の金属配線の半導体チップが実装される電極端子の表面に金層が形成され、そ の他の金属配線の表面を粗ィヒすることにより、電気絶縁性基板の半導体チップ実装 面とフリップチップ実装の封止榭脂、ワイヤボンディング実装のモールド榭脂との接 着強度が大きくなり、半導体チップ実装の電気接続の信頼性を向上することができる  According to the present invention, in the semiconductor device on which the semiconductor chip is mounted, a gold layer is formed on the surface of the electrode terminal on which the semiconductor chip of the metal wiring of the electrically insulating substrate is mounted. By roughening the surface of the other metal wiring, the adhesion strength between the semiconductor chip mounting surface of the electrically insulating substrate and the sealing resin for flip chip mounting and the mold resin for wire bonding mounting increases. It is possible to improve the reliability of electrical connection on semiconductor chip mounting
[0039] 以下、本発明の実施の形態について、図 1乃至図 8を用いて説明する。なお、本発 明は下記の実施形態に限定されるものではない。 Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 8. The present invention is not limited to the following embodiments.
[0040] (実施形態 1)  Embodiment 1
本発明の半導体装置の一実施形態を、図 1の模式的な断面図を参照して説明する 。 101は半導体チップ、 102は半導体チップの素子電極、 103はバンプ、 104は電 気絶縁性基板、 105は金属配線、 106は半導体チップが実装される電極端子、 107 は金属配線の粗化部分、 108は電極端子の金層、 109は封止榭脂である。  One embodiment of the semiconductor device of the present invention will be described with reference to the schematic cross-sectional view of FIG. 101 is a semiconductor chip, 102 is an element electrode of the semiconductor chip, 103 is a bump, 104 is an electrically insulating substrate, 105 is a metal wiring, 106 is an electrode terminal on which the semiconductor chip is mounted, 107 is a roughened portion of the metal wiring, 108 is a gold layer of the electrode terminal, and 109 is a sealing resin.
[0041] 電気絶縁性基板 104の金属配線 105の中で、半導体チップ 101がフリップチップ 実装される電極端子 106の表面に金 108を 0. 01〜3 /ζ πιの厚みに形成し、その他 の金属配線 105の表面には金を形成せずに粗化（107)処理することにより、封止榭 脂 109と電気絶縁性基板 104の接着強度が大きくし、封止榭脂 109によって保持さ れている半導体チップ 101のフリップチップ実装の電気接続信頼性を向上させる。実 際の半導体装置では、封止榭脂 109に接触している金属配線 105の面積によって、 電気接続信頼性が影響を受けやすいが、電極端子 106以外の金属配線の表面に 金を形成せず粗化処理することで、金属配線 105の面積の影響を低減し、電気接続 の信頼性を向上させることができる。 Gold 108 is formed on the surface of the electrode terminal 106 on which the semiconductor chip 101 is flip-chip mounted among the metal wiring 105 of the electrically insulating substrate 104 to a thickness of 0.1 to 3 / ζπι, and the other The adhesion strength between the sealing resin 109 and the electrically insulating substrate 104 is increased by roughening (107) treatment without forming gold on the surface of the metal wiring 105, and the surface is held by the sealing resin 109. The electrical connection reliability of flip chip mounting of the semiconductor chip 101 is improved. Real In the case of the semiconductor device, the electrical connection reliability is easily affected by the area of the metal wire 105 in contact with the sealing resin 109, but no gold is formed on the surface of the metal wire other than the electrode terminal 106 By the conversion treatment, the influence of the area of the metal wiring 105 can be reduced, and the reliability of the electrical connection can be improved.
[0042] 本発明の実施形態において、市販されているもともと粗化された銅配線基板に選 択的に金メッキを施すことで粗化部と平滑な金表面部を形成してもよ！/ヽし、光沢銅箔 を用いて後から粗ィ匕してもよい。後から粗ィ匕する手段として、化学的なエッチングによ る表面の微粗ィ匕処理等が用いられる。  In the embodiment of the present invention, a roughened portion and a smooth gold surface portion may be formed by selectively performing gold plating on a commercially available originally roughened copper wiring substrate. / It may be roughened later using a shiny copper foil. As a means to carry out roughing later, surface roughening by chemical etching or the like is used.
[0043] 前記金を形成しない金属配線表面の粗ィ匕の程度は、 JIS B 0601に規定の十点 平均粗さ Rzにおいて、 1〜： LO /z mの範囲が好ましぐより好ましくは 3〜6 /ζ πιの範囲 である。前記範囲であれば、榭脂との接着性を高く維持できる。  The degree of roughness of the metal wiring surface which does not form the gold is preferably in the range of 1 to: LO / zm in the ten-point average roughness Rz specified in JIS B 0601. The range is 6 / ιπζ. If it is the said range, adhesiveness with a resin can be maintained highly.
[0044] (実施形態 2)  Embodiment 2
本発明の半導体装置の別の一実施形態を、図 2の模式的な断面図を参照して説 明する。 201は半導体チップ、 202は半導体チップの素子電極、 203は金ワイヤ、 20 4は電気絶縁性基板、 205は金属配線、 206は半導体チップが実装される電極端子 、 207は金属配線の粗ィ匕部分、 208は電極端子の金層、 209はモールド榭脂、 210 は半導体チップのダイボンディング材である。  Another embodiment of the semiconductor device of the present invention will be described with reference to the schematic cross-sectional view of FIG. 201 is a semiconductor chip, 202 is an element electrode of the semiconductor chip, 203 is a gold wire, 204 is an electrically insulating substrate, 205 is a metal wiring, 206 is an electrode terminal on which the semiconductor chip is mounted, and 207 is a rough metal wiring A portion 208 is a gold layer of the electrode terminal, 209 is a mold resin, and 210 is a die bonding material of the semiconductor chip.
[0045] 電気絶縁性基板 204の金属配線の中で、半導体チップ 201がワイヤボンディング 実装される電極端子 206の表面に金を形成し、その他の金属配線 205の表面には 金を形成せずに粗化 (207)処理することにより、モールド榭脂 209と電気絶縁性基 板 204の接着強度を大きくし、モールド榭脂 209によって保持されている半導体チッ プ 201のワイヤボンディング実装の電気接続信頼性を向上させることができる。粗ィ匕 の程度は実施形態 1と同程度が好まし 、。  Among the metal wires of the electrically insulating substrate 204, gold is formed on the surface of the electrode terminal 206 on which the semiconductor chip 201 is mounted by wire bonding, and gold is not formed on the surface of the other metal wires 205. By roughening (207) treatment, the adhesive strength between the mold resin 209 and the electrically insulating substrate 204 is increased, and the electrical connection reliability of the wire bonding mounting of the semiconductor chip 201 held by the mold resin 209 is achieved. Can be improved. The degree of coarseness is preferably the same as in Embodiment 1.
[0046] (実施形態 3)  Embodiment 3
本発明の半導体装置の別の一実施形態を、図 3の模式的な断面図を参照して説 明する。 301は積層半導体チップ、 302は積層半導体チップの素子電極、 303は金 ワイヤ、 304は電気絶縁性基板、 305は金属配線、 306は積層半導体チップが実装 される電極端子、 307は金属配線の粗ィ匕部分、 308は電極端子の金層、 309はモー ルド榭脂、 310は半導体チップのダイボンディング材である。 Another embodiment of the semiconductor device of the present invention will be described with reference to the schematic sectional view of FIG. Reference numeral 301 is a laminated semiconductor chip, 302 is an element electrode of the laminated semiconductor chip, 303 is a gold wire, 304 is an electrically insulating substrate, 305 is a metal wiring, 306 is an electrode terminal on which the laminated semiconductor chip is mounted, 307 is a rough metal wiring Part 308, gold layer of electrode terminal, 309 Lud resin 310 is a die bonding material for semiconductor chips.
[0047] 2個の半導体チップが積層された積層半導体チップ 301がワイヤボンディング実装 された半導体装置においても、実施形態 1〜2と同様に、電気絶縁性基板 304の金 属配線の中で、積層半導体チップ 301がワイヤボンディング実装される電極端子 30 6の表面に金を形成し、その他の金属配線 305の表面には金を形成せず粗化 (307 )処理することにより、モールド榭脂 309と電気絶縁性基板 304の接着強度を大きくし 、モールド榭脂 309によって保持されて 、る積層半導体チップ 301のワイヤボンディ ング実装の電気接続信頼性を向上させることができる。また、積層する半導体チップ 数が 3枚に増えても、同様の効果を得ることができる。粗化の程度は実施形態 1と同 程度が好ましい。  Also in the semiconductor device in which the laminated semiconductor chip 301 in which the two semiconductor chips are laminated is mounted by wire bonding, as in the first and second embodiments, the metal wiring of the electrically insulating substrate 304 is laminated. The semiconductor chip 301 forms gold on the surface of the electrode terminal 306 on which the wire bonding is mounted, and the surface of the other metal wiring 305 does not form gold but is roughened (307) to obtain mold resin 309 and The bonding strength of the electrically insulating substrate 304 can be increased, and the electrical connection reliability of the wire bonding mounting of the laminated semiconductor chip 301 held by the mold resin 309 can be improved. Further, even if the number of semiconductor chips to be stacked is increased to three, the same effect can be obtained. The degree of roughening is preferably the same as in Embodiment 1.
[0048] (実施形態 4)  Embodiment 4
本発明の半導体装置の別の一実施形態を、図 4の模式的な断面図を参照して説 明する。 401は積層半導体チップ、 402は積層半導体チップの素子電極、 403は金 ワイヤ、 404はバンプ、 405は電気絶縁性基板、 406は金属配線、 407は積層半導 体チップが実装される電極端子、 408は金属配線の粗ィ匕部分、 409は電極端子の 金層、 410はモールド榭脂、 411は封止榭脂、 412は積層半導体チップのダイボン ディング材である。  Another embodiment of the semiconductor device of the present invention will be described with reference to the schematic cross-sectional view of FIG. 401 is a laminated semiconductor chip, 402 is an element electrode of the laminated semiconductor chip, 403 is a gold wire, 404 is a bump, 405 is an electrically insulating substrate, 406 is a metal wiring, 407 is an electrode terminal on which the laminated semiconductor chip is mounted, The numeral 408 is a rough portion of metal wiring, 409 is a gold layer of the electrode terminal, 410 is a mold resin, 411 is a sealing resin, and 412 is a die bonding material of the laminated semiconductor chip.
[0049] 2個の半導体チップが積層された積層半導体チップ 401がフリップチップ実装及び ワイヤボンディング実装によって電気接続された半導体装置にぉ 、ても、実施形態 1 〜3と同様に電気絶縁性基板 405の金属配線の中で、積層半導体チップ 401がワイ ャボンディング実装及びフリップチップ実装によって電気接続される電極端子 407の 表面に金を形成し、その他の金属配線 406の表面には金を形成せずに粗化 (408) 処理することにより、モールド榭脂 410及び封止榭脂 411と電気絶縁性基板 405の 接着強度を大きくし、モールド榭脂 410及び封止榭脂 411によって保持されている 積層半導体チップ 401のワイヤボンディング実装及びフリップチップ実装の電気接続 信頼性を向上させることができる。また、積層する半導体チップ数が 3枚に増えても、 最下段の半導体チップをフリップチップ実装、上二段の半導体チップをワイヤボンデ イングすることで作製することができる。粗ィ匕の程度は実施形態 1と同程度が好ましい [0050] (実施形態 5) Even in a semiconductor device in which a stacked semiconductor chip 401 in which two semiconductor chips are stacked is electrically connected by flip chip mounting and wire bonding mounting, the electrically insulating substrate 405 is the same as in the first to third embodiments. Among the metal interconnections, gold is formed on the surface of the electrode terminal 407 to which the laminated semiconductor chip 401 is electrically connected by wire bonding mounting and flip chip mounting, and gold is not formed on the surface of the other metal interconnection 406. By roughening (408) treatment, the adhesive strength between the mold resin 410 and the sealing resin 411 and the electrically insulating substrate 405 is increased, and the laminated semiconductor held by the mold resin 410 and the sealing resin 411 is obtained. Electrical connection reliability of wire bonding mounting and flip chip mounting of the chip 401 can be improved. Further, even if the number of semiconductor chips to be stacked is increased to three, it can be manufactured by flip-chip mounting the lowermost semiconductor chip and wire bonding the upper two semiconductor chips. The same degree of coarseness as in Embodiment 1 is preferable. Embodiment 5
本発明の半導体装置の別の一実施形態を、図 5の模式的な断面図を参照して説 明する。 501は半導体チップ、 502は半導体チップの素子電極、 503はバンプ、 504 は電気絶縁性基板、 505は金属配線、 506は半導体チップが実装される電極端子、 507は金属配線の粗ィ匕部分、 508は電極端子の金層、 509は封止榭脂、 510は無 機フイラ一と熱硬化性榭脂とを含む混合物からなる電気絶縁性基板、 511は導電性 榭脂組成物が充填されたインナービアである。  Another embodiment of the semiconductor device of the present invention will be described with reference to the schematic cross sectional view of FIG. 501 is a semiconductor chip, 502 is an element electrode of the semiconductor chip, 503 is a bump, 504 is an electrically insulating substrate, 505 is a metal wiring, 506 is an electrode terminal on which the semiconductor chip is mounted, 507 is a rough surface portion of metal wiring, 508 is a gold layer of the electrode terminal, 509 is a sealing resin, 510 is an electrically insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin, and 511 is filled with a conductive resin composition. It is an inner via.
[0051] フリップチップ実装された半導体を電気絶縁性基板に内蔵した部品内蔵モジユー ルの形態の半導体装置において、電気絶縁性基板 504の金属配線の中で、半導体 チップ 501がフリップチップ実装される電極端子 506の表面に金を形成し、その他の 金属配線 505の表面には金を形成せず粗化（507)処理することにより、封止榭脂 5 09と電気絶縁性基板 504の接着強度及び無機フィラーと熱硬化性榭脂とを含む混 合物からなる電気絶縁性基板 510と電気絶縁性基板 504の接着強度を大きくできる 。また、これにより封止榭脂 509によって保持され、電気絶縁性基板 510に内蔵され ている半導体チップ 501のフリップチップ実装の電気接続信頼性を向上させることが できる。この実施形態 5のような半導体チップ 501が電気絶縁性基板 510に内蔵され た形態においては、表面実装された半導体チップの形態より封止榭脂 509、電気絶 縁性基板 504間の剥離応力が大きぐ信頼性の高い電気接続の実現が難しいが、 本実施形態の半導体装置によって、半導体チップの電気接続の信頼性を大きく向上 させることができる。また、導電性榭脂組成物が充填されたインナービア 511の電気 接続される金属配線の表面が粗化処理されており、平滑な金層の場合、導電性榭脂 糸且成物が充填されたインナービア 511が金層上を滑って位置ずれを起こしやすかつ たが、本実施形態の半導体装置では、位置ずれを抑制することができる。また、イン ナービアと電気絶縁性基板の金属配線の接着強度が大きくなり、部品内蔵モジユー ルの形態の半導体装置における信頼性の高いインナービア接続を実現することがで きる。粗ィ匕の程度は実施形態 1と同程度が好ましい。  In a semiconductor device in the form of a module with a built-in component in which a flip chip mounted semiconductor is incorporated in an electrically insulating substrate, an electrode on which the semiconductor chip 501 is flip chip mounted among the metal wiring of the electrically insulating substrate 504. By forming gold on the surface of the terminal 506 and roughening (507) without forming gold on the surface of the other metal wiring 505, adhesion strength of the sealing resin 5 09 and the electrically insulating substrate 504 and The adhesive strength between the electrically insulating substrate 510 and the electrically insulating substrate 504, which is a mixture containing an inorganic filler and a thermosetting resin, can be increased. In addition, the electrical connection reliability of flip chip mounting of the semiconductor chip 501 held by the sealing resin 509 and incorporated in the electrically insulating substrate 510 can be improved. In the embodiment in which the semiconductor chip 501 as in this embodiment 5 is incorporated in the electrically insulating substrate 510, the peeling stress between the sealing resin 509 and the electrically insulating substrate 504 is smaller than the form of the surface mounted semiconductor chip. Although it is difficult to realize highly reliable electrical connection, the semiconductor device of this embodiment can greatly improve the reliability of the electrical connection of the semiconductor chip. In addition, the surface of the metal wire electrically connected to the inner via 511 filled with the conductive resin composition is roughened, and in the case of a smooth gold layer, the conductive resin yarn is filled. Although the inner vias 511 easily slip on the gold layer and cause misalignment, the semiconductor device of this embodiment can suppress the misalignment. In addition, the bonding strength between the inner via and the metal wiring of the electrically insulating substrate is increased, and a highly reliable inner via connection can be realized in the semiconductor device in the form of a module with a built-in component. The degree of coarseness is preferably the same as in Embodiment 1.
[0052] (実施形態 6) 本発明の半導体装置の製造方法の一実施形態を、図 6A— Dの模式的な工程断 面図を参照して説明する。 601は半導体チップ、 602は半導体チップの素子電極、 6 03はバンプ、 604は電気絶縁性基板、 605は金属配線、 606は半導体チップが実 装される電極端子、 607は金属配線の粗ィ匕部分、 608は電極端子の金層、 609は封 止榭脂、 610はフォトレジストである。 Embodiment 6 One embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to schematic process sectional views of FIGS. 6A to 6D. 601 is a semiconductor chip, 602 is an element electrode of the semiconductor chip, 603 is a bump, 604 is an electrically insulating substrate, 605 is a metal wiring, 606 is an electrode terminal on which the semiconductor chip is mounted, and 607 is a rough metal wiring Part 608 is a gold layer of the electrode terminal, 609 is a sealing resin, and 610 is a photoresist.
[0053] まず、金属配線 605の表面が粗化された電気絶縁性基板 604を用意する（図 6A) 。次に、フォトリソグラフィ一法により半導体チップ 601 (図 6D)がフリップチップ実装さ れる電極端子 606を除く部分にフォトレジスト 610を形成する（図 6B)。次に、電極端 子 606の表面に金 608を形成する。金層 608は金メッキにより形成する。その後、フ オトレジスト 610を除去する（図 6C)。次に、封止榭脂 609を介して半導体チップ 601 を電気絶縁性基板 604にフリップチップ実装して、本実施形態の半導体装置を作製 する（図 6D)。以上のとおり、既存のフリップチップ実装技術とフォトリソグラフィ一法を そのまま使用することができ、信頼性の高い半導体装置を作製することができる。  First, an electrically insulating substrate 604 in which the surface of the metal wiring 605 is roughened is prepared (FIG. 6A). Next, a photoresist 610 is formed on the portion excluding the electrode terminal 606 to which the semiconductor chip 601 (FIG. 6D) is flip-chip mounted by a photolithographic method (FIG. 6B). Next, gold 608 is formed on the surface of the electrode terminal 606. The gold layer 608 is formed by gold plating. Thereafter, photoresist 610 is removed (FIG. 6C). Next, the semiconductor chip 601 is flip-chip mounted on the electrically insulating substrate 604 via the sealing resin 609 to fabricate the semiconductor device of this embodiment (FIG. 6D). As described above, the existing flip chip mounting technology and the photolithography method can be used as they are, and a highly reliable semiconductor device can be manufactured.
[0054] (実施形態 7)  Embodiment 7
本発明の半導体装置の製造方法の別の一実施形態を、図 7A— Eの模式的なェ 程断面図を参照して説明する。 701は半導体チップ、 702は半導体チップの素子電 極、 703は金ワイヤ、 704は電気絶縁性基板、 705は金属配線、 706は半導体チッ プが実装される電極端子、 707は金属配線の粗ィ匕部分、 708は電極端子の金層、 7 09はモールド榭脂、 710は半導体チップのダイボンディング材、 711はフォトレジスト である。  Another embodiment of a method of manufacturing a semiconductor device of the present invention will be described with reference to schematic process sectional views of FIGS. 7A to 7E. Reference numeral 701 is a semiconductor chip, 702 is an element electrode of the semiconductor chip, 703 is a gold wire, 704 is an electrically insulating substrate, 705 is a metal wiring, 706 is an electrode terminal on which the semiconductor chip is mounted, and 707 is a rough metal wiring. A ridge portion 708 is a gold layer of an electrode terminal, 7 09 is a mold resin, 710 is a die bonding material of a semiconductor chip, and 711 is a photoresist.
[0055] まず、金属配線 705の表面が粗化された電気絶縁性基板 704を用意する（図 7A) 。次に、フォトリソグラフィ一法により半導体チップがワイヤボンディング実装される電 極端子 706を除く部分にフォトレジスト 711を形成する（図 7B)。次に、電極端子 706 の表面に金を形成し、フォトレジスト 710を除去する（図 7C)。次に、半導体チップ 70 1の素子電極 702が形成されて 、な 、面をダイボンディング材 710を介して絶縁性 基板 704に接合し、金ワイヤ 703を用 、て半導体チップ 701をワイヤボンディング実 装する（図 7D)。その後、半導体チップ 701及び金ワイヤ 703を含むワイヤボンディ ング実装部をモールド榭脂 709でモールドし、本実施形態の半導体装置を作製する (図 7E)。以上のようにして既存のワイヤボンディング実装技術とフォトリソグラフィー 法をそのまま使用することができ、信頼性の高い半導体装置を作製することができる First, an electrically insulating substrate 704 in which the surface of the metal wiring 705 is roughened is prepared (FIG. 7A). Next, a photoresist 711 is formed on the portion excluding the electrode terminal 706 where the semiconductor chip is wire-bonded and mounted by a photolithography method (FIG. 7B). Next, gold is formed on the surface of the electrode terminal 706, and the photoresist 710 is removed (FIG. 7C). Next, the element electrode 702 of the semiconductor chip 701 is formed, and the surface is bonded to the insulating substrate 704 through the die bonding material 710, and the gold wire 703 is used to mount the semiconductor chip 701 with the wire bonding. Yes (Figure 7D). Thereafter, a wire bonding mounting portion including the semiconductor chip 701 and the gold wire 703 is molded with a mold resin 709 to manufacture the semiconductor device of the present embodiment. (Figure 7E). As described above, the existing wire bonding mounting technology and the photolithography method can be used as they are, and a highly reliable semiconductor device can be manufactured.
[0056] (実施形態 8) Embodiment 8
本発明の半導体装置の製造方法の別の一実施形態を、図 8A— Iの模式的な工程 断面図を参照して説明する。 801は半導体チップ、 802は半導体チップの素子電極 、 803はバンプ、 804は半導体チップが電気接続される電気絶縁性基板、 805は電 気絶縁性基板、 806は無機フィラーと熱硬化性榭脂とを含む混合物カゝらなる板状体 、 807は貫通孔、 808は導電性榭脂組成物カゝらなる導電性ペーストが充填されたィ ンナービア、 809は金属配線、 810は半導体チップが実装される電極端子、 811は 金属配線の粗化部分、 812は電極端子の金層、 813は封止榭脂、 814はフォトレジ ストである。  Another embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to schematic cross-sectional views of FIGS. 8A-I. 801 is a semiconductor chip, 802 is an element electrode of the semiconductor chip, 803 is a bump, 804 is an electrically insulating substrate to which the semiconductor chip is electrically connected, 805 is an electrically insulating substrate, 806 is an inorganic filler and a thermosetting resin A plate containing a mixture of metals, 807 is a through hole, 808 is an inner via filled with a conductive paste consisting of a conductive resin composition, 809 is a metal wiring, and 810 is a semiconductor chip mounted. 811 is a roughened portion of the metal wiring, 812 is a gold layer of the electrode terminal, 813 is a sealing resin, and 814 is a photoresist.
[0057] まず、金属配線 809の表面が粗化された電気絶縁性基板 804を用意する（図 8A) 。次に、フォトリソグラフィ一法により半導体チップがフリップチップ実装される電極端 子 810を除く部分にフォトレジスト 814を形成する（図 8B)。次に、電極端子 810の表 面に金層 812を形成し、フォトレジスト 814を除去する（図 8C)。次に、封止榭脂 813 を介して半導体チップ 801を電気絶縁性基板 804にフリップチップ実装する（図 8D) 。一方、無機フィラーと熱硬化性榭脂とを含む混合物カゝらなる板状体 806を準備し（ 図 8E)、導電性ペーストが充填されインナービア 808となる貫通孔 807を形成する（ 図 8F)。次に、貫通孔 807に導電性ペーストを充填する（図 8G)。次に、半導体チッ プ 801をフリップチップ実装した電気絶縁性基板 804と、導電性ペーストが充填され たインナービア 808が形成された板状体 806と、板状体 806のもう一方の金属配線を 形成するための電気絶縁性基板 805を、インナービア 808によって電気接続するよう に位置あわせする（図 8H)。次に、加熱加圧して、電気絶縁性基板 804と板状体 80 6と電気絶縁性基板 805を接着して、半導体チップ 801を板状体 806に埋設して一 体ィ匕し、板状体 806及びインナービア 808に充填された導電性ペーストを硬化して、 本実施形態の半導体装置を作製する（図 81)。以上のように、既存のフリップチップ実 装技術とフォトリソグラフィ一法をそのまま使用することができ、信頼性の高い半導体 装置を作製することができる。また、加熱加圧工程による半導体チップの板状体への 埋設時に、導電性ペーストが充填されたインナービアと電気接続される金属配線が 粗化されており、インナービアの位置ずれが置きにくいため、金属配線の微細化、ィ ンナービアのビアピッチの狭ピッチ化が進んでも、この半導体装置では、導電性榭脂 組成物からなる導電性ペーストが充填されたインナービアを位置精度良く形成するこ とがでさる。 First, an electrically insulating substrate 804 in which the surface of the metal wire 809 is roughened is prepared (FIG. 8A). Next, a photoresist 814 is formed on the portion excluding the electrode terminal 810 where the semiconductor chip is flip-chip mounted by a photolithographic method (FIG. 8B). Next, a gold layer 812 is formed on the surface of the electrode terminal 810, and the photoresist 814 is removed (FIG. 8C). Next, the semiconductor chip 801 is flip-chip mounted on the electrically insulating substrate 804 via the sealing resin 813 (FIG. 8D). On the other hand, a plate-like body 806 made of a mixture of an inorganic filler and a thermosetting resin is prepared (FIG. 8E), and a conductive paste is filled to form through holes 807 to be inner vias 808 (FIG. 8F). ). Next, the through holes 807 are filled with a conductive paste (FIG. 8G). Next, an electrically insulating substrate 804 on which a semiconductor chip 801 is flip-chip mounted, a plate 806 having an inner via 808 filled with a conductive paste, and the other metal wiring of the plate 806 are used. An electrically insulating substrate 805 to be formed is aligned to be electrically connected by the inner via 808 (FIG. 8H). Next, heat and pressure are applied to bond the electrically insulating substrate 804, the plate-like body 806, and the electrically insulating substrate 805, and the semiconductor chip 801 is embedded in the plate-like body 806 and integrally formed. The conductive paste filled in the body 806 and the inner via 808 is cured to fabricate the semiconductor device of the present embodiment (FIG. 81). As described above, it is possible to use the existing flip chip mounting technology and one photolithography method as it is, and a highly reliable semiconductor. The device can be made. In addition, when the semiconductor chip is embedded in the plate-like body by the heating and pressing process, the metal wiring electrically connected to the inner via filled with the conductive paste is roughened, and the positional deviation of the inner via is difficult to set. In this semiconductor device, it is possible to form an inner via filled with a conductive paste made of a conductive resin composition with high positional accuracy, even if miniaturization of metal wiring and narrowing of via pitch of inner via progress. You
実施例  Example
[0058] 以下、実施例により本発明をさらに具体的に説明する。  Hereinafter, the present invention will be more specifically described by way of examples.
[0059] (実施例 1) Example 1
実施例 1では上述の実施の形態 5の部品内蔵モジュールの形態の半導体装置を、 次の（i)〜 (iv)の手順に従って製造した。  In Example 1, the semiconductor device in the form of the component built-in module of the fifth embodiment described above was manufactured according to the following procedures (i) to (iv).
(i)電気絶縁性基板における電極端子の金層の形成  (i) Formation of gold layer of electrode terminal on electrically insulating substrate
半導体チップを実装する電気絶縁性基板としてガラスエポキシ基板を準備した。ガ ラスエポキシ基板は厚さ 200 m、半導体チップを実装する電極端子、導電性榭脂 組成物からなる導電性ペーストが充填されたインナービアを接続するビアランド、及 びそれらを電気接続する金属配線が形成されており、それらの金属配線の厚さは 18 mで、表面の粗ィ匕度合いは平均十点粗さ Rz5 mに粗ィ匕されている。フォトリソダラ フィ一法を用いてガラスエポキシ基板の半導体チップが実装される電極端子を除く部 分にフォトレジストを形成した。フォトレジストには旭化成社製 AQ— 1558を用いた。 次に、このガラスエポキシ基板に無電解ニッケルメツキを: L m、引き続いて無電解金 メツキ 0.04 mを形成した。メツキ浴にはウェムラ 'インターナショナル'シンガポール 社製の-ムデン NPR— M、ォーリカル TKK51 M20を用いた。以上の工程により、 半導体チップを実装する電極端子の表面のみに金を形成したガラスエポキシ基板を 作製した。  A glass epoxy substrate was prepared as an electrically insulating substrate for mounting a semiconductor chip. The glass epoxy substrate has a thickness of 200 m, electrode terminals for mounting semiconductor chips, via lands for connecting inner vias filled with a conductive paste consisting of a conductive resin composition, and metal wiring for electrically connecting them. The thickness of the metal wiring is 18 m, and the surface roughness is roughened to an average ten-point roughness Rz 5 m. A photoresist was formed on the portion other than the electrode terminal on which the semiconductor chip of the glass epoxy substrate is mounted using the photolithographic method. As a photoresist, AQ-1558 manufactured by Asahi Kasei Corporation was used. Next, electroless nickel plating was formed on the glass epoxy substrate: L m, and subsequently electroless gold plating of 0.04 m was formed. We used 'Muden NPR-M' and 'Oralic TKK51 M20, manufactured by Wemura' International 'Singapore, for the plating bath. Through the above steps, a glass epoxy substrate was produced in which gold was formed only on the surface of the electrode terminal on which the semiconductor chip is mounted.
(ii)半導体チップの実装  (ii) Mounting of semiconductor chip
10mm角、厚さ 0.3mmの半導体チップを準備し、半導体チップの 100個の素子電 極に予め金ワイヤボンディング法によって高さ 70 μ mの金バンプを突起状電極として 形成した。フリップチップ実装に用いる封止榭脂には、 日立化成社製の厚さ 40 m のシート状封止榭脂 UF— 511を用いた。このシート状封止榭脂を面積が 100平方 m mとなるように加工した後、ガラスエポキシ基板の半導体チップが実装される領域に 貼り付けた。次に、半導体チップを素子電極が形成されていない背面から加熱加圧 し、ガラスエポキシ基板にフリップチップ実装した。加熱温度は 200°C、圧力は 3MP a、加熱加圧時間は 15秒とした。その結果、半導体チップの素子電極とガラスェポキ シ基板の無電解金メッキされた電極端子が、金バンプを介して電気接続され、封止 榭脂が硬化した。 A 10 mm square semiconductor chip having a thickness of 0.3 mm was prepared, and gold bumps having a height of 70 μm were formed in advance as protruding electrodes on 100 element electrodes of the semiconductor chip by a gold wire bonding method. The sealing resin used for flip chip mounting has a thickness of 40 m manufactured by Hitachi Chemical Co., Ltd. Sheet-like sealing resin UF-511 was used. The sheet-like sealing resin was processed to have an area of 100 mm 2 and then attached to the area of the glass epoxy substrate on which the semiconductor chip was mounted. Next, the semiconductor chip was heated and pressurized from the back side where the device electrode was not formed, and flip chip mounting was performed on a glass epoxy substrate. The heating temperature was 200 ° C., the pressure was 3 MP a, and the heating and pressurizing time was 15 seconds. As a result, the element electrode of the semiconductor chip and the electroless gold-plated electrode terminal of the glass epoxy substrate were electrically connected through the gold bump, and the sealing resin was cured.
(iii)無機フィラーと熱硬化性榭脂とを含む混合物カゝらなる板状体の準備  (iii) Preparation of a plate made of a mixture containing an inorganic filler and a thermosetting resin
まず無機フィラーと熱硬化性榭脂の混合を、板状体を構成する材料を、必要に応じ て粘度調整のための微量の溶剤を投入し、混合攪拌機を用いて混合し調整した。本 実施例では、エポキシ榭脂 10重量％、シリカフィラー 90重量％を含む混合物を 10 分間攪拌して調整した。次に、この混合物から、ドクターブレード法によって厚さ 100 μ mの板状体を作製した。次に、この板状体を 4枚重ねてラミネートし、厚さ 400 m の板状体を形成した後、パンチヤーを用いてインナービアとなる直径 160 mの貫通 孔を形成し、この貫通孔に導電性ペーストをスクリーン印刷法により充填した。ここで 使用した導電性ペーストは、球形状の銅粒子 85重量％と、榭脂成分としてビスフエノ ール A型エポキシ榭脂（油化シェルエポキシ社製「ェピコート 828」） 3重量％と、ダリ シジルエステル系エポキシ榭脂 (東都化成社製「YD— 171」） 9重量％と、硬化剤と してアミンァダクト硬ィ匕剤（味の素社製「MY— 24」 ) 3重量％とを三本ロールを用いて 混鍊して調整した。  First, a mixture of an inorganic filler and a thermosetting resin was prepared, and, if necessary, a small amount of solvent for viscosity adjustment was added to the material constituting the plate, and the mixture was adjusted by mixing using a mixing stirrer. In this example, a mixture containing 10% by weight of epoxy resin and 90% by weight of silica filler was adjusted by stirring for 10 minutes. Next, a plate-like body having a thickness of 100 μm was produced from this mixture by a doctor blade method. Next, four sheets of this plate-like body are laminated and laminated to form a plate-like body having a thickness of 400 m, and then a puncher is used to form a through hole having a diameter of 160 m to be an inner via. The conductive paste was filled by screen printing. The conductive paste used here is 85% by weight of spherical copper particles, 3% by weight of bis-phenol A-type epoxy resin (“Epicoat 828” manufactured by Yuka Shell Epoxy Co., Ltd.) as a resin component, and A triple roll of 9% by weight of an ester-based epoxy resin ("YD-171" manufactured by Tohto Kasei Co., Ltd.) and 3% by weight of an amine adduct hard coat agent ("MY- 24" manufactured by Ajinomoto Co., Ltd.) as a curing agent. It was mixed and adjusted.
(iv)半導体チップの内蔵、一体ィ匕  (iv) Built-in semiconductor chip, integrated design
次に (ii)で得た半導体チップをフリップチップ実装したガラスエポキシ基板と、 (iii) で得た導電性ペーストを充填したインナービアが形成された板状体、そして板状体の もう一方の主面の金属配線を形成するためのガラスエポキシ基板を準備し、これらを 半導体チップが板状体に内蔵されるよう、板状体のインナービアによって 2つのガラ スエポキシ基板及び板状体が電気接続されるよう、位置合わせした後、加熱加圧す ることで一体化し、本実施例の部品内蔵モジュールをした半導体装置を得た。加熱 加圧は熱プレス機を用いて、加熱温度は 200°C、圧力は 3MPa、加熱加圧時間は 2 時間とした。板状体に含まれるエポキシ榭脂は、粘度が一旦低下した後、硬化し、板 状体とガラスエポキシ基板が接着された。導電性ペーストが充填されたインナービア に含まれるエポキシ榭脂も硬化し、板状体を通して 2つのガラスエポキシ基板が電気 接続された。 Next, a glass epoxy substrate on which the semiconductor chip obtained in (ii) is flip-chip mounted, a plate-like body having an inner via filled with the conductive paste obtained in (iii), and the other of the plate-like body The glass epoxy substrate for forming the metal wiring of the main surface is prepared, and the two glass epoxy substrates and the plate are electrically connected by the inner via of the plate so that the semiconductor chip is embedded in the plate. After alignment, they were integrated by heating and pressing to obtain a semiconductor device having the component built-in module of this embodiment. Heating and pressurizing using a heat press, heating temperature 200 ° C, pressure 3MPa, heating and pressurizing time 2 It was time. The epoxy resin contained in the plate-like body was cured after the viscosity once decreased, and the plate-like body and the glass epoxy substrate were adhered. The epoxy resin contained in the inner via filled with the conductive paste was also cured, and the two glass epoxy substrates were electrically connected through the plate.
[0060] このようにして本実施例の半導体装置を作製した。  Thus, the semiconductor device of this example was manufactured.
[0061] 比較例として、従来例と同様に前記 (i)の工程で、半導体チップが実装される電極 端子を含む一面の全部の金属配線の表面に、同様の方法で金層を形成した半導体 装置を作製した。  As a comparative example, in the same manner as in the conventional example, in the step (i), a semiconductor in which a gold layer is formed by the same method on the surface of all the metal wires on one surface including the electrode terminal on which the semiconductor chip is mounted The device was made.
[0062] 2つの半導体装置の電気接続信頼性の評価は、吸湿リフロー試験によって行なつ た。具体的な条件は、 85°C、 85%RH条件下で 168時間保持した後、最高温度 260 °Cであるベルト式リフロー試験機を用いて熱衝撃を加えた。半導体装置の信頼性とし て、フリップチップ実装の半導体チップの素子電極とガラスエポキシ基板の電極端子 との間の接続抵抗値 (以下、バンプ抵抗と略）によって評価した。評価基準はバンプ 抵抗が吸湿リフロー試験前後で 10%以上変化したものを不良とし、 100個の電気接 続点に対する不良発生率で評価した結果、従来の半導体装置では 60%不良が発 生したが、本発明の半導体装置では不良は発生しな力 た。  Evaluation of the electrical connection reliability of the two semiconductor devices was performed by a moisture absorption reflow test. Concrete conditions were that thermal shock was applied using a belt type reflow tester with a maximum temperature of 260.degree. C. after holding for 168 hours under conditions of 85.degree. C. and 85% RH. The reliability of the semiconductor device was evaluated by the connection resistance value (hereinafter referred to as bump resistance) between the element electrode of the semiconductor chip of flip chip mounting and the electrode terminal of the glass epoxy substrate. The evaluation criteria were that the bump resistance changed 10% or more before and after the moisture absorption reflow test as a defect, and as a result of evaluating the defect incidence rate for 100 electrical connection points, 60% failure occurred in the conventional semiconductor device. In the semiconductor device of the present invention, no failure occurred.
[0063] このように本実施例の半導体装置は、半導体チップが実装される電極端子の表面 に金層を形成し、榭脂と接着するその他の金属配線の表面に粗化処理を行なうこと で、半導体チップの実装の電気接続信頼性を向上することができる。  As described above, in the semiconductor device of the present example, a gold layer is formed on the surface of the electrode terminal on which the semiconductor chip is mounted, and the surface of the other metal wiring to be bonded to the resin is roughened. The electrical connection reliability of the mounting of the semiconductor chip can be improved.
産業上の利用可能性  Industrial applicability
[0064] 本発明によれば、半導体チップが実装された半導体装置を信頼性の高!ヽ電気接 続で製造することができる。 According to the present invention, a semiconductor device on which a semiconductor chip is mounted can be manufactured with high reliability and electrical connection.

Claims

請求の範囲 The scope of the claims
[1] 複数の金属配線を備えた電気絶縁性基板の表面に半導体チップが実装され、少 なくとも前記複数の金属配線の一部を榭脂が覆っている半導体装置であって、 前記電気絶縁性基板に形成された複数の金属配線のうち、少なくとも前記半導体 チップと電気的に接続される金属配線の表面には金層を形成し、  [1] A semiconductor device in which a semiconductor chip is mounted on the surface of an electrically insulating substrate provided with a plurality of metal wirings, and a resin covers at least a part of the plurality of metal wirings, A gold layer is formed on the surface of the metal wiring electrically connected to at least the semiconductor chip among the plurality of metal wirings formed on the insulating substrate,
前記電気絶縁性基板に形成された複数の金属配線のうち、前記樹脂と接触する金 属配線の表面には粗化部を形成することを特徴とする半導体装置。  A semiconductor device characterized in that a roughened portion is formed on a surface of a metal wire in contact with the resin among a plurality of metal wires formed on the electrically insulating substrate.
[2] 前記半導体チップの実装はフリップチップ実装であり、前記半導体チップの素子電 極面と前記電気絶縁性基板の電極端子面との間に封止榭脂が位置している請求項 1に記載の半導体装置。  [2] The mounting of the semiconductor chip is a flip chip mounting, and a sealing resin is positioned between the element electrode surface of the semiconductor chip and the electrode terminal surface of the electrically insulating substrate. The semiconductor device of description.
[3] 前記半導体チップの実装はワイヤボンディング実装であり、  [3] The mounting of the semiconductor chip is a wire bonding mounting,
前記半導体チップの素子電極面の反対の主面が前記電気絶縁性基板のワイヤボ ンデイング実装される主面に接合され、前記半導体チップ、前記ワイヤボンディング 実装部分が榭脂モールドされて 、る請求項 1に記載の半導体装置。  The main surface opposite to the element electrode surface of the semiconductor chip is bonded to the main surface of the electrically insulating substrate on which the wire bonding is mounted, and the semiconductor chip and the wire bonding mounting portion are resin-molded. The semiconductor device according to claim 1.
[4] 前記半導体チップは複数の半導体チップが積層された積層半導体チップであり、 前記積層半導体チップ力 Sワイヤボンディング実装された電極端子を含む複数の金 属配線が形成された主面をもつ電気絶縁性基板とを備え、 [4] The semiconductor chip is a stacked semiconductor chip in which a plurality of semiconductor chips are stacked, and the stacked semiconductor chip power S electric wire having a main surface on which a plurality of metal wires including an electrode terminal mounted by wire bonding is formed. And an insulating substrate,
前記積層半導体チップのうち一つの半導体チップの素子電極面の反対の主面が 前記電気絶縁性基板のワイヤボンディング実装される主面に接合され、前記積層半 導体チップ、前記ワイヤボンディング実装部分が榭脂モールドされて!/、る請求項 1に 記載の半導体装置。  The principal surface opposite to the element electrode surface of one semiconductor chip among the laminated semiconductor chips is joined to the principal surface of the electrically insulating substrate on which the wire bonding is mounted, and the laminated semiconductor chip and the wire bonding mounting portion The semiconductor device according to claim 1, which is oil-molded.
[5] 前記半導体チップは複数の半導体チップが積層された積層半導体チップであり、 前記積層半導体チップ力 Sワイヤボンディング実装及びフリップチップ実装された電 極端子を含む複数の金属配線が形成された主面をもつ電気絶縁性基板とを備え、 前記積層半導体チップのフリップチップ実装された半導体チップの素子電極面と 前記電気絶縁性基板の電極端子面との間に封止榭脂が位置しており、  [5] The semiconductor chip is a laminated semiconductor chip in which a plurality of semiconductor chips are laminated, and the laminated semiconductor chip force S wire bonding mounting and a plurality of metal wirings including flip-chip mounted electrode terminals are mainly formed A sealing resin is positioned between the device electrode surface of the flip-chip mounted semiconductor chip of the laminated semiconductor chip and the electrode terminal surface of the electric insulating substrate; ,
前記積層半導体チップ、前記ワイヤボンディング実装部分が榭脂モールドされてい る請求項 1に記載の半導体装置。 The semiconductor device according to claim 1, wherein the laminated semiconductor chip and the wire bonding mounting portion are resin-molded.
[6] 前記半導体チップの実装はフリップチップ実装であり、 [6] The mounting of the semiconductor chip is flip chip mounting,
前記半導体チップがフリップチップ実装された第 1の電気絶縁性基板と、 複数の金属配線が形成された主面をもつ第 2の電気絶縁性基板と、  A first electrically insulating substrate on which the semiconductor chip is flip chip mounted, and a second electrically insulating substrate having a main surface on which a plurality of metal interconnections are formed;
前記第 1の電気的絶縁基板と前記第 2の電気的絶縁基板との間に配置されている Disposed between the first electrically insulating substrate and the second electrically insulating substrate
、複数の金属配線が形成された主面をもつ無機フィラーと熱硬化性榭脂とを含む混 合物からなる第 3の電気絶縁性基板と、 A third electrically insulating substrate made of a mixture containing an inorganic filler having a main surface on which a plurality of metal wires are formed and a thermosetting resin;
前記第 3の電気絶縁性基板内に形成された導電性榭脂組成物が充填されたイン ナービアとを備え、  And an inner via filled with a conductive resin composition formed in the third electrically insulating substrate.
前記半導体チップの素子電極面と前記第 1の電気絶縁性基板の電極端子面との 間に封止榭脂が位置しており、  A sealing resin is located between the element electrode surface of the semiconductor chip and the electrode terminal surface of the first electrically insulating substrate,
前記第 1と第 2の電気絶縁性基板は前記第 3の電気絶縁性基板を介して一体化し ており、  The first and second electrically insulating substrates are integrated via the third electrically insulating substrate,
前記第 1〜第 3の電気絶縁性基板の少なくとも一部の金属配線は前記インナービ ァを介して電気接続されて!ヽる請求項 1に記載の半導体装置。  The semiconductor device according to claim 1, wherein at least a part of metal wiring of the first to third electrically insulating substrates is electrically connected through the inner via.
[7] 前記半導体チップが実装された主面の金属配線において、前記電極端子表面を 含む前記金属配線の一部の表面に金層が形成されており、他の金属配線の表面は 粗化処理されて!、る請求項 1〜6の 、ずれかに記載の半導体装置。  [7] In the metal wiring on the main surface on which the semiconductor chip is mounted, a gold layer is formed on the surface of a part of the metal wiring including the surface of the electrode terminal, and the surface of the other metal wiring is roughened The semiconductor device according to any one of claims 1 to 6, which is !.
[8] 前記金層は、無電解メツキ、電解メツキ、蒸着及びスパッタカも選ばれる少なくとも 一つの手段で形成されている請求項 1〜7のいずれかに記載の半導体装置。  [8] The semiconductor device according to any one of [1] to [7], wherein the gold layer is formed by at least one means also selected from electroless plating, electrolytic plating, vapor deposition, and sputtering.
[9] 前記半導体チップのフリップチップ実装は、 ACF(Anisotropic Conductive Film), A [9] The flip chip mounting of the semiconductor chip can be performed as follows: ACF (Anisotropic Conductive Film), A
CP(Anisotropicし onauctive Paste八 NCF(Non Conductive Film)ゝ NCP(Non Condu ctive Paste)のいずれかを用いた熱圧着工法、又は前記半導体チップの素子電極に 形成された金バンプと前記電気絶縁性基板の電極端子表面に形成された金の超音 波接合によってなされている請求項 2、 5又は 6に記載の半導体装置。 A thermocompression bonding method using either CP (anisotropic and passive paste eight NCF (non conductive film) or NCP (non conductive paste), or a gold bump formed on a device electrode of the semiconductor chip and the electrically insulating substrate The semiconductor device according to claim 2, wherein the semiconductor device is made by ultrasonic bonding of gold formed on the surface of the electrode terminal.
[10] 前記金属配線は、表面が粗ィ匕された銅を含む請求項 1〜9のいずれかに記載の半 導体装置。  [10] The semiconductor device according to any one of claims 1 to 9, wherein the metal wiring contains copper whose surface is roughened.
[11] 前記金属配線表面の粗化の程度は、 JIS B 0601記載の十点平均粗さ Rzにおい て、 1〜10 μ mの範囲である請求項 1〜10のいずれかに記載の半導体装置。 [11] The semiconductor device according to any one of claims 1 to 10, wherein the degree of roughening of the surface of the metal wiring is in a range of 1 to 10 μm in ten-point average roughness Rz described in JIS B 0601. .
[12] 前記第 3の電気絶縁性基板の無機フイラ一は 70重量％〜95重量％の範囲である 請求項 6に記載の半導体装置。 [12] The semiconductor device according to [6], wherein the inorganic filler of the third electrically insulating substrate is in the range of 70% by weight to 95% by weight.
[13] 前記無機フイラ一は、 Al O、 MgO、 BN、 A1N及び SiO力も選ばれる少なくとも [13] The inorganic filler may be selected from Al 2 O, MgO, BN, A 1 N, and SiO forces.
2 3 2 一 つの無機フィラーを含む請求項 6又は 12に記載の半導体装置。  The semiconductor device according to claim 6, wherein the semiconductor device contains one inorganic filler.
[14] 前記熱硬化性榭脂は、エポキシ榭脂、フエノール榭脂及びシァネート榭脂から選ば れる少なくとも一つの熱硬化性榭脂を含む請求項 6又は 12に記載の半導体装置。 [14] The semiconductor device according to claim 6 or 12, wherein the thermosetting resin comprises at least one thermosetting resin selected from epoxy resin, phenol resin and cyanate resin.
[15] 前記導電性榭脂組成物が金、銀、銅及びニッケル力 選ばれる少なくとも一つの金 属を含む金属粒子を導電性成分として含み、エポキシ榭脂を榭脂成分として含む請 求項 6に記載の半導体装置。 [15] The conductive resin composition according to claim 6, wherein the conductive resin composition contains metal particles containing at least one metal selected from gold, silver, copper and nickel as a conductive component, and contains epoxy resin as a resin component. The semiconductor device according to claim 1.
[16] 半導体チップと、前記半導体チップがフリップチップ実装される電極端子を含む複 数の粗化処理された表面の金属配線が形成された主面をもつ電気絶縁性基板とを 準備する工程 (a)と、 [16] a step of preparing a semiconductor chip and an electrically insulating substrate having a main surface on which a plurality of roughened surface metal wires including an electrode terminal on which the semiconductor chip is flip-chip mounted is formed ( a) and
フォトリソグラフィ一法によって、前記電気絶縁性基板の前記半導体チップがフリツ プチップ実装される主面の、前記電極端子以外の部分に、フォトレジストを形成する 工程 (b)と、  Forming a photoresist on a portion other than the electrode terminal on the main surface of the electrically insulating substrate on which the semiconductor chip of the electrically insulating substrate is mounted by a photolithography method;
前記電気絶縁性基板のフリップチップ実装される主面に無電解金メッキを行なって 、前記電極端子表面に金を形成した後、フォトレジストを除去する工程 (c)と、 前記半導体チップの素子電極面と前記電気絶縁性基板の電極端子面との間に封 止榭脂を介して、前記半導体チップを前記電気絶縁性基板にフリップチップ実装す る工程 (d)とを含む半導体装置の製造方法。  Performing electroless gold plating on the main surface of the electrically insulating substrate to be flip chip mounted, forming gold on the surface of the electrode terminal, and then removing a photoresist (c); and an element electrode surface of the semiconductor chip And (d) mounting the semiconductor chip on the electrically insulating substrate via a sealing resin between the electrode terminal surface of the electrically insulating substrate and the electrically insulating substrate.
[17] 半導体チップと、前記半導体チップがワイヤボンディング実装される電極端子を含 む複数の粗化処理された表面の金属配線が形成された主面をもつ電気絶縁性基板 とを準備する工程 (a)と、 [17] A step of preparing a semiconductor chip and an electrically insulating substrate having a main surface on which a plurality of roughened surface metal wires including an electrode terminal on which the semiconductor chip is mounted by wire bonding are formed ( a) and
フォトリソグラフィ一法によって、前記電気絶縁性基板の前記半導体チップがワイヤ ボンディング実装される主面の、前記電極端子以外の部分に、フォトレジストを形成 する工程 (b)と、  Forming a photoresist on a portion other than the electrode terminal on the main surface of the electrically insulating substrate on which the semiconductor chip of the electrically insulating substrate is wire-bonded and mounted;
前記電気絶縁性基板のワイヤボンディング実装される主面に無電解金メッキを行な つて、前記電極端子表面に金を形成した後、フォトレジストを除去する工程 (c)と、 前記半導体チップの素子電極が形成されている面の反対の主面を前記電気絶縁 性基板に接合する工程 (d)と、 Performing electroless gold plating on the main surface of the electrically insulating substrate on which wire bonding is to be mounted, forming gold on the surface of the electrode terminal, and then removing the photoresist (c). Bonding the main surface opposite to the surface on which the device electrode of the semiconductor chip is formed to the electrically insulating substrate (d);
前記半導体チップを前記電気絶縁性基板にワイヤボンディング実装する工程 (e)と 前記半導体チップと前記ワイヤボンディング実装部分を榭脂モールドする工程 (f) とを含む半導体装置の製造方法。  A method of manufacturing a semiconductor device, comprising: (e) mounting the semiconductor chip on the electrically insulating substrate by wire bonding; and (f) resin-molding the semiconductor chip and the wire bonding mounting portion.
[18] 複数の半導体チップが積層された積層半導体チップをワイヤボンディング実装、も しくはフリップチップ実装及びワイヤボンディング実装によって前記電気絶縁性基板 に実装した請求項 16又は 17に記載の半導体装置の製造方法。  [18] The manufacturing of the semiconductor device according to claim 16 or 17, wherein a laminated semiconductor chip in which a plurality of semiconductor chips are laminated is mounted on the electrically insulating substrate by wire bonding mounting or flip chip mounting and wire bonding mounting. Method.
[19] 半導体チップと、前記半導体チップがフリップチップ実装される電極端子を含む複 数の粗化処理された表面の金属配線が形成された主面をもつ第 1の電気絶縁性基 板と、複数の金属配線が形成された主面をもつ第 2の電気絶縁性基板と、無機フイラ 一と熱硬化性榭脂とを含む混合物からなる第 3の電気絶縁性基板である板状体を準 備する工程 (a)と、  [19] A semiconductor chip, and a first electrically insulating substrate having a main surface on which a plurality of roughened surface metal wires including an electrode terminal on which the semiconductor chip is flip-chip mounted is formed; A plate-like body which is a third electrically insulating substrate comprising a second electrically insulating substrate having a main surface on which a plurality of metal wires are formed, and a mixture containing an inorganic filler and a thermosetting resin (A) to prepare
フォトリソグラフィ一法によって、前記第 1の電気絶縁性基板の前記半導体チップが フリップチップ実装される主面の、前記電極端子以外の部分に、フォトレジストを形成 する工程 (b)と、  Forming a photoresist on a portion other than the electrode terminal on the main surface of the first electrically insulating substrate on which the semiconductor chip of the first electrically insulating substrate is flip-chip mounted;
前記第 1の電気絶縁性基板のフリップチップ実装される主面に無電解金メッキを行 なって、前記電極端子表面に金を形成した後、フォトレジストを除去する工程 (c)と、 前記半導体チップの素子電極面と前記電気絶縁性基板の電極端子面との間に封 止榭脂を介して、前記半導体チップを前記電気絶縁性基板にフリップチップ実装す る工程 (d)と、  Performing electroless gold plating on the main surface of the first electrically insulating substrate to be flip chip mounted, forming gold on the surface of the electrode terminal, and then removing the photoresist (c); and the semiconductor chip And (d) mounting the semiconductor chip on the electrically insulating substrate via a sealing resin between the element electrode surface of the electrically insulating substrate and the electrode terminal surface of the electrically insulating substrate.
前記板状体に貫通孔を形成し、前記貫通孔に導電性榭脂組成物からなる導電性 ペーストを充填する工程 (e)と、  Forming a through hole in the plate-like body, and filling the through hole with a conductive paste made of a conductive resin composition (e);
前記第 1と第 2の電気絶縁性基板及び前記板状体を、前記板状体の一方の主面に 前記第 1の電気絶縁性基板の前記半導体チップがフリップチップ実装された主面が 向くように、もう一方の主面に前記第 2の電気絶縁性基板の金属配線が形成された 主面が向くように位置あわせし、積層する工程 (f)と、 加熱加圧して、前記第 1と第 2の電気絶縁性基板を前記板状体に接着し、前記半 導体チップを前記板状体に埋設して一体化し、前記板状体及び前記導電性榭脂組 成物からなる導電性ペーストを硬化させる工程 (g)とを含む半導体装置の製造方法。 The main surface of the first electrically insulating substrate on which the semiconductor chip of the first electrically insulating substrate is flip chip mounted is directed to the first and second electrically insulating substrates and the plate-like body on one main surface of the plate-like body And aligning and laminating so that the main surface of the second electrically insulating substrate is formed on the other main surface, and laminating (f). Heat and pressure are applied to bond the first and second electrically insulating substrates to the plate, and the semiconductor chip is embedded in the plate so as to be integrated, and the plate and the conductive foil And (g) curing the conductive paste composed of the oil composition.
[20] 前記電極端子表面の金の形成方法は、電解メツキ、蒸着又はスパッタである請求 項 16〜19のいずれかに記載の半導体装置の製造方法。  [20] The method of manufacturing a semiconductor device according to any one of claims 16 to 19, wherein a method of forming gold on the surface of the electrode terminal is electrolytic plating, vapor deposition or sputtering.
[21] 前記第 3の電気絶縁性基板は、前記無機フィラーと熱硬化性榭脂とを含む混合物 からなる請求項 19に記載の半導体装置の製造方法。  21. The method for manufacturing a semiconductor device according to claim 19, wherein the third electrically insulating substrate is made of a mixture containing the inorganic filler and a thermosetting resin.
PCT/JP2006/304443 2005-03-23 2006-03-08 Semiconductor device and method for manufacturing same WO2006100909A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006526475A JPWO2006100909A1 (en) 2005-03-23 2006-03-08 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005084656 2005-03-23
JP2005-084656 2005-03-23

Publications (1)

Publication Number Publication Date
WO2006100909A1 true WO2006100909A1 (en) 2006-09-28

Family

ID=37023583

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2006/304443 WO2006100909A1 (en) 2005-03-23 2006-03-08 Semiconductor device and method for manufacturing same

Country Status (4)

Country Link
JP (1) JPWO2006100909A1 (en)
KR (1) KR20070117991A (en)
CN (1) CN1943029A (en)
WO (1) WO2006100909A1 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008198712A (en) * 2007-02-09 2008-08-28 Toppan Printing Co Ltd Circuit board with built-in electronic component, electronic module, electronic apparatus, and method for manufacturing circuit board with built-in electronic component
JP2008235898A (en) * 2007-03-19 2008-10-02 Infineon Technologies Ag Power semiconductor module, method for producing power semiconductor module, and semiconductor chip
JP2010258277A (en) * 2009-04-27 2010-11-11 Dainippon Printing Co Ltd Wiring board with built-in component
JP2010267845A (en) * 2009-05-15 2010-11-25 Dainippon Printing Co Ltd Component built-in wiring board and method of manufacturing the component built-in wiring board
JP2013021370A (en) * 2012-10-29 2013-01-31 Dainippon Printing Co Ltd Component built-in wiring board
US11810721B2 (en) * 2021-02-05 2023-11-07 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8358002B2 (en) * 2009-12-23 2013-01-22 Marvell World Trade Ltd. Window ball grid array (BGA) semiconductor packages
EP3796402A1 (en) * 2013-07-24 2021-03-24 Epistar Corporation Light-emitting dies incorporating wavelength-conversion materials and related methods
KR102207273B1 (en) * 2014-01-29 2021-01-25 삼성전기주식회사 Package substrate
CN105826295B (en) * 2015-01-07 2019-01-29 中芯国际集成电路制造(上海)有限公司 Interconnection structure and forming method thereof
KR101971493B1 (en) * 2017-09-29 2019-04-23 서울과학기술대학교 산학협력단 Ag-coated Cu pillar bonding structure and bonding method using the Ag-coated Cu pillars
TWI646877B (en) * 2018-03-12 2019-01-01 Chipbond Technology Corporation Wiring circuit structure of flexible circuit board
CN113594151B (en) * 2021-06-25 2024-05-14 苏州汉天下电子有限公司 Semiconductor package and method of manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11214446A (en) * 1998-01-27 1999-08-06 Matsushita Electric Ind Co Ltd Electronic part manufacturing method
JP2001332663A (en) * 2000-05-24 2001-11-30 Mitsui High Tec Inc Binder for mounting flip chip and manufacturing method for semiconductor device using the same
JP2002261449A (en) * 2000-12-27 2002-09-13 Matsushita Electric Ind Co Ltd Module with built-in component and its manufacturing method
JP2003303937A (en) * 2002-04-05 2003-10-24 Nec Electronics Corp Semiconductor device and manufacturing method thereof
JP2005039227A (en) * 2003-07-03 2005-02-10 Matsushita Electric Ind Co Ltd Module with built-in semiconductor, and its manufacturing method

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000236037A (en) * 1999-02-15 2000-08-29 Sumitomo Metal Mining Co Ltd Solder resist forming method
JP2001313314A (en) * 2000-04-28 2001-11-09 Sony Corp Semiconductor device using bump, its manufacturing method, and method for forming bump
JP2002184811A (en) * 2000-12-11 2002-06-28 Sony Corp Electronic circuit device and its manufacturing method
JP3687610B2 (en) * 2002-01-18 2005-08-24 セイコーエプソン株式会社 Semiconductor device, circuit board, and electronic equipment
JP4318886B2 (en) * 2002-04-25 2009-08-26 シャープ株式会社 Protrusion electrode bonded semiconductor device and manufacturing method thereof
JP2004193392A (en) * 2002-12-12 2004-07-08 Matsushita Electric Ind Co Ltd Circuit component incorporating module and its manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11214446A (en) * 1998-01-27 1999-08-06 Matsushita Electric Ind Co Ltd Electronic part manufacturing method
JP2001332663A (en) * 2000-05-24 2001-11-30 Mitsui High Tec Inc Binder for mounting flip chip and manufacturing method for semiconductor device using the same
JP2002261449A (en) * 2000-12-27 2002-09-13 Matsushita Electric Ind Co Ltd Module with built-in component and its manufacturing method
JP2003303937A (en) * 2002-04-05 2003-10-24 Nec Electronics Corp Semiconductor device and manufacturing method thereof
JP2005039227A (en) * 2003-07-03 2005-02-10 Matsushita Electric Ind Co Ltd Module with built-in semiconductor, and its manufacturing method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008198712A (en) * 2007-02-09 2008-08-28 Toppan Printing Co Ltd Circuit board with built-in electronic component, electronic module, electronic apparatus, and method for manufacturing circuit board with built-in electronic component
JP2008235898A (en) * 2007-03-19 2008-10-02 Infineon Technologies Ag Power semiconductor module, method for producing power semiconductor module, and semiconductor chip
JP2010258277A (en) * 2009-04-27 2010-11-11 Dainippon Printing Co Ltd Wiring board with built-in component
JP2010267845A (en) * 2009-05-15 2010-11-25 Dainippon Printing Co Ltd Component built-in wiring board and method of manufacturing the component built-in wiring board
JP2013021370A (en) * 2012-10-29 2013-01-31 Dainippon Printing Co Ltd Component built-in wiring board
US11810721B2 (en) * 2021-02-05 2023-11-07 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component

Also Published As

Publication number Publication date
KR20070117991A (en) 2007-12-13
JPWO2006100909A1 (en) 2008-09-04
CN1943029A (en) 2007-04-04

Similar Documents

Publication Publication Date Title
WO2006100909A1 (en) Semiconductor device and method for manufacturing same
KR100987688B1 (en) Printed wiring board and method for manufacturing printed wiring board
EP2172089B1 (en) Method for manufacturing a multilayer wiring element having pin interface
US9226382B2 (en) Printed wiring board
US7705446B2 (en) Package structure having semiconductor chip embedded therein and method for fabricating the same
TWI645567B (en) Semiconductor device and method for manufacturing semiconductor device
TWI247373B (en) Semiconductor package having semiconductor constructing body and method of manufacturing the same
US7390692B2 (en) Semiconductor device and method for manufacturing the same
US8288865B2 (en) Semiconductor module having semiconductor device mounted on device mounting substrate
US20030127725A1 (en) Metal wiring board, semiconductor device, and method for manufacturing the same
EP1906446A2 (en) Semiconductor device and manufacturing method thereof
KR20070032702A (en) Manufacturing method of semiconductor device, substrate for semiconductor device manufacturing and substrate for semiconductor device manufacturing
JP4242777B2 (en) CONNECTION BOARD, MULTILAYER WIRING BOARD, SEMICONDUCTOR PACKAGE BOARD AND SEMICONDUCTOR PACKAGE USING THE CONNECTION SUBSTRATE, AND MANUFACTURING METHOD THEREOF
JP4449975B2 (en) Connection board, multilayer wiring board using the connection board, and methods of manufacturing the same
US7964493B2 (en) Method of manufacturing semiconductor device
JP5081267B2 (en) Circuit component built-in module and method for manufacturing circuit component built-in module
JP2004172597A (en) Semiconductor device and its manufacturing method
CN101383329B (en) Package construction embedded with chip and preparation thereof
JPH10335528A (en) Semiconductor package and manufacture thereof
JP2009004813A (en) Wiring substrate for mounting semiconductor
US6495771B2 (en) Compliant multi-layered circuit board for PBGA applications
CN108305864B (en) Terminal with a terminal body
US9673063B2 (en) Terminations
JP4231229B2 (en) Semiconductor package
JP2004266271A (en) Electronic part mounting body and method for manufacturing the same

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 2006526475

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 1020067019136

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 200680000125.8

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

NENP Non-entry into the national phase

Ref country code: RU

122 Ep: pct application non-entry in european phase

Ref document number: 06728762

Country of ref document: EP

Kind code of ref document: A1