CN113594151B - Semiconductor package and method of manufacturing the same - Google Patents

Semiconductor package and method of manufacturing the same Download PDF

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Publication number
CN113594151B
CN113594151B CN202110714994.3A CN202110714994A CN113594151B CN 113594151 B CN113594151 B CN 113594151B CN 202110714994 A CN202110714994 A CN 202110714994A CN 113594151 B CN113594151 B CN 113594151B
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Prior art keywords
substrate
semiconductor package
chip
structures
chips
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CN113594151A (en
Inventor
郜振豪
杨清华
唐兆云
赖志国
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Suzhou Huntersun Electronics Co Ltd
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Suzhou Huntersun Electronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Led Device Packages (AREA)

Abstract

The invention provides a semiconductor package and a method for manufacturing the same, comprising: a substrate including a plurality of barrier structures surrounding the chip mounting region; the chip is flip-chip welded on the chip mounting area; a first sealant covering the chip on the chip mounting region; and a second sealant coating the first sealant on the substrate. According to the semiconductor package and the method of manufacturing the same of the present invention, a barrier structure is used around each chip on a substrate to prevent moisture penetration, enhance adhesion, and simultaneously prevent sealant from overflowing, thereby effectively improving reliability of the package.

Description

Semiconductor package and method of manufacturing the same
Technical Field
The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package capable of effectively preventing moisture from penetrating and preventing an encapsulant from overflowing, and a method of manufacturing the same.
Background
The rapid development of microelectronic technology, the increase in complexity of integrated circuits, and the potential for integration of a large portion of the functionality of an electronic system into a single chip (i.e., a system-on-a-chip) has correspondingly required microelectronic packages with higher performance, more leads, denser interconnects, smaller size or larger chip cavities, greater heat dissipation capabilities, better electrical performance, higher reliability, lower cost per lead, etc.
With the recent trend of semiconductor technology, wafer process technology is also being improved to meet the demands of the semiconductor industry. On the other hand, due to the continuous improvement of wafer process technology, the conventional package testing technology is gradually eliminated from the market, so that the package testing technology is also improved to cope with the change of the semiconductor industry.
Specifically, in the prior art, more than one semiconductor component, especially different kinds of chips, such as a memory chip and a logic control chip, a light emitting chip (LED, laser, etc.) and a light sensor chip (photodiode, etc.), a digital IC and an analog IC, and an active device and a passive device (e.g., R, L, C networks, etc.), are often mounted in the same semiconductor package. These components operate under different application conditions, and there are different demands on the package performance, so that different performance sealants need to be used in the same package.
In device warm and humid environment reliability experiments performed on these packages, moisture penetration is one of the important reasons for failure due to the influence of its air tightness. Moisture penetration into the device has two main pathways: the body of the layer is encapsulated by plastic package material or the gap between the plastic package material encapsulation layer and the package substrate. In the above-mentioned conventional packaging technology, due to the difference in the chip mounting process, the existing sealant used for one chip is extremely susceptible to temperature and pressure during the subsequent packaging of other chips, and thus the adhesion between the sealant and the substrate is reduced, and moisture is liable to intrude from these cracks, thereby failing the semiconductor element. In addition, the flow properties of different encapsulants are different, and the previous encapsulant is susceptible to overflow by the subsequent sealing process, and the flowing encapsulant may cause contamination or shielding of pads on the substrate where the chip is not yet mounted, affecting the interconnection reliability of subsequent semiconductor elements.
Disclosure of Invention
Accordingly, an object of the present invention is to provide an innovative semiconductor package and a method of manufacturing the same, which overcome the above technical obstacles, and which prevent moisture penetration, enhance adhesion, and simultaneously prevent sealant from overflowing, using a barrier structure around each chip on a substrate, thereby effectively improving the reliability of the package.
The present invention provides a semiconductor package, comprising:
a substrate including a plurality of barrier structures surrounding the chip mounting region;
the chip is flip-chip welded on the chip mounting area;
A first sealant covering the chip on the chip mounting region;
and a second sealant coating the first sealant on the substrate.
Wherein the chip comprises a plurality of chips of the same or different types, and a plurality of blocking structures surrounds each chip. Wherein different additives are added to the inner or surface of the plurality of barrier structures around the plurality of chips of different types, or different additives are added to the first encapsulant on the plurality of chips of different types. Wherein the additive comprises conductive particles, colored particles, reflective particles, chemical modifiers, refractory particles, high hardness particles, wavelength conversion particles, or thermally conductive particles.
The plurality of barrier structures are rough surfaces or concave-convex structures processed on the surface of the substrate or dam structures formed on the surface of the substrate.
The plurality of barrier structures are periodic or non-periodic structures with a level of thickness on the normal line of the substrate, or curve distribution structures with a height difference on the normal line of the substrate.
The blocking structures are line segments or curves parallel to each other in a plan view, or grids formed by crosslinking the line segments or the curves.
Wherein, in plan view, the chip or the first encapsulant partially overlaps the plurality of barrier structures.
The invention further provides a semiconductor package manufacturing method, comprising the steps of:
Forming a plurality of barrier structures on the substrate surrounding the one or more chip mounting regions;
Flip-chip mounting one or more chips on one or more chip mounting regions of a substrate;
Forming one or more first encapsulants within the one or more die mounting areas to cover the one or more dies;
A second sealant is formed on the substrate to cover all of the first sealant.
Wherein the plurality of barrier structures have a thickness of 10 to 100 microns.
According to the semiconductor package and the method of manufacturing the same of the present invention, a barrier structure is used around each chip on a substrate to prevent moisture penetration, enhance adhesion, and simultaneously prevent sealant from overflowing, thereby effectively improving reliability of the package.
The stated objects of the application, as well as other objects not listed herein, are met within the scope of the independent claims of the present application. Embodiments of the application are defined in the independent claims and specific features are defined in the dependent claims thereof.
Drawings
The technical solution of the present invention is described in detail below with reference to the attached drawings, wherein:
fig. 1 shows a cross-sectional view of a semiconductor package according to one embodiment of the invention;
FIG. 2 shows a plan view of a substrate surface in the semiconductor package of FIG. 1;
Fig. 3 shows a cross-sectional view of a semiconductor package according to another embodiment of the present invention;
FIG. 4 shows a plan view of a substrate surface in the semiconductor package of FIG. 3; and
Fig. 5 shows a flowchart of a semiconductor package manufacturing method according to an embodiment of the present invention.
Detailed Description
The features and technical effects of the technical scheme of the present application are described in detail below with reference to the accompanying drawings in combination with the exemplary embodiments, and a semiconductor package and a method of manufacturing the same are disclosed which effectively improve package reliability. It should be noted that like reference numerals refer to like structures and that the terms "first," "second," "upper," "lower," and the like as used herein may be used to modify various device structures. These modifications, unless specifically stated, do not imply a spatial, sequential, or hierarchical relationship to the modified device structures.
As shown in fig. 1 and 2, a semiconductor package according to a preferred embodiment of the present invention includes a substrate 1, one or more chips 2, a first encapsulant 6A, and a second encapsulant 6B. The substrate 1 is, for example, a Printed Circuit Board (PCB) including a plurality of insulating layers made of an organic (e.g., resin) or inorganic material, a metal interconnection layer or rewiring layer (RDL) provided between the respective insulating layers as required for wiring, and a plurality of pads 1B on the top surface of the substrate. In addition, the substrate 1 may also be a lead frame (LEAD FRAME) with metal traces and pads on the top surface of the traces that are encapsulated by an encapsulant.
The chip 2 may be various commonly used semiconductor chips such as silicon-based logic/memory circuits manufactured based on CMOS processes, power devices manufactured based on bipolar or BiMOS processes, light Emitting Diodes (LEDs) or photodiodes (LD) based on III-V or II-VI compounds, etc. The bottom of the chip 2 comprises a plurality of metal traces or pads 3, for example made of Al, cu, mo, W, pt, ni and alloys thereof, which serve as electrical signal input/output inside the chip 2.
The suction nozzle is used for coring from the wafer and simultaneously pasting the bumps 4 of the chip on the chip mounting area or the substrate welding area. Specifically, metal bumps (bumps) 4, preferably Cu, sn, al, ag, ni, au, pt, pd and alloys thereof, are provided on the pads 3 of the chip 2 by electroplating, electroless plating, bonding, pressing, conductive adhesive bonding, etc. processes for providing sufficient mechanical support during flip-chip reflow of the chip 2, avoiding solder ball displacement, and at the same time, solderable materials are also preferred to promote bond strength with solder balls. The metal bump 4 is formed with a solder ball 5, and the solder ball 5 is in contact with and soldered to the pad 1B on the surface of the substrate 1, thereby realizing physical connection and electrical connection. The metal bumps 4 are generally circular in cross-section so that the solder balls 5 are evenly distributed over the bump surface during reflow without overflowing from sharp corners or protrusions to the sidewalls. The material of the solder balls 5 may be lead-containing solder or lead-free solder. Preferably, a soldering flux or a solder paste (not shown) may be further provided between the solder balls 5 and the top surface pads 1B of the substrate 1, so as to improve the reliability of soldering with the substrate.
In the case of a semiconductor package including a plurality of chips 2 of different kinds, the sealing environment required for each chip 2 may be different, and for example, chips such as LEDs, LDs, etc. have high requirements for optical functions such as transmittance, wavelength conversion, etc. of the sealant, and control logic, memories have high requirements for permeation resistance and electromagnetic interference resistance of the sealant, so that it is necessary to sequentially seal with the same kind of sealant after the same kind of chip is mounted, and then to seal with another kind of sealant in batch for another kind of chip. In this process, the bonding pad 1B on the substrate is easily contaminated or shielded due to the different fluidity of the sealant, and the subsequent process is also easily caused by the peeling-off of the previous sealant due to the different thermal stability of the sealant.
For this reason, in the present application, during the step of providing the substrate 1 before the mounting of the chip 2, a plurality of barrier structures 1A are provided at least at the periphery of each chip mounting region for enhancing the adhesion between the substrate and the sealant to prevent the sealant from peeling off, and the penetration of moisture from the interface gap between the package and the substrate can be effectively reduced. In addition, the blocking structure 1A can also prevent the sealant from overflowing outwards, can effectively ensure that the substrate pad is not affected, and ensures the reliability of the electrical interconnection.
The plurality of barrier structures 1A may be, for example, rough surfaces or uneven structures formed directly on the substrate 1 by a subtractive process such as mechanical dicing or laser ablation, or dam structures formed by an additive process of coating or printing a barrier material (for example, an epoxy resin) on the flat surface of the substrate 1. As shown in fig. 1, the plurality of barrier structures 1A may have a thickness (e.g., less than 5% of the thickness of the encapsulant 6A, such as 10 to 100 microns and preferably 20 to 70 microns, in a normal line view, and may be substantially horizontal periodic or non-periodic structures, although shown in fig. 1 as substantially horizontal stripe-like structures, in a normal line direction, such as a center bump with two side bumps, two side bumps with a center bump, or a portion of the bump and another portion of the bump alternating various curved profiles, thereby enhancing moisture barrier capability by effectively extending the moisture permeation path length, while as shown in fig. 2, the plurality of barrier structures 1A surround at least the die mounting area (shown in the box outside the bonding pad 1B in the figure, corresponding to the encapsulant 6A profile area in fig. 1), and may be substantially horizontal linear or curved segments or periodic or non-periodic structures formed therefrom, such as an array, preferably, such that the plurality of barrier structures 1A are distributed at the edge of the substrate 1A so as to effectively extend the moisture permeation path length, thereby further overlapping the encapsulant 1A to the first side surface (shown in fig. 2), and thus extending the moisture barrier structures 1A further from the side surface to the encapsulant 6A) by a distance equal to, preferably less than 50% from the first side of the encapsulant 6A (shown in fig. 1), the peeling problem that may exist for the different kinds of the first sealing agent 6A during the different processes is avoided.
Preferably, in order to meet the individualization requirements of the different kinds of chips 2 for packaging, additives can also be added to the inside or on the surface of the plurality of barrier structures 1A: conductive particles such as graphite powder, graphene fragments, silver powder and the like are added to form a grounding loop in order to effectively improve the electromagnetic interference resistance; in order to prevent light leakage from the side or bottom of the top-emission type LED, colored particles such as melanin, dye and the like are added to form a light absorption layer, or reflective particles such as silver powder, magnesium powder, zinc oxide, titanium oxide and the like are added to form a reflective layer so as to improve the light-emitting efficiency of the bottom-emission type LED or the side-emission type LED; in order to improve the bonding strength between the substrate and the sealant, a proper cross-linking agent, coupling agent or surface modifier can be selected for the organic insulating material adopted by the substrate and the organic insulating material adopted by the sealant, and a cross-linked molecular chain is generated between the substrate and the sealant; to improve heat resistance or pressure resistance, refractory particles or high hardness particles such as zirconia, titania, manganese oxide, ceria, or the like may be added.
After flip-chip mounting of the chip 2, the chip 2 is fixed on the substrate by applying the first encapsulant 6A by a low or normal temperature process such as spin coating, spray coating, screen printing, etc., completely encapsulating the chip 2, the pads 3, the bumps 4 and the solder balls 5, and simultaneously covering the pads 1B on the substrate 1 (and preferably partially covering a portion of the plurality of barrier structures 1A on the substrate 1). The first sealant 6A may be various encapsulating organic materials commonly used, such as epoxy resin, phenolic resin, amide resin, polyester resin, and the like. Preferably, in order to meet the individual requirements of the different kinds of chips 2 for packaging, different additives are added into the first encapsulant 6A on the different chips 2: conductive particles are added to combat electromagnetic interference, wavelength converting particles (organic dyes or pigments, quantum dots, phosphors or fluorophores, etc.) are added to alter the color of the LED emitted light, thermally conductive particles (insulating thermally conductive ceramic particles such as alumina, aluminum nitride, titanium nitride, etc.) are added to improve heat dissipation, colored or reflective particles are added to alter the LED optical properties, etc.
After the flip-chip bonding of the respective semiconductor chips 2 is completed, the second sealant 6B is applied on the entire substrate 1, completely covering the remaining area of the substrate 1 and all of the first sealant 6A, and the final semiconductor package is completed. Preferably, the width of the barrier structure 1A covered by the second sealant 6B is 5 times or more and 30 times or less of the width of the barrier structure 1A covered by the first sealant 6A, so that the bonding strength between the second sealant 6B as a whole and the substrate 1 is effectively enhanced and the stress distribution at the interface between the first sealant 6A and the second sealant 6B is coordinated, and the peeling phenomenon possibly existing at the interface between the two is prevented.
And then, according to the electrical function realized by the packaging structure, dicing and separating each packaging body into semi-finished products by adopting mechanical saw blade cutting or laser scanning cutting, and performing reliability tests such as environment temperature-humidity-like/bias voltage tests on each semi-finished product to select qualified products to finish final finished product packaging. In this process, it is preferable to use a plurality of barrier structures as dicing areas, since the barrier structures have various additives according to the requirements of the sealant 6A, which effectively reduce damage at dicing cuts, ensuring reliability of the package.
Fig. 3, 4 show a cross-sectional view and a top view of a semiconductor package according to a further embodiment of the invention, wherein a substrate 1 has a plurality of semiconductor chips 2 thereon, each semiconductor chip 2 being surrounded by a respective first encapsulant 6A, while a second encapsulant 6B covers all of the first encapsulant 6A and the remaining substrate 1, wherein a plurality of barrier structures 1A are distributed not only over the peripheral edges of the substrate 1 but also over the substrate 1 between the respective semiconductor chips 2 so as to enclose the respective semiconductor chips 2 in a plan view.
As shown in fig. 5, the method of manufacturing a semiconductor package according to the above preferred embodiment of the present invention includes the steps of:
forming a plurality of barrier structures surrounding the chip mounting region(s) on the substrate 1;
Flip-chip(s) 2 on substrate 1;
Forming a first encapsulant 6A(s) inside the plurality of barrier structures 1A of the substrate 1 on the chip 2;
the second sealing agent 6B is formed on the substrate 1 and (all) the first sealing agent 6A.
According to the semiconductor package and the method of manufacturing the same of the present invention, a barrier structure is used around each chip on a substrate to prevent moisture penetration, enhance adhesion, and simultaneously prevent sealant from overflowing, thereby effectively improving reliability of the package.
While the invention has been described with reference to one or more exemplary embodiments, it will be understood by those skilled in the art that various suitable changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings disclosed without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the device structure and method of making the same will include all embodiments falling within the scope of the present invention.

Claims (9)

1. A semiconductor package, comprising:
a substrate comprising a plurality of barrier structures surrounding one or more chip mounting regions;
One or more chips flip-chip bonded to the one or more chip mounting regions;
A first encapsulant encapsulating the chip over the one or more chip mounting regions;
A second sealant covering the remaining area of the substrate and all of the first sealant;
And a plurality of blocking structures between the second sealant and the substrate and surrounding each chip, wherein additives including conductive particles are added into or on the surfaces of the plurality of blocking structures to form a grounding loop, and no blocking structure is arranged between the first sealant and the substrate.
2. The semiconductor package of claim 1, wherein the plurality of chips comprises a plurality of chips of the same or different types.
3. The semiconductor package of claim 2, wherein different additives are added to the inner or surface of the plurality of barrier structures around the plurality of chips of different types or to the first encapsulant on the plurality of chips of different types.
4. A semiconductor package according to claim 3, wherein the different additives added to the first encapsulant on the plurality of chips of different types are colored particles, reflective particles, chemical modifiers, refractory particles, high hardness particles, wavelength conversion particles, or thermally conductive particles.
5. The semiconductor package according to claim 1, wherein the plurality of barrier structures are rough surfaces or uneven structures processed on the surface of the substrate, or dam structures formed on the surface of the substrate.
6. The semiconductor package of claim 1, wherein the plurality of barrier structures are periodic or non-periodic structures having a level of thickness on a normal line of the substrate or are curvilinear distribution structures having a height difference on a normal line of the substrate.
7. The semiconductor package of claim 1, wherein the plurality of barrier structures have a thickness of 10 to 100 microns.
8. A method of manufacturing a semiconductor package, comprising the steps of:
Forming a plurality of barrier structures on the substrate surrounding the one or more chip mounting regions, wherein additives including conductive particles are added to the plurality of barrier structures to form a ground loop;
Flip-chip mounting one or more chips on one or more chip mounting regions of a substrate;
forming a first encapsulant to cover the one or more chips in the one or more chip mounting regions, wherein no barrier structure is provided between the first encapsulant and the substrate;
a second encapsulant is formed over the substrate, covering the remaining area of the substrate and all of the first encapsulant, and a plurality of barrier structures are located between the second encapsulant and the substrate and surrounding each of the chips.
9. The method for manufacturing a semiconductor package according to claim 8, wherein after the second sealing agent is formed, the individual chips are cut and separated using a part of the plurality of barrier structures as a dicing area.
CN202110714994.3A 2021-06-25 2021-06-25 Semiconductor package and method of manufacturing the same Active CN113594151B (en)

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