CN112531084A - LED chip, LED chip packaging module and display device - Google Patents

LED chip, LED chip packaging module and display device Download PDF

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Publication number
CN112531084A
CN112531084A CN202011282176.2A CN202011282176A CN112531084A CN 112531084 A CN112531084 A CN 112531084A CN 202011282176 A CN202011282176 A CN 202011282176A CN 112531084 A CN112531084 A CN 112531084A
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China
Prior art keywords
conductive
led chip
layer
width
mesa structure
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CN202011282176.2A
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CN112531084B (en
Inventor
刘士伟
徐瑾
刘可
王水杰
张中英
曾合加
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Xiamen Sanan Optoelectronics Technology Co Ltd
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Xiamen Sanan Optoelectronics Technology Co Ltd
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Priority to CN202210535067.XA priority Critical patent/CN115000261A/en
Priority to CN202210535064.6A priority patent/CN115000265A/en
Priority to CN202210535471.7A priority patent/CN114824011A/en
Priority to CN202210535435.0A priority patent/CN114914340A/en
Priority to CN202011282176.2A priority patent/CN112531084B/en
Application filed by Xiamen Sanan Optoelectronics Technology Co Ltd filed Critical Xiamen Sanan Optoelectronics Technology Co Ltd
Publication of CN112531084A publication Critical patent/CN112531084A/en
Priority to US17/454,895 priority patent/US20220158028A1/en
Priority to KR1020210156854A priority patent/KR20220066851A/en
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Publication of CN112531084B publication Critical patent/CN112531084B/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22Roughened surfaces, e.g. at the interface between epitaxial layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
    • H01L33/145Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure with a current-blocking structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46Reflective coating, e.g. dielectric Bragg reflector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B20/00Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
    • Y02B20/30Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)

Abstract

LED chip, LED chip encapsulation module and display device. The LED chip includes: a substrate, a first mesa structure, and a second mesa structure; at least one cross-over current block; the number of the cross-over conductive blocks is the same as that of the cross-over current blocking blocks; a first conductive pad and a second conductive pad; the top view projection of the cross-over current block has a head and a tail; the planar projection of the bridging conductive block is provided with a first contact part, a junction part and a second contact part; the knot portion is within the head portion and the first contact portion is within the tail portion; the portion of the head portion not overlapping the junction portion has a first width, and the portion of the tail portion not overlapping the first contact portion has a second width, the first width being greater than the second width. The reliability of the LED chip is improved.

Description

LED chip, LED chip packaging module and display device
Technical Field
The invention relates to the field of LEDs, in particular to an LED chip, an LED chip packaging module and a display device.
Background
The LED (light emitting diode) has the advantages of low cost, high lighting effect, energy conservation, environmental protection and the like, and is widely applied to scenes such as illumination, visible light communication, luminous display and the like.
One development direction of the LED is towards miniaturization and microminiaturization, and the LED forms an array with millimeter-level and even micron-level spacing after being miniaturized, so that ultrahigh resolution can be achieved, and the LED can be more widely applied to the fields of information display and the like. Compared with Liquid Crystal Display (LCD) and Organic Light Emitting Display (OLED), LED has the advantages of long light emitting life, high brightness, thin volume, low power consumption, high pixel density, and the like, and thus, it is one of the representatives of the third generation display technologies featuring high degree of reality, interaction, and personalized display.
At present, in the development process of LED chips toward miniaturization, one of the problems encountered is reliability, that is, the industry is faced with the situation that the corresponding LED chip structure needs to be optimized to improve the reliability of the product.
Disclosure of Invention
The invention aims to provide an LED chip, an LED chip packaging module and a display device so as to improve the reliability of products.
To solve the above problems, the present invention provides an LED chip, comprising: a substrate; a first mesa structure on the substrate; a second mesa structure on the substrate; at least one crossover current block covering a portion of the upper surface and a portion of the side surfaces of the first mesa structure and covering a portion of the recess between the first and second mesa structures; the number of the cross-over conductive blocks is the same as that of the cross-over current blocking blocks, the main body part of the cross-over conductive block is positioned on the cross-over current blocking blocks, the first ends of the cross-over conductive blocks are electrically connected with the top layer of the first mesa structure, and the second ends of the cross-over conductive blocks are electrically connected with the bottom layer of the second mesa structure; a first conductive pad located over the first mesa structure; a second conductive pad located above the second mesa structure; the top view projection of the cross-over current block has a head and a tail; the planar projection of the bridging conductive block is provided with a first contact part, a junction part and a second contact part; the knot portion is within the head portion and the first contact portion is within the tail portion; the portion of the head portion not overlapping the junction portion has a first width, and the portion of the tail portion not overlapping the first contact portion has a second width, the first width being greater than the second width.
Optionally, the first width is 3 μm to 100 μm in size.
Optionally, the second width is greater than or equal to 0 μm and less than or equal to 30 μm in size.
Optionally, the width of the head portion is more than 1.5 times the width of the tail portion.
Optionally, the number of the bridging conductive blocks is two, and the bridging conductive blocks are respectively located at two opposite edges of the whole overlooking projection area.
Optionally, a top view projection of the bridging conductive block does not overlap with a top view projection of the first conductive pad and the second conductive pad.
Optionally, a portion of the top projection of the second conductive pad is sandwiched between the two bridging conductive blocks, and the top shape of the first conductive pad and the top shape of the second conductive pad are substantially symmetrical.
Optionally, the width of the junction is greater than the width of the first contact portion; the width of the junction portion is greater than the width of the second contact portion.
Optionally, a bisector of the junction and a bisector of the first contact portion coincide with each other on a first straight line, the bisector of the second contact portion is a second straight line, the first straight line is parallel to the second straight line, and the second contact portion is connected to an outer corner of the junction; or the bisector of the junction and the bisector of the second contact part are superposed on a first straight line, the bisector of the first contact part is a second straight line, the first straight line is parallel to the second straight line, and the first contact part is connected with the inner corner of the junction.
Optionally, the LED chip further includes: a first current spreading layer located over the first mesa structure, the first conductive pad located over the first current spreading layer, the cross-over conductive block electrically connected to a top layer of the first mesa structure by connecting the first current spreading layer; a second current spreading layer over the second mesa structure, the second conductive pad over the second current spreading layer; the top projection of the bridging conductive block and the top projection of the second current spreading layer have no overlapping part.
Optionally, the LED chip further includes a first DBR reflective layer, the first DBR reflective layer covering the first current spreading layer and the second current spreading layer; the first conductive pad is located on the first DBR reflective layer, and the first conductive pad penetrates through the first DBR reflective layer to electrically connect to a bottom layer of the first mesa structure; the second conductive pad is located on the first DBR reflective layer and extends through the first DBR reflective layer to electrically connect the second current spreading layer; the first DBR reflective layer also serves as a passivation protection layer.
Optionally, the LED chip further includes a built-in current blocking block, the built-in current blocking block and the cross-over current blocking block are in the same layer structure, and the built-in current blocking block is located between the second mesa structure and the second current spreading layer; the top-view projection of the built-in current block comprises a middle part and two side parts connecting the middle part, and the width of the middle part is larger than that of the side parts.
Optionally, the LED chip further includes a first conductive block, and the first conductive block and the bridging conductive block are in the same layer structure; the top projection of the top layer of the first table-board structure is provided with an inward concave notch, and the top projection of the first conductive block is arranged in the inward concave notch of the first table-board structure.
Optionally, the top projection of the top layer of the second mesa structure is a chamfered rectangle with two corner notches, the corner notches face the first mesa structure, and the two corner notches are symmetrical; the corner gap is matched with the bridging conductive block.
Optionally, the overlooking projection of the concave notch is funnel-shaped, and the overlooking projection of the first conductive block is round or nail-shaped with a round head.
Optionally, the LED chip further includes a second conductive block, the second conductive block and the cross-over conductive block are in a same layer structure, the second conductive block is located above the built-in current blocking block and on the second current spreading layer, and the second conductive pad is electrically connected to the second current spreading layer by being connected to the second conductive block; a top view projection of the second conductive bump falls within a top view projection of the built-in current block.
Optionally, the second conductive block includes a core and two wings located on two sides of the core; the first DBR reflective layer has a first via and a second via through itself; the second via is located above the middle of the core of the second conductive block.
Optionally, the LED chip further includes a second DBR reflective layer, and the second DBR reflective layer is located on the back surface of the substrate.
In order to solve the above problems, the present invention further provides an LED chip package module, including the LED chip as described above.
In order to solve the above problems, the present invention further provides a display device, including the LED chip as described above, where the LED chip is used as a backlight source chip of a backlight module of the display device.
In one aspect of the present invention, the LED chip is designed such that the jumper conductive block has a junction, a first contact, and a second contact, and the jumper current blocking block has a head and a tail, wherein the junction is located in the head, the first contact is located in the tail, a portion of the head that does not overlap the junction has a first width, a portion of the tail that does not overlap the first contact has a second width, and the first width is greater than the second width. At this moment, because the head is located recess position, it is comparatively uneven usually, the electric resistance dog can be thinner on the slope, consequently, with the width design of head wideer, can guarantee better the reliability of the knot portion of recess top prevents phenomenons such as electric leakage, improves product reliability.
Furthermore, the LED chip has no overlapping part between the overlooking projection of the bridging conductive block and the overlooking projections of the first conductive pad and the second conductive pad through structural design, so that the chip leakage condition caused by the damage of the protective passivation layer can be prevented, namely, the leakage channel can be reduced, and the reliability of the product is improved.
Furthermore, the overlooking projection of the bridging conductive block and the overlooking projection of the second current expansion layer do not have an overlapping part, and in the structure, the bridging conductive block is positioned at the edge of the core grain, so that the problem of failure of the LED chip caused by the fact that the middle bridging conductive block is damaged by the ejector pin (the ejector pin is a tool for matching the chip to grab) in the grabbing process of the LED chip is solved, and the reliability of the product is improved.
Furthermore, the two bridging conductive blocks are designed, so that when a single bridging conductive block is damaged, the failure of a core particle cannot be caused, and the reliability of a product is better. Meanwhile, the two bridging conductive blocks are distributed on two sides of the core grain, so that the problem of failure of the LED chip caused by the fact that the middle bridging conductive block is damaged by the ejector pin is further solved, and the reliability of the product is further improved.
Furthermore, the provided LED chip takes the first DBR reflecting layer as a protective passivation layer, and is provided with corresponding through holes above the middle position of the overlooking projection of the first conductive block and above the middle position of the overlooking projection of the second conductive block, so that the corresponding current diffusion (expansion) effect is better, and the performance of the product is better.
Drawings
FIG. 1 is a schematic diagram of a partial cross-sectional structure of an LED chip in a first embodiment;
FIG. 2 is a schematic top-view projection of the top layer of the first mesa structure, the top layer of the second mesa structure and the substrate in the first embodiment;
FIG. 3 is a schematic top plan view of the first deep trench, the second deep trench and the substrate in the first embodiment;
FIG. 4 is a schematic top plan view of a first embodiment of a cross-over current block and its same layer structure and substrate;
FIG. 5 is a schematic diagram of a partial cross-sectional structure of the first embodiment further shown in FIG. 1, spanning the current block and its same layer structure;
FIG. 6 is a schematic top plan view of a first current spreading layer, a second current spreading layer and a substrate in a first embodiment;
FIG. 7 is a schematic diagram showing a cross-sectional view of a portion of the first embodiment, further showing the cross-over conductive block and its same layer structure on FIG. 5;
FIG. 8 is a schematic top plan view of a first embodiment of a cross-over conductive block and its same layer structure and substrate;
FIG. 9 is a schematic top view projection of the layer across the current block and the layer across the conductive bump together with the substrate in the first embodiment;
FIG. 10 is a schematic diagram of a first embodiment further showing a partial cross-sectional structure of the first DBR reflective layer in FIG. 7;
FIG. 11 is a schematic top view of the first DBR reflective layer in the first embodiment;
FIG. 12 is a schematic cross-sectional view of an LED chip according to the first embodiment;
FIG. 13 is a schematic top view projection of the first conductive pad, the second conductive pad and the substrate in the first embodiment;
FIG. 14 is a schematic top view of an LED chip in a first embodiment, and is a schematic solid perspective structure;
fig. 15 is a schematic top view projection of the top layer of the first mesa structure, the top layer of the second mesa structure and the substrate in the second embodiment;
FIG. 16 is a schematic top plan view of a cross-over current block and its same layer structure and substrate in a second embodiment;
FIG. 17 is a schematic top plan view of a second embodiment of a jumper conductive block and its same layer structure and substrate;
FIG. 18 is a top plan view of a layer spanning the current block and a layer spanning the conductive bump in a second embodiment taken together with the substrate;
FIG. 19 is a schematic top view projection of the first conductive pad, the second conductive pad and the substrate in the second embodiment;
FIG. 20 is a schematic view of an overall top-view projection of an LED chip in a second embodiment, and is a schematic view of a solid perspective structure;
fig. 21 is a schematic top view projection of the top layer of the first mesa structure, the top layer of the second mesa structure and the substrate in the third embodiment;
FIG. 22 is a schematic top plan view of a third embodiment of a cross-over conductive block and its same layer structure and substrate;
FIG. 23 is a schematic top plan view of a layer spanning the current block and a layer spanning the conductive bump in a third embodiment taken together with the substrate;
FIG. 24 is a schematic top view of an LED chip in a third embodiment, and is a schematic solid perspective structure;
fig. 25 is a schematic top view projection of the top layer of the first mesa structure, the top layer of the second mesa structure and the substrate in the fourth embodiment;
FIG. 26 is a schematic top plan view of a fourth embodiment of a cross-over current block and its same layer structure and substrate;
FIG. 27 is a schematic top plan view of a fourth embodiment of a cross-over conductive block and its same layer structure and substrate;
FIG. 28 is a schematic top plan view of a layer crossing a current block and a layer crossing a conductive bump in a fourth embodiment taken together with a substrate;
FIG. 29 is a schematic top view of an LED chip in a fourth embodiment, and is a schematic solid perspective structure;
fig. 30 is a schematic top view projection of the top layer of the first mesa structure, the top layer of the second mesa structure and the substrate in the fifth embodiment;
FIG. 31 is a schematic top plan view of a fifth embodiment of a cross-over current block and its same layer structure and substrate;
FIG. 32 is a schematic top plan view of a fifth embodiment of a cross-over conductive block and its same layer structure and substrate;
FIG. 33 is a schematic top plan view of a layer crossing a current block and a layer crossing a conductive bump in a fifth embodiment taken together with a substrate;
fig. 34 is a schematic top view of an entire LED chip in a fifth embodiment, and is a schematic solid perspective structure.
Detailed Description
The invention provides a novel LED chip, an LED chip packaging module and a display device, and for clearer representation, the invention is described in detail below with reference to the accompanying drawings.
The present description will assume simplified references to structures, except in figures 12 and 14, where the same structure is referenced only once, in cross-sectional and top plan projection, respectively, to more clearly show the structure.
Fig. 1 to 14 are combined, wherein fig. 14 is a schematic top view projection diagram of each structure of the entire LED chip, and shows a schematic perspective structure diagram of solid lines, that is, each structure is displayed by overlapping solid lines.
As shown in fig. 1 to 14, the LED chip includes a substrate 100, a first mesa structure 111, a second mesa structure 112, a cross-over current blocking bump 130 (refer to fig. 1, 4, and 14), a cross-over conductive bump 150 (refer to fig. 7, 8, and 14), a first conductive pad 171 (refer to fig. 12, 13, and 14), and a second conductive pad 172 (refer to fig. 12, 13, and 14).
Fig. 1 shows a first mesa structure 111 on a substrate 100 and a second mesa structure 112 on the substrate 100.
In this embodiment, the substrate 100 may be sapphire (Al)2O3) And the like. As is well known in the art, the first and second mesa structures 111 and 112 may generally include a first conductive type semiconductor layer, a quantum well layer, and a second conductive type semiconductor layer from bottom to top. The first conductivity type semiconductor layer is a bottom layer of the mesa structure, and may generally include an N-type semiconductor layer, a buffer layer, and the like, that is, a stacked structure. The quantum well layer and the second conductive type semiconductor layer may each generally have a stacked structure, and the second conductive type semiconductor layer may generally include a P-type semiconductor layer, which serves as a top layer of the mesa structure.
It should be noted that, in other embodiments of the present invention, a third mesa structure (not shown) may be further included, that is, there may be more than three mesa structures, and the corresponding serial connection manner and structure may refer to the entire contents of this embodiment, which is not described herein again.
Fig. 2 shows a top-down projection of the top layer of the first mesa structure 111 (the second conductive type semiconductor layer), the top layer of the second mesa structure 112 (the second conductive type semiconductor layer) and the substrate 100 separately. The top projection of the top layer of the first mesa structure 111 has an inner concave notch 1111. The top projection of the second mesa structure 112 is a chamfered rectangle having two corner notches 1121, the corner notches 1121 face the first mesa structure 111, and the two corner notches 1121 are symmetrical. In other embodiments, only one corner notch 1121 may be provided, and the corner notch 1121 may also be a structure similar to the concave notch 1111, exposing the first conductive type semiconductor layer of the second mesa.
Fig. 3 shows the first deep trench 121, the second deep trench 122, and the substrate 100 in top-view projection separately. The first deep trench 121 and the second deep trench 122 are formed by an etch-back (ISO) process, which respectively surround projections of the first mesa structure 111 and the second mesa structure 112, and a recess (not labeled) described later is formed between regions surrounded by the first deep trench 121 and the second deep trench 122.
Fig. 4 shows a top view projection of the cross-over current blocking bumps 130, the same layer structure thereof, and the substrate in the structure shown in fig. 1, where the number of the cross-over current blocking bumps 130 corresponds to the number of the notches 1121, and in this embodiment, there are two cross-over current blocking bumps 130, as can be seen from fig. 1 to 4, the two cross-over current blocking bumps 130 respectively cover a part of the upper surface and a part of the side surface of the first mesa structure 111, and cover a part of the groove (as described above, not labeled) between the first mesa structure 111 and the second mesa structure 112.
Fig. 7 shows a partial cross-sectional structure of the LED chip, in which the topmost structure is a bridging conductive bump 150.
Fig. 8 shows that the number of the cross-over conductive bumps 150 is the same as that of the cross-over current blocking bumps 130, and since there are two cross-over current blocking bumps 130, there are also two cross-over conductive bumps 150. Two bridging conductive bumps 150 are located on both sides (edge regions) of the core grain, which are shown as upper and lower sides in fig. 8, that is, two bridging conductive bumps 150 are located on two opposite edges of the whole top-view projection region, respectively.
As can be seen from fig. 7 and 8, the main portion of the cross-over conductive bump 150 is located on the cross-over current blocking bump 130, a first end of the cross-over conductive bump 150 is electrically connected to the top layer of the first mesa structure 111, and a second end of the cross-over conductive bump 150 is electrically connected to the bottom layer of the second mesa structure 112.
It should be noted that fig. 8 shows a dashed line (not labeled), where the dashed line is a cutting trend for illustrating each cross-sectional schematic diagram of the present embodiment, that is, each cross-sectional structural schematic diagram is cut along the direction of the broken line shown in fig. 8 and then re-spliced to a plane.
Fig. 12 shows that the first conductive pad 171 is located above the first mesa structure 111, and the second conductive pad 172 is located above the second mesa structure 112. The first conductive pad 171 and the second conductive pad 172 may be respective various metals or alloys.
Fig. 13 shows a top projection of the first conductive pad 171, the second conductive pad 172, and the substrate 100 separately.
As can be seen from a comparison between fig. 8 and fig. 13, the present embodiment is designed such that the top projection of the cross-over conductive block 150 does not overlap with the top projections of the first conductive pad 171 and the second conductive pad 172, and the structure design can also be directly seen from fig. 14.
Fig. 14 shows that, in the present embodiment, the top projection of the two bridging conductive blocks 150 is symmetrical, and a portion of the top projection of the first conductive pad 171 is sandwiched between the two bridging conductive blocks 150.
In this embodiment, the crossover current block 130 and the crossover conductive block 150 both cross the groove. The material of the cross-over current block 130 may be a corresponding transparent insulating material, such as SiO2And the like. The material of the jumper conductive block 150 may be various metals, metal conductive oxides, or other conductive materials, such as copper, silver, gold, or corresponding alloys.
With reference to fig. 8, in the present embodiment, the cross-over conductive block 150 has a first contact portion 1501, a junction portion 1502 and a second contact portion 1503 in a top view projection, the junction portion 1502 crosses over the groove, an outer end of the first contact portion 1501 is a first end, and an outer end of the second contact portion 1503 is a second end. The junction 1502 falls within a top view projection across the current block 130.
In this embodiment, the width of the junction 1502 is greater than the width of the first contact 1501, and the width of the second contact 1503 is greater than the width of the junction 1502. The width relationship of the portions of the bridging conductive block 150 is represented by the dimension in the vertical direction in fig. 8, and the length of the bridging conductive block 150 is represented by the dimension in the horizontal direction in fig. 8. The design of different widths further optimizes the whole structure of the chip and improves the reliability.
The main body of the cross-over conductive block 150 is located on the cross-over current blocking block 130, and is mainly embodied as: the junction 1502 falls entirely within the top-view projection across the current block 130; most of the structure of the first contact 1501 and the second contact 1503 also falls within the top view projection of the crossover current block 130, and a small segment of the end of the first contact 1501 and the second contact 1503 crosses over the crossover current block 130 to achieve corresponding electrical connection.
In this embodiment, the bisectors of the first contact portion 1501, the knot portion 1502 and the second contact portion 1503 are coincident with each other, i.e., the whole cross-over conductive block 150 has an axisymmetric shape in a top view, like a nail-like structure with a flat top (i.e., the second contact portion 1503) and a neck (i.e., the knot portion 1502), and the first contact portion 1501 is a nail portion of the nail-like structure. This structure can make use of the junction portion 1502 to better cross the groove, and the feature of the second contact portion 1503 that the front end is wider is utilized to increase the corresponding conductive contact area, thereby being beneficial to improving the reliability of the product. Referring to fig. 4, in the present embodiment, a top view projection of the cross current block 130 includes a head portion 1301 and a tail portion 1302.
Referring to fig. 9, in each top projection, the junction 1502 is in the head 1301, the first contact 1501 is in the tail 1302, and the second contact 1503 does not overlap the cross-over current block 130.
With continued reference to FIG. 9, the portion of the head 1301 not overlapping the junction 1502 has a first width W1, the portion of the tail 1302 not overlapping the first contact 1501 has a second width W2, and the first width W1 is greater than the second width W2. In fig. 9, it is shown that the portion of the head portion 1301 not overlapping the knot portion 1502 is surrounded on both upper and lower sides of the knot portion 1502, and the portion of the tail portion 1302 not overlapping the first contact portion 1501 is surrounded on both left and upper and lower sides of the first contact portion 1501.
Due to the design, the head 1301 (bridging the current blocking block 130) is located at the position of the groove, which is generally uneven, the current blocking blocks on the slope are thinner, and the current blocking blocks of the parts are easily over-etched in the etching process in the forming process, so that the width of the head 1301 is designed to be wider in the embodiment, and at the moment, the reliability of the structure above the groove (i.e. mainly referring to the junction 1502 bridging the conductive block 150) can be better ensured, the phenomena of electric leakage and the like are prevented, and the product reliability is improved. The first width W1 and the second width W2 are in directions perpendicular to the common bisector of the head portion 1301 and the tail portion 1302 in the present embodiment, and refer to fig. 9 directly.
In this embodiment, the first width W1 shown in fig. 9 is between 3 μm and 100 μm, and may be, for example, 5 μm, 10 μm, 20 μm, 30 μm, or 50 μm. These widths are selected to better ensure that the corresponding electrical leakage is prevented, ensuring good conduction across the conductive block 150.
In this embodiment, the size of the second width W2 shown in fig. 9 is between 0 μm and 30 μm, for example, it may be 0.5 μm, 1 μm, 5 μm or 10 μm, and the first width W1 is always larger than the second width W2.
Referring back to fig. 5 and 6, fig. 5 shows a partial cross-sectional structure of the LED chip, where the topmost structure is a current spreading layer. As can be seen from fig. 5, the LED chip further includes a first current spreading layer 141 and a second current spreading layer 142.
Fig. 5 shows that the first current spreading layer 141 is located above the first mesa structure 111. Fig. 12 shows that the first conductive pad 171 is located above the first current spreading layer 141. Fig. 7 shows that the cross-over conductive block 150 is electrically connected to the top layer of the first mesa structure 111 by connecting the first current spreading layer 141. Fig. 5 shows the second current spreading layer 142 positioned over the second mesa structure 112, and fig. 12 shows the second conductive pad 172 positioned over the second current spreading layer 142.
Fig. 6 shows a top view projection of the first current spreading layer 141, the second current spreading layer 142 and the substrate 100 in isolation.
As can be seen from a comparison between fig. 6 and fig. 2, and with reference to fig. 14, the top-view projection shapes of the first current spreading layer 141 and the top layer of the first mesa structure 111 are similar, the first current spreading layer 141 is located in the first mesa structure 111, the top-view projection shapes of the second current spreading layer 142 and the top layer of the second mesa structure 112 are similar, and the second current spreading layer 142 is located in the second mesa structure 112. Thus, fig. 6 shows that the first current spreading layer 141 has a notch 1411 corresponding to the inner concave notch 1111, and the second current spreading layer 142 has two notches 1421 corresponding to the two corner notches 1121.
It should be noted that the indent notch 1111 is caused by the difference of the top and bottom projections of the first mesa structure 111, that is, the corresponding area of the indent notch 1111 still belongs to a portion of the first mesa structure 111, and the corresponding first conductive block 151 is located right on the portion of the bottom structure; the notch 1411 of the first current spreading layer 141 indicates that there is no corresponding current spreading layer structure at this position. Similarly, the corner notch 1121 is caused by the difference between the top and bottom projections of the second mesa structure 112, that is, the area corresponding to the corner notch 1121 still belongs to a portion of the second mesa structure 121, the corner notch 1121 corresponds to the bottom structure of the second mesa structure 112, and the second end of the bridging conductive block 150 is just connected to the bottom structure corresponding to the corner notch 1121; the second current spreading layer 142 has a gap 1421, which indicates that there is no corresponding current spreading layer structure at this position.
As can be seen from fig. 6 and 8, the top projection of the bridging conductive block 150 and the top projection of the second current spreading layer 142 do not overlap, and can be directly seen from fig. 14. However, the cross-over conductive block 150 and the first current spreading layer 141 have an overlapping portion, which means an electrical connection of the cross-over conductive block 150 and the first current spreading layer 141, and the overlapping structure can also be visually seen from fig. 7.
Fig. 10 shows a partial cross-sectional structure of the LED chip, where the topmost structure is the first DBR reflective layer 160, i.e., the LED chip further includes the first DBR reflective layer 160.
Fig. 11 shows a top projection of the first DBR reflective layer 160 in isolation.
As can be seen from fig. 10 and 11, the first DBR reflective layer 160 covers the first current spreading layer 141 and the second current spreading layer 142. Fig. 12 shows that the first conductive pad 171 is located on the first DBR reflective layer 160, and the first conductive pad 171 penetrates the first DBR reflective layer 160 to electrically connect the bottom layer of the first mesa structure 111. Fig. 12 shows that a second conductive pad 172 is located on the first DBR reflective layer 160, and the second conductive pad 172 penetrates the first DBR reflective layer 160 to electrically connect to the second current spreading layer 142.
In this embodiment, the first DBR reflective layer 160 serves as a passivation protective layer at the same time, which simplifies the structure and improves reliability.
Referring to fig. 10 and 11, the first conductive pad 171 and the second conductive pad 172 penetrate the position of the first DBR reflective layer 160 by using a first via 1601 and a second via 1602 of the first DBR reflective layer 160, respectively.
Referring back to fig. 1 and 4, the LED chip further includes an internal current block 132, the internal current block 132 and the cross-over current block 130 are in the same layer structure, and the internal current block 132 is located between the second mesa structure 112 and the second current spreading layer 142, please refer to fig. 5, 7, 10 and 12 in combination.
It should be noted that, in the chip structure, the same layer structure does not refer to a structure located on the same horizontal plane, but refers to: structures that may be formed in the same process, together with structures formed on the basis of previous processes, may be formed in different locations.
With continued reference to fig. 4, the top view projection of the internal current blocker 132 includes a central portion 1321 and two side portions 1322 connecting the central portion 1321, the central portion 1321 being circular. The side portions 1322 are symmetrically disposed at both sides of the circular shape in an ear-shaped structure.
Referring back to fig. 7 and 8, the LED chip further includes a first conductive block 151, and the first conductive block 151 and the bridging conductive block 150 are in the same layer structure. As mentioned above, the top-view projection of the top layer of the first mesa structure 111 has the concave notch 1111 (the top-view projection of the first mesa structure 111 has a chamfered rectangle with the concave notch 1111), and as can be compared with fig. 2 and 8, the top-view projection of the first conductive bump 151 falls within the concave notch 1111 of the first mesa structure 111, and this structure design can also be visually seen in fig. 14. In this embodiment, the top projection of the first conductive block 151 is circular, as shown in fig. 8. As mentioned above, the top projection of the second mesa structure 112 is a chamfered rectangle having two corner notches 1121, the corner notches 1121 face the first mesa structure 111, and the two corner notches 1121 are symmetrical. The corner notch 1121 is matched with the bridging conductive block 150. The specific matching is to realize a fitting structure that fits each other, that is, the top surface of the second mesa structure 112 is staggered from the bridging conductive block 150, and the bottom surface of the second mesa structure 112 is connected to the bridging conductive block 150, which can be referred to in fig. 12 and 14 in combination.
Referring back to fig. 7 and 8, the LED chip further includes a second conductive bump 152, the second conductive bump 152 and the bridging conductive bump 150 are in the same layer structure, the second conductive bump 152 is located above the built-in current blocking bump 132 and on the second current spreading layer 142, and the second conductive pad 172 is electrically connected to the second current spreading layer 142 by connecting the second conductive bump 152. As can be seen from fig. 7 and 8, the top projection of the second conductive bump 152 falls within the top projection of the built-in current blocking bump 132.
Fig. 7 shows that the second conductive bump 152 and the built-in current blocking bump 132 are separated by the second current spreading layer 142.
As shown in fig. 8, the second conductive block 152 includes a core portion 1521 and two wing portions 1522, the two wing portions 1522 are symmetrically located at two sides of the core portion 1521, as can be seen by referring to fig. 4 and 8, the core portion 1521 is located above the middle portion 1321, and the core portion 1521 falls within the middle portion 1321; wing portion 1522 is positioned over side portion 1322 and wing portion 1522 is seated within side portion 1322 as can also be seen visually in fig. 14.
As mentioned above, the top view projection of the second conductive bump 152 is within the top view projection of the built-in current blocking bump 132, so that the current can be prevented from being directly injected downward, as can be directly seen from fig. 14. That is, the second conductive bump 152 and the built-in current stopper 132 are cooperatively disposed, so that the second current spreading layer 142 can fully exert the current spreading function, and simultaneously, the current is prevented from being directly injected from the second conductive pad 172 on the second conductive bump 152 to the mesa structure below the second conductive pad 172.
In this embodiment, it has been mentioned above that the first DBR reflective layer 160 has the first via 1601 and the second via 1602 penetrating through itself, and the second via 1602 is located above and in the middle of the core portion 1521 of the second conductive block 152, and this structure can be visually compared with fig. 8, 10 and 11, or the structure design can be directly derived from fig. 14. Such a structure is different from the conventional structure that the corresponding conductive structure is usually directly connected with the end of the conductive structure, and the second conductive pad 172 is ensured to be directly connected with the center of the core portion 1521 of the second conductive block 152, so that current injection can be ensured to diffuse from the middle of the second conductive block 152 to the periphery (particularly to both sides), and the two wing portions 1522 can also better assist the corresponding current diffusion function, so that the current diffusion effect is better, and the chip reliability is higher.
Also shown in fig. 12, the LED chip further includes a second DBR reflective layer 180, the second DBR reflective layer 180 being located on the back surface of the substrate 100.
In a top view projection, the first conductive block 151 is equidistant from the first conductive pad 171 and the second conductive pad 172, which can be combined with fig. 8 and 13, or refer to fig. 14 directly.
Fig. 13 and 14 show that, in a top projection, the second conductive pad 152 is located at an equal distance from the two bridging conductive pads 150, or that the top projection of the second conductive pad 152 falls on a common bisector of the first conductive pad 171 and the second conductive pad 172. This also means that the second through hole 1602 of the first DBR reflective layer 160 is disposed at an intermediate position in the width direction thereof. By the structure, current injection can be diffused from the middle to two sides, the current diffusion effect is better, and the chip reliability is higher.
Fig. 13 separately shows a top view projection of the first conductive pad 171, the second conductive pad 172 and the substrate 100, from which it can be seen that the first conductive pad 171 is of a convex design (protruding toward the second conductive pad 172), and, in combination with fig. 8, the first conductive pad 171 and the second conductive pad 172 do not overlap with the location of the jumper conductive block 150 in a top view projection, which can also refer to fig. 14.
In this embodiment, the length direction of the bridging current block 130 is perpendicular to the length direction of the built-in current block 132, but in other embodiments, the two length directions may be parallel.
In the LED chip provided in this embodiment, through the structural design, there is no overlapping portion between the top view projection of the bridging conductive block 150 and the top view projections of the first conductive pad 171 and the second conductive pad 172, so as to prevent the chip from leaking electricity due to the damage of the protection passivation layer (i.e., the first DBR reflective layer 160), that is, reduce the leakage path, and improve the reliability of the product.
Furthermore, the top-view projection of the bridging conductive block 150 and the top-view projection of the second current spreading layer 142 do not have an overlapping portion (conversely, the bridging conductive block 150 is connected to the bottom layer of the second mesa structure 112 below the second current spreading layer 142), and in this structure, the bridging conductive block 150 is located at the edge of the core grain, so that the problem of LED chip failure caused by the middle bridging conductive block being damaged by the thimble in the process of grabbing the LED chip is solved, and the reliability of the product is improved.
In the LED chip provided by this embodiment, two bridging conductive blocks 150 are designed, and when a single bridging conductive block 150 is damaged, the core particle will not fail, so that the reliability of the product is better. Meanwhile, the two bridging conductive blocks 150 are distributed on two sides of the core grain, so that the problem of failure of the LED chip caused by the fact that the middle bridging conductive block is damaged by the ejector pin can be further solved, and the reliability of the product is further improved.
In the LED chip provided in this embodiment, the corresponding first through hole 1601 of the first DBR reflective layer 160 is disposed above the middle position of the top view projection of the first conductive block 151, and the corresponding second through hole 1602 of the first DBR reflective layer 160 is disposed above the middle position of the top view projection of the second conductive block 152, which can be combined with fig. 8 and 11, or can be directly referred to fig. 14, so that the corresponding current spreading (expanding) function is better, and the performance of the product is better.
The LED chip that this embodiment provided sets up above-mentioned first width W1 and is greater than second width W2, and the bridging structure of protection recess department that can be better reaches better leak protection and better guarantees the effect of electric connection, has further improved the reliability.
Another embodiment of the present invention provides another LED chip, please refer to fig. 15 to fig. 20 in combination, wherein fig. 20 is a schematic top view projection diagram of each structure of the entire LED chip. Also, the sectional view of fig. 12 of the foregoing embodiment can be combined because the sectional structure of the LED chip of the present embodiment is substantially the same as that of the LED chip of the foregoing embodiment.
Referring to fig. 15, the LED chip includes a substrate 100, a first mesa structure 111, a second mesa structure 112, a cross-over current blocking bump 130 (refer to fig. 16 and 20), a cross-over conductive bump 150 (refer to fig. 17 and 20), a first conductive pad 171 (refer to fig. 19 and 20), and a second conductive pad 172 (refer to fig. 19 and 20). A first mesa structure 111 is located on the substrate 100 and a second mesa structure 112 is located on the substrate 100.
Fig. 15 shows a top-down projection of the top layer of the first mesa structure 111, the top layer of the second mesa structure 112 and the substrate 100 separately. The top projection of the top layer of the first mesa structure 111 has an inner concave notch 1111. The top projection of the second mesa structure 112 is a chamfered rectangle having two corner notches 1121, the corner notches 1121 face the first mesa structure 111, and the two corner notches 1121 are symmetrical.
The present embodiment does not separately show the corresponding deep trench projection, which can refer to fig. 3 of the previous embodiment, and also refer to fig. 20.
Fig. 16 shows that there are two cross-over current blocks 130 of this embodiment.
Fig. 17 shows that there are two bridging conductive bumps 150, which are located at two opposite edges of the whole top projection area.
Referring to fig. 18, a schematic view of the structural layers of fig. 16 and 17 is shown after lamination. A junction 1502 and a first contact 1504 are included across the current block 130, including the head portion 1301 and the tail portion 1302, respectively. In a top view projection, the junction 1502 falls within the head 1301, the first contact 1504 is located within the tail 1302, and the second contact 1505 has no overlap with the crossover current block 130.
Referring to fig. 18, a portion of the head 1301 not overlapping the junction 1502 has a first width W1, a portion of the tail 1302 not overlapping the first contact 1504 has a second width W2, and the first width W1 is greater than the second width W2. The design is also used for preventing the phenomena of electric leakage and the like and improving the reliability of the product.
In the present embodiment, the first width W1 is between 3 μm and 100 μm, and may be, for example, 5 μm, 10 μm, 20 μm, 30 μm, or 50 μm. These widths are selected to better ensure that the corresponding electrical leakage is prevented, ensuring good conduction across the conductive block 150. The second width W2 is between 0 μm and 30 μm, for example, 0.5 μm, 1 μm, 5 μm, or 10 μm, and the first width W1 is always larger than the second width W2.
Fig. 19 shows a top view projection of the first conductive pad 171, the second conductive pad 172 and the substrate 100 separately, from which it can be seen that the first conductive pad 171 and the second conductive pad 172 are both of a convex design. In addition, a part of the second conductive pad 172 is also sandwiched between the two bridging conductive bumps 150 in a plan view, and the plan view shape of the first conductive pad 171 and the plan view shape of the second conductive pad 172 are substantially symmetrical. The substantially symmetrical means that the top view shape of the first conductive pad 171 and the top view shape of the second conductive pad 172 each have a chamfered rectangle with a pair of cut corners, which are different only in that the corresponding cut corners are not the same, including that the size, shape and angle of the cut corners are slightly different, but are generally symmetrical as a whole, as shown in fig. 19.
In the present embodiment, there is no overlapping portion between the top projection of the cross-over conductive block 150 and the top projection of the first conductive pad 171 and the second conductive pad 172, and this structural design can be directly seen from fig. 20.
Fig. 20 shows that, in the present embodiment, the top projection of the two bridging conductive blocks 150 is symmetrical, and a portion of the top projection of the first conductive pad 171 is sandwiched between the two bridging conductive blocks 150.
Referring to fig. 12 of the previous embodiment, the LED chip of this embodiment also includes a first current spreading layer 141 and a second current spreading layer 142.
In this embodiment, the top projection of the bridging conductive block 150 and the top projection of the second current spreading layer 142 do not overlap, and can be directly seen from fig. 20. There is a corresponding overlap in the top view projection of the cross-over conductive block 150 and the first current spreading layer 141.
The LED chip of this embodiment further includes a first DBR reflective layer 160, and the first DBR reflective layer 160 has a first through hole 1601 and a second through hole 1602, which can be referred to the corresponding contents of the previous embodiments.
The LED chip further includes an internal current blocker 132, and a top view projection of the internal current blocker 132 includes a middle portion 1321 and two side portions 1322 connecting the middle portion 1321.
The LED chip further includes a first conductive bump 151, and a top-view projection of the first conductive bump 151 falls within the concave indentation 1111 of the first mesa structure 111, which can also be seen from fig. 20.
The LED chip further comprises a second conductive bump 152, a top view projection of the second conductive bump 152 falling within a top view projection of the built-in current block 132. The second conductive mass 152 includes a core 1521 and two wings 1522, the core 1521 being located above the middle portion 1321, the core 1521 falling within the middle portion 1321; wing portion 1522 is positioned over side portion 1322 and wing portion 1522 is seated within side portion 1322 as can also be seen visually in fig. 20.
Referring to fig. 12 of the previous embodiment, the LED chip further includes a second DBR reflective layer 180, and the second DBR reflective layer 180 is located on the back surface of the substrate 100.
In this embodiment, the length direction of the cross current block 130 is parallel to the length direction of the built-in current block 132.
Please refer to the corresponding contents of the foregoing embodiments for more details regarding the structure, properties and advantages of the LED chip provided by the present embodiment.
Unlike the previous embodiment, the corner notch 1121 of the present embodiment shown in fig. 15 is more specifically shaped so that the second mesa structure 112 can be divided into three portions having different average widths, which are shown in fig. 15 by dashed line divisions.
Different from the previous embodiments, correspondingly, the cross-over conductive block 150 of the present embodiment has a first contact 1504, a junction 1502 and a second contact 1505 in a top view projection, wherein the junction 1502 crosses over the groove, the outer end of the first contact 1504 is the first end, and the outer end of the second contact 1505 is the second end. The junction 1502 falls within a top view projection across the current block 130.
Unlike the previous embodiments, the width of the knot portion 1502 of the present embodiment is larger than the width of the first contact portion 1504 and the width of the second contact portion 1505, and the width of the finger portion 1504 and the width of the second contact portion 1505 can be equal. The width structure design is beneficial to the optimization of the structure and the improvement of the reliability.
The corner notch 1121 of fig. 15 is matched with the bridging conductive block 150 of fig. 17, so that the corresponding bridging series connection conductive function is stronger and the reliability is further improved in the present application.
Unlike the previous embodiments, the bisector of the junction 1502 of the present embodiment coincides with the bisector of the first contact 1504 with a first straight line (not shown), the bisector of the second contact 1505 is a second straight line (not shown), the first straight line is parallel to the second straight line, and the second contact 1505 connects the outer corners of the junction 1502 (outer corners refer to corners that are more edgewise). Which together define the top-view projected shape of the cross-over conductive block 150 shown in fig. 17. This particular shape of the jumper conductive block 150 also provides the advantages of the previous embodiments and further enhances the series conductive connection.
It should be noted that the coincidence of the bisectors is the coincidence under design, and the ideal actual product should coincide, but some actual products may have a certain deviation due to factors such as process, which is understood in the art.
In other embodiments, the bisector of the junction and the bisector of the second contact portion may coincide with a first straight line, the bisector of the first contact portion is a second straight line, the first straight line is parallel to the second straight line, and the first contact portion connects the inner corners of the junction (the inner corners refer to corners toward a more central area).
Unlike the previous embodiments, in this embodiment, the common bisector of the central portion 1321 and the side portions 1322 is a third straight line (not shown) that is parallel to the first straight line.
Similar to the previous embodiment, a top-down projection across current block 130 is shown in fig. 20 with a head 1301 and a tail 1302. In a top view projection, the junction 1502 is within the head 1301, the first contact 1504 is within the tail 1302, and the second contact 1505 has no overlap with the crossover current block 130.
In the present embodiment, the width of the head 1301 is 1.5 times or more, for example, 1.5 times, 2 times, or 2.5 times, as large as the width of the tail 1302.
Another embodiment of the present invention provides another LED chip, please refer to fig. 21 to 24 in combination, wherein fig. 24 is a schematic top view projection diagram of each structure of the entire LED chip. Also, the cross-sectional view of fig. 12 of the foregoing embodiment can be combined because the cross-sectional structure of the present embodiment is substantially the same as that of the foregoing embodiment.
Most of the structures of the LED chips provided in this embodiment are the same as those of the LED chips shown in fig. 15 to 20, and therefore, reference may be made to the corresponding contents of the foregoing embodiments.
The present embodiment is different from the embodiment shown in fig. 15 to 20 in two places: first, as shown in fig. 21, the shape of the concave notch 1111 formed by the top-view projection of the first mesa structure 111 of the present embodiment is different; second, as shown in fig. 22, the first conductive block 151 of the present embodiment has a different top projection shape. In this embodiment, the top view projection of the indent notch 1111 is shaped like a funnel, and the top view projection of the first conductive block 151 is shaped like a nail with a round head.
Referring to fig. 23, there is shown a schematic view of the layer structure of the crossover conductive block 150 and the crossover current block 130 (see fig. 16 of the previous embodiment) in fig. 22 laminated together. A junction 1502 and a first contact 1504 are included across the current block 130, including the head portion 1301 and the tail portion 1302, respectively. In a top view projection, the junction 1502 falls within the head 1301, the first contact 1504 is located within the tail 1302, and the second contact 1505 has no overlap with the crossover current block 130.
Referring to fig. 23, a portion of the head 1301 not overlapping the junction 1502 has a first width W1, a portion of the tail 1302 not overlapping the first contact 1504 has a second width W2, and the first width W1 is greater than the second width W2. The design is also used for preventing the phenomena of electric leakage and the like and improving the reliability of the product.
The design of the first conductive bump 151 also falling within the recessed notch 1111 of the first mesa structure 111 can be seen with reference to fig. 24.
In this embodiment, the concave notch 1111 is located on a bisector (not shown) of the top projection of the first mesa structure, and this bisector also bisects the concave notch 1111 and the first conductive block 151. That is, when the top projection of the first conductive bump 151 is in the shape of a round-headed nail, the bisector of this round-headed nail is also parallel to the first straight line described in the embodiment shown in fig. 15 to 20. The design is also beneficial to the expansion of corresponding current.
Please refer to fig. 15 to 20 for further description about the structure, properties and advantages of the LED chip provided in this embodiment.
Another embodiment of the invention provides another LED chip, please refer to fig. 25 to fig. 29 in combination, in which fig. 29 is a schematic top view projection diagram of each structure of the entire LED chip. Also, its cross-sectional structure may incorporate the cross-sectional view of fig. 12 of the previous embodiment.
The structure of the LED chip provided in this embodiment is the same as that of the previous embodiment, and therefore, reference may be made to the corresponding content of the previous embodiment.
In this embodiment, as shown in fig. 25, the top projection of the second mesa structure 112 also forms the concave notches 1122 instead of forming the corner notches, and the number of the concave notches 1122 is one.
More importantly, as shown in fig. 26, in the present embodiment, only one cross current block 130 includes a head portion 1301 and a tail portion 1302, and the width of the tail portion 1302 is greater than the width of the head portion 1301.
Accordingly, as shown in fig. 27, there is only one bridging conductive block 150, which is located at the middle of the entire top projection area. The jumper conductive block 150 includes a junction 1502, a first contact 1506, and a second contact 1507. The width of the first contact 1506 is greater than the width of the second contact 1507, and the width of the second contact 1507 is greater than the width of the junction.
In this embodiment, only one cross-over current blocking piece 130 and cross-over conductive piece 150 are designed, but they are correspondingly arranged at the middle position of the whole top-view structure, and the widths of the cross-over current blocking piece and the cross-over conductive piece are correspondingly increased, which helps to improve the conductive performance of the cross-over current blocking piece and the cross-over conductive piece, and thus improves the reliability of the product.
Referring to fig. 28, a schematic view of the structures of fig. 26 and 27 is shown after they have been stacked together. A junction 1502 and a first contact 1506 are included across the current block 130, including the head portion 1301 and the tail portion 1302, respectively. In a top view projection, the junction 1502 is located in the head portion 1301, the first contact 1506 is located in the tail portion 1302, and the second contact 1507 has no overlapping portion with the crossover current block 130.
Referring to fig. 28, a portion of the head portion 1301 not overlapping the knot portion 1502 has a first width W1, a portion of the tail portion 1302 not overlapping the first contact portion 1506 has a second width W2, and the first width W1 is greater than the second width W2. The design is also used for preventing the phenomena of electric leakage and the like and improving the reliability of the product.
Please refer to the corresponding contents of the foregoing embodiments for more details regarding the structure, properties and advantages of the LED chip provided by the present embodiment.
Another embodiment of the invention provides another LED chip, please refer to fig. 30 to 34 in combination, wherein fig. 34 is a schematic top view projection diagram of each structure of the entire LED chip. Also, its cross-sectional structure may incorporate the cross-sectional view of fig. 12 of the previous embodiment.
The structure of the LED chip provided in this embodiment is the same as that of the previous embodiment, and therefore, reference may be made to the corresponding content of the previous embodiment.
In this embodiment, as shown in fig. 30, the concave notch 1111 in the top view projection of the first mesa structure 111 is different from the previous embodiment in that the concave notch 1111 in the present embodiment is disposed at the upper left corner position of the top view projection of the first mesa structure 111 in fig. 30.
The top projection of the second mesa structure 112 has a corner notch 1121, and the position of the corner notch 1121 is different from that of the previous embodiment, and it is only disposed at the lower left corner of the first mesa structure 111 in fig. 30.
As shown in fig. 31, in this embodiment, only one cross current block 130 is provided, which includes a head portion 1301 and a tail portion 1302, and in contrast to fig. 26, the width of the tail portion 1302 is smaller than the width of the head portion 1301.
Accordingly, as shown in fig. 32, there is only one bridging conductive block 150, which is located at the opposite edge of the top projection area. The jumper conductive block 150 includes a junction 1502, a first contact 1508, and a second contact 1509. The first end 1508 is linear, while the second contact 1509 not only connects to the lower corner of the junction 1502, but in this embodiment the second contact 1509 has a corner structure itself.
In this embodiment, only one bridging current blocking block 130 and bridging conductive block 150 are designed, and meanwhile, the concave notch 1111 and the corner notch 1121 are disposed at different corner positions of the product, one at the upper corner and one at the lower corner, which also helps to expand the current and improve the reliability of the product.
Referring to fig. 33, a schematic view of the structures of fig. 31 and 32 after lamination is shown. A junction 1502 and a first contact 1508 are included within the head 1301 and tail 1302, respectively, of the cross-over current block 130. In a top view projection, the junction 1502 falls within the head 1301, the first contact 1508 is located within the tail 1302, and the second contact 1509 does not overlap the cross-over current block 130.
Referring to fig. 33, a portion of the head 1301 not overlapping the knot portion 1502 has a first width W1, a portion of the tail 1302 not overlapping the first contact portion 1508 has a second width W2, and the first width W1 is greater than the second width W2. The design is also used for preventing the phenomena of electric leakage and the like and improving the reliability of the product.
Please refer to the corresponding contents of the foregoing embodiments for more details regarding the structure, properties and advantages of the LED chip provided by the present embodiment.
The embodiment of the invention also provides an LED chip packaging module (not shown), which can comprise any one of the LED chips in the above embodiments, so that the reliability of the LED chip packaging module is improved.
The embodiment of the invention also provides a display device, which can comprise any one of the LED chips in the embodiments, and the LED chip is used as a backlight source chip of a backlight module of the display device, so that the reliability of the display device is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. An LED chip, comprising:
a substrate;
a first mesa structure on the substrate;
a second mesa structure on the substrate;
at least one crossover current block covering a portion of the upper surface and a portion of the side surfaces of the first mesa structure and covering a portion of the recess between the first and second mesa structures;
the number of the cross-over conductive blocks is the same as that of the cross-over current blocking blocks, the main body part of the cross-over conductive block is positioned on the cross-over current blocking blocks, the first ends of the cross-over conductive blocks are electrically connected with the top layer of the first mesa structure, and the second ends of the cross-over conductive blocks are electrically connected with the bottom layer of the second mesa structure;
a first conductive pad located over the first mesa structure;
a second conductive pad located above the second mesa structure;
the top view projection of the cross-over current block has a head and a tail;
the planar projection of the bridging conductive block is provided with a first contact part, a junction part and a second contact part;
the knot portion is within the head portion and the first contact portion is within the tail portion;
the portion of the head portion not overlapping the junction portion has a first width, and the portion of the tail portion not overlapping the first contact portion has a second width, the first width being greater than the second width.
2. The LED chip of claim 1, wherein said first width is in the size of 3 μ ι η to 100 μ ι η.
3. The LED chip of claim 2, wherein said second width is sized to be greater than or equal to 0 μ ι η and less than or equal to up to 30 μ ι η.
4. The LED chip of claim 1, wherein said head portion has a width that is greater than 1.5 times a width of said tail portion.
5. The LED chip of claim 1, wherein said bridging conductive bumps are two and located at two opposite edges of the entire top-view projection area.
6. The LED chip of claim 1 or 5, wherein a top view projection of said bridging conductive block has no overlap with a top view projection of said first and second conductive pads.
7. The LED chip of claim 5, wherein a portion of the top view projection of said second conductive pad is sandwiched between two of said bridging conductive bumps, and wherein the top view shape of said first conductive pad and the top view shape of said second conductive pad are substantially symmetrical.
8. The LED chip of claim 1, wherein said junction has a width greater than a width of said first contact; the width of the junction portion is greater than the width of the second contact portion.
9. The LED chip of claim 1, wherein a bisector of said junction and a bisector of said first contact coincide with a first line, and wherein a bisector of said second contact is a second line, said first line being parallel to said second line, said second contact connecting an outer corner of said junction; or the bisector of the junction and the bisector of the second contact part are superposed on a first straight line, the bisector of the first contact part is a second straight line, the first straight line is parallel to the second straight line, and the first contact part is connected with the inner corner of the junction.
10. The LED chip of claim 9, further comprising:
a first current spreading layer located over the first mesa structure, the first conductive pad located over the first current spreading layer, the cross-over conductive block electrically connected to a top layer of the first mesa structure by connecting the first current spreading layer;
a second current spreading layer over the second mesa structure, the second conductive pad over the second current spreading layer;
the top projection of the bridging conductive block and the top projection of the second current spreading layer have no overlapping part.
11. The LED chip of claim 10, further comprising a first DBR reflective layer covering said first and second current spreading layers; the first conductive pad is located on the first DBR reflective layer, and the first conductive pad penetrates through the first DBR reflective layer to electrically connect to a bottom layer of the first mesa structure; the second conductive pad is located on the first DBR reflective layer and extends through the first DBR reflective layer to electrically connect the second current spreading layer; the first DBR reflective layer also serves as a passivation protection layer.
12. The LED chip of claim 10, further comprising a built-in current block located between said second mesa structure and a second current spreading layer; the top-view projection of the built-in current block comprises a middle part and two side parts connecting the middle part, and the width of the middle part is larger than that of the side parts.
13. The LED chip of claim 12, further comprising a second conductive bump above said built-in current block and on said second current spreading layer, said second conductive pad electrically connecting said second current spreading layer by connecting said second conductive bump; a top view projection of the second conductive bump falls within a top view projection of the built-in current block.
14. The LED chip of claim 1, further comprising a first conductive block, a top view projection of said first mesa structure top layer having an internal recess, a top view projection of said first conductive block falling within said internal recess of said first mesa structure.
15. The LED chip of claim 14, wherein said indentation has a funnel-like shape in plan view, and said first conductive bump has a round or pin-like shape with rounded ends in plan view.
16. The LED chip of claim 1, wherein a top view projection of the top layer of the second mesa structure is a chamfered rectangle with two corner notches, the corner notches facing the first mesa structure, the two corner notches being symmetrical; the corner gap is matched with the bridging conductive block.
17. The LED chip of claim 13, wherein said second conductive mass comprises a core and two wings on either side of said core; the first DBR reflective layer has a first via and a second via through itself; the second via is located above the middle of the core of the second conductive block.
18. The LED chip of claim 1, further comprising a second DBR reflective layer, said second DBR reflective layer being located on the back side of said substrate.
19. An LED chip package module, comprising the LED chip as claimed in any one of claims 1 to 18.
20. A display device, comprising the LED chip according to any one of claims 1 to 18 as a backlight source chip of a backlight module of the display device.
CN202011282176.2A 2020-11-16 2020-11-16 LED chip, LED chip packaging module and display device Active CN112531084B (en)

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CN202210535064.6A CN115000265A (en) 2020-11-16 2020-11-16 LED chip and display device
CN202210535471.7A CN114824011A (en) 2020-11-16 2020-11-16 LED chip, LED chip packaging module and display device
CN202210535435.0A CN114914340A (en) 2020-11-16 2020-11-16 LED chip, LED chip packaging module and display device
CN202011282176.2A CN112531084B (en) 2020-11-16 2020-11-16 LED chip, LED chip packaging module and display device
CN202210535067.XA CN115000261A (en) 2020-11-16 2020-11-16 LED chip, LED chip packaging module and display device
US17/454,895 US20220158028A1 (en) 2020-11-16 2021-11-15 Light-emitting device, light-emitting module including the same and display apparatus including the same
KR1020210156854A KR20220066851A (en) 2020-11-16 2021-11-15 Light-emitting device, light-emitting module including the same and display apparatus including the same

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CN202210535064.6A Division CN115000265A (en) 2020-11-16 2020-11-16 LED chip and display device
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CN115000265A (en) 2022-09-02

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