KR20020061811A - Manufacturing method for chip scale package - Google Patents
Manufacturing method for chip scale package Download PDFInfo
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- KR20020061811A KR20020061811A KR1020010002827A KR20010002827A KR20020061811A KR 20020061811 A KR20020061811 A KR 20020061811A KR 1020010002827 A KR1020010002827 A KR 1020010002827A KR 20010002827 A KR20010002827 A KR 20010002827A KR 20020061811 A KR20020061811 A KR 20020061811A
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- South Korea
- Prior art keywords
- semiconductor chip
- carrier film
- scale package
- chip scale
- wire
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title description 12
- 239000002184 metal Substances 0.000 claims abstract description 32
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 239000011347 resin Substances 0.000 claims abstract description 15
- 229920005989 resin Polymers 0.000 claims abstract description 15
- 239000008393 encapsulating agent Substances 0.000 claims description 10
- 238000001465 metallisation Methods 0.000 claims 2
- 238000007789 sealing Methods 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 5
- 238000002161 passivation Methods 0.000 abstract 2
- 229910000679 solder Inorganic materials 0.000 description 12
- 238000005538 encapsulation Methods 0.000 description 9
- 230000001681 protective effect Effects 0.000 description 7
- 238000011109 contamination Methods 0.000 description 5
- 239000012790 adhesive layer Substances 0.000 description 3
- 229920001971 elastomer Polymers 0.000 description 3
- 239000000806 elastomer Substances 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000012050 conventional carrier Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
본 발명은 칩 스케일 패키지(CSP; Chip Scale Package)에 관한 것으로서, 더욱 상세하게는 수지 봉지재에 의한 캐리어 필름의 볼 패드의 오염을 방지하기 위한 칩 스케일 패키지 제조 방법에 관한 것이다.The present invention relates to a chip scale package (CSP), and more particularly, to a method of manufacturing a chip scale package for preventing contamination of a ball pad of a carrier film by a resin encapsulant.
오늘날 반도체 칩 패키지는 더욱 경량화, 소형화, 고속화, 다기능화, 고성능화 되고 높은 신뢰성을 가지며 저렴하게 제조될 수 있는 제품의 개발을 위하여 계속적인 발전을 거듭해 왔다. 이와 같은 제품 설계의 목표 달성을 가능하게 하는 중요한 기술 중의 하나가 바로 BGA(Ball Grid Array) 패키지 기술이다. BGA 패키지는 통상적인 플라스틱 패키지에 비하여 주기판에 대한 실장면적을 축소시킬 수 있고, 전기적 특성이 우수하다는 장점 등을 갖고 있다.Today's semiconductor chip packages continue to evolve to develop products that are lighter, smaller, faster, more versatile, more powerful, more reliable and more affordable. One important technology that enables us to achieve these product design goals is the Ball Grid Array (BGA) packaging technology. The BGA package has a merit that it can reduce the mounting area on the main board and excellent electrical characteristics, compared to the conventional plastic package.
BGA 패키지는 통상적인 플라스틱 패키지와 달리 리드프레임(lead frame) 대신에 인쇄회로기판을 사용한다. 인쇄회로기판은 반도체 칩이 접착되는 면의 반대쪽 전면(全面)이 솔더 볼(solder ball)을 배치할 수 있는 영역으로 제공될 수 있다. 따라서, 인쇄회로기판을 이용하여 제조되는 BGA 패키지는 주기판에 대한 실장 밀도 면에서 유리하게 된다. 그러나, BGA 패키지는 인쇄회로기판의 크기를 축소하는 데 근본적으로 한계를 갖고 있다. 즉, 반도체 칩을 실장하기 위하여 회로 배선이 형성되지 않은 영역을 필요로 하기 때문에, 인쇄회로기판의 크기는 여전히 반도체 칩의 크기보다 클 수밖에 없다. 이러한 사정에서 제안된 것이 소위 칩 스케일 패키지이다. 칩 스케일 패키지의 일 예를 소개하기로 한다.Unlike conventional plastic packages, BGA packages use printed circuit boards instead of lead frames. The printed circuit board may be provided as an area in which the entire surface opposite to the surface to which the semiconductor chip is bonded may be arranged with the solder ball. Therefore, a BGA package manufactured using a printed circuit board is advantageous in terms of mounting density for the main board. However, BGA packages are fundamentally limited in reducing the size of printed circuit boards. In other words, the size of the printed circuit board is still larger than the size of the semiconductor chip because the area in which the circuit wiring is not formed is required to mount the semiconductor chip. Proposed in this context is the so-called chip scale package. An example of a chip scale package will be introduced.
도 1은 칩 스케일 패키지의 일 예를 나타낸 단면도이고, 도 2는 도 1의 칩 스케일 패키지 제조 공정 중에 볼 패드의 오염이 발생된 상태를 나타낸 단면도이다.1 is a cross-sectional view illustrating an example of a chip scale package, and FIG. 2 is a cross-sectional view illustrating a state in which contamination of a ball pad occurs during the chip scale package manufacturing process of FIG. 1.
도 1을 참조하면, 이 칩 스케일 패키지(100)는 활성면(active surface)의 중앙부에 전극패드(12)들이 형성된 반도체 칩(10) 상에 탄성 중합체(20; elastomer)가 개재되어 캐리어 필름(30)이 부착되며, 그 캐리어 필름(30)에 솔더 볼(70)이 부착된 구조이다.Referring to FIG. 1, in the chip scale package 100, an elastomer 20 is interposed on a semiconductor chip 10 on which electrode pads 12 are formed at a center of an active surface. 30 is attached, and the solder ball 70 is attached to the carrier film 30.
반도체 칩(10)이 부착되는 캐리어 필름(30)은 베이스 필름(32)의 상면에 접속패드(44)와 볼 패드(42)들을 포함하는 금속배선(40)이 접착층(34)에 의해 부착되어 있고, 접속패드(44)와 볼 패드(42)를 제외한 금속배선(40)은 솔더 레지스트(solder resist)로 형성되는 보호막(36)으로 덮여져 보호되며, 각각의 볼 패드(42)에는 솔더 볼(70)이 부착되는 구조로서, 반도체 칩(10)의 전극패드(12)들은 캐리어 필름(30)에 형성된 윈도우(window; 38)에 위치된다.In the carrier film 30 to which the semiconductor chip 10 is attached, a metal wiring 40 including connection pads 44 and ball pads 42 is attached to the upper surface of the base film 32 by an adhesive layer 34. The metal wiring 40 except for the connection pad 44 and the ball pad 42 is covered and protected by a protective film 36 formed of a solder resist, and each ball pad 42 has solder balls. As a structure to which the 70 is attached, the electrode pads 12 of the semiconductor chip 10 are positioned in a window 38 formed in the carrier film 30.
반도체 칩(10)은 전극패드(12)가 캐리어 필름(30)의 접속패드(44)와 도전성 금속선(50)으로 와이어 본딩(wire bonding)되고, 금속배선(40)에 의해 최종적으로 솔더 볼(70)과 전기적으로 연결된다. 도전성 금속선(50)과 그 접합 부분이 수지 봉지재로 형성된 봉지(60)부에 의해 외부 환경으로부터 보호된다.In the semiconductor chip 10, the electrode pads 12 are wire bonded to the connection pads 44 of the carrier film 30 and the conductive metal wires 50, and finally the solder balls are formed by the metal wires 40. 70) is electrically connected. The conductive metal wire 50 and its joined portion are protected from the external environment by the encapsulation 60 portion formed of the resin encapsulation material.
이와 같은 구조의 칩 스케일 패키지는 와이어 본딩을 적용하기 때문에 기존의 빔 리드를 갖는 캐리어 필름을 이용하여 갱-본딩(gang bonding)을 적용하는 형태의 칩 스케일 패키지에서 반도체 칩의 전극패드들이 일정한 간격으로 형성되어 있어야 하는 제한을 해소할 수 있다. 그러나, 와이어 본딩 과정에서 와이어 루프(wire loop)가 캐리어 필름의 표면보다 높게 형성되고 수지 봉지재가 도포되는 영역 또한 캐리어 필름의 표면보다 높게 형성되며, 상대적으로 솔더 레지스터로 형성되는 보호막의 두께가 얇기 때문에, 수지 봉지 과정에서 도 2와 같이 액상의 봉지재(61)가 볼 패드(42)들이 형성된 영역까지 흘러들어 해당 볼 패드(42)들을 오염시킬 수 있다. 이에 따라, 볼 패드들 위에 침범된 수지 봉지재로 인하여 볼 패드와 솔더 볼의 접착 불량이 발생되는 결과를 가져올 수 있다. 즉, 솔더 볼이 볼 패드에 부착되지 않는 불량이 발생될 수 있으며, 또는 불완전하게 솔더 볼이 부착되는 등의 불량이 발생될 수 있다.In the chip scale package having the above structure, wire bonding is applied, so that electrode pads of the semiconductor chip are uniformly spaced in the chip scale package in which gang bonding is applied by using a carrier film having a conventional beam lead. Eliminate the restrictions that must be formed. However, in the wire bonding process, the wire loop is formed higher than the surface of the carrier film, the area where the resin encapsulant is applied is also formed higher than the surface of the carrier film, and the protective film formed of the solder resistor is relatively thin. In the resin encapsulation process, as shown in FIG. 2, the liquid encapsulant 61 may flow into a region where the ball pads 42 are formed to contaminate the ball pads 42. As a result, a poor adhesion between the ball pad and the solder ball may occur due to the resin encapsulation material impinged on the ball pads. That is, a defect in which the solder ball does not adhere to the ball pad may occur, or a defect such as incomplete attachment of the solder ball may occur.
따라서 본 발명의 목적은 봉지 과정에서 수지 봉지재에 의한 볼 패드 오염을 방지할 수 있는 칩 스케일 패키지 제조 방법을 제공하는 데 있다.Accordingly, an object of the present invention is to provide a chip scale package manufacturing method capable of preventing ball pad contamination by a resin encapsulant during encapsulation.
도 1은 칩 스케일 패키지의 일 예를 나타낸 단면도,1 is a cross-sectional view showing an example of a chip scale package;
도 2는 도 1의 칩 스케일 패키지 제조 공정 중에 볼 패드의 오염이 발생된 상태를 나타낸 단면도,2 is a cross-sectional view illustrating a state in which contamination of a ball pad occurs during the chip scale package manufacturing process of FIG. 1;
도 3과 도 4는 본 발명에 따른 칩 스케일 패키지 제조 방법의 공정도이다.3 and 4 are process diagrams of the chip scale package manufacturing method according to the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10; 반도체 칩12; 전극패드10; Semiconductor chip 12; Electrode pad
20; 탄성 중합체30; 캐리어 필름20; Elastomer 30; Carrier film
32; 베이스 필름34; 접착층32; Base film 34; Adhesive layer
36; 보호막38; 윈도우36; Protective film 38; window
40; 금속배선42; 볼 패드40; Metal wiring 42; Ball pad
44; 접속패드50; 본딩 와이어44; A connection pad 50; Bonding wire
60,65; 봉지부100; 칩 스케일 패키지60,65; Encapsulation unit 100; Chip scale package
이와 같은 목적을 달성하기 위한 본 발명에 따른 칩 스케일 패키지 제조 방법은, ⒜ 베이스 필름에 금속배선이 형성된 캐리어 필름에 복수의 전극패드를 갖는 반도체 칩을 부착시키는 단계, ⒝ 반도체 칩의 전극패드와 금속배선을 도전성 금속선으로 와이어 본딩시키는 단계, 및 ⒞ 도전성 금속선과 그 접합 부분을 봉지하고 금속배선의 볼 패드가 개방되도록 하여 반도체 칩과 캐리어 필름의 상부를 수지 봉지재로 프린팅(printing)하는 단계를 포함하는 것을 특징으로 한다.The chip scale package manufacturing method according to the present invention for achieving the above object, the step of attaching a semiconductor chip having a plurality of electrode pads to a carrier film formed with metal wiring on the base film, (⒝) electrode pad and metal of the semiconductor chip Wire bonding the wiring with a conductive metal wire, and (b) printing the upper portion of the semiconductor chip and the carrier film with a resin encapsulant by encapsulating the conductive metal wire and the bonding portion thereof and opening the ball pad of the metal wiring. Characterized in that.
이하 첨부 도면을 참조하여 본 발명에 따른 칩 스케일 패키지 제조 방법을 보다 상세하게 설명하고자 한다.Hereinafter, a method of manufacturing a chip scale package according to the present invention will be described in detail with reference to the accompanying drawings.
도 3과 도 4는 본 발명의 칩 스케일 패키지 제조 방법에 따른 공정도이다.3 and 4 are process charts according to the chip scale package manufacturing method of the present invention.
도 3을 참조하면, 먼저, 폴리이미드(polyimide) 재질의 베이스 필름(32)의상면에 구리(Cu)와 같은 재질로 볼 패드(42)와 접속패드(44)를 포함하는 금속배선(40)이 접착층(34)에 의해 부착되어 있는 캐리어 필름(30)과, 활성면 중앙에 전극패드(12)들이 형성된 반도체 칩(10)을 준비한다. 이 캐리어 필름(30)은 종래의 캐리어 필름에서 볼 수 있는 솔더 레지스트로 형성되는 보호막을 갖지 않는다. 캐리어 필름(30)은 반도체 칩(10)의 전극패드(12)의 형성 위치에 따라 그에 대응되는 위치에 윈도우(38)가 형성된다, 여기서 캐리어 필름(30)은 중앙부에 윈도우(38)가 형성된 것이다.Referring to FIG. 3, first, a metal wiring 40 including a ball pad 42 and a connection pad 44 made of a material such as copper (Cu) on an upper surface of a polyimide base film 32. The carrier film 30 attached by this adhesive layer 34 and the semiconductor chip 10 in which the electrode pads 12 were formed in the center of the active surface are prepared. This carrier film 30 does not have a protective film formed of a soldering resist found in the conventional carrier film. The carrier film 30 has a window 38 formed at a position corresponding thereto according to the formation position of the electrode pad 12 of the semiconductor chip 10, where the carrier film 30 has a window 38 formed at the center thereof. will be.
다음으로 준비된 캐리어 필름(30)과 반도체 칩(10)을 탄성 중합체(20)를 개재하여 부착시킨다. 반도체 칩(10)의 활성면이 전극패드(12)가 캐리어 필름(30)의 윈도우(38)에 위치하도록 캐리어 필름(30)의 금속배선(40)이 형성된 반대쪽 면에 부착된다.Next, the prepared carrier film 30 and the semiconductor chip 10 are attached to each other via the elastomer 20. The active surface of the semiconductor chip 10 is attached to the opposite surface on which the metal wire 40 of the carrier film 30 is formed so that the electrode pad 12 is located in the window 38 of the carrier film 30.
다음에 반도체 칩(10)의 전극패드(12)와 그에 대응되는 금속배선(40)을 도전성 금속선(50)으로 와이어 본딩시킨다. 도전성 금속선(50)은 캐리어 필름(30)의 윈도우(38)를 거쳐 금속배선(40)에 접합된다. 이때, 도전성 금속선(50)의 와이어 루프의 최상위 점은 캐리어 필름(30)보다는 높은 위치에 있게 된다.Next, the electrode pad 12 of the semiconductor chip 10 and the metal wiring 40 corresponding thereto are wire bonded to the conductive metal wire 50. The conductive metal wire 50 is bonded to the metal wire 40 via the window 38 of the carrier film 30. At this time, the uppermost point of the wire loop of the conductive metal wire 50 is at a higher position than the carrier film 30.
그 다음에 도전성 금속선(50)과 그 접합 부분을 봉지하고 금속배선(40)의 볼 패드(42)가 개방되도록 하여 반도체 칩(10)과 캐리어 필름(30)의 상부를 수지 봉지재로 프린팅(printing)하여 봉지부(60)를 형성시킨다. 이에 따라, 도전성 금속선(50)과 그 접합 부위 및 반도체 칩(10)의 활성면이 봉지됨과 동시에 금속배선(40)이 수지 봉지재로 덮여 보호되며 솔더 볼(70)이 부착될 수 있도록 볼패드(42)의 개방이 이루어진다.Then, the conductive metal wire 50 and the bonding portion thereof are sealed, and the ball pad 42 of the metal wire 40 is opened to print the upper portion of the semiconductor chip 10 and the carrier film 30 with a resin encapsulant ( printing to form the encapsulation unit 60. Accordingly, the conductive metal wire 50, its junction portion, and the active surface of the semiconductor chip 10 are encapsulated, and the metal wire 40 is covered with a resin encapsulant and protected, and the ball pad can be attached to the solder ball 70. Opening of 42 is made.
이상과 같은 본 발명에 따른 칩 스케일 패키지 제조 방법은 수지 봉지 과정에서 수지 봉지재를 금속배선을 보호하는 보호막의 역할을 하고 또한 솔더 볼이 부착될 수 있도록 볼 패드를 개방시킨다.The chip scale package manufacturing method according to the present invention as described above serves as a protective film to protect the metal encapsulation of the resin encapsulant in the resin encapsulation process, and opens the ball pad so that solder balls can be attached.
따라서, 본 발명에 의한 칩 스케일 패키지 제조 방법에 따르면, 보호막이 형성되지 않은 캐리어 필름을 이용하여 와이어 본딩 후 수지 봉지재로 보호막을 형성하여 볼 패드의 오염을 방지하여 품질을 향상시킬 수 있다. 또한, 솔더 레지스트 도포에 의한 테이프 제조 비용 상승을 억제할 수 있다.Therefore, according to the method of manufacturing a chip scale package according to the present invention, a protective film is formed of a resin encapsulant after wire bonding using a carrier film on which a protective film is not formed, thereby preventing contamination of a ball pad, thereby improving quality. In addition, an increase in tape manufacturing cost due to solder resist coating can be suppressed.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010002827A KR20020061811A (en) | 2001-01-18 | 2001-01-18 | Manufacturing method for chip scale package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020010002827A KR20020061811A (en) | 2001-01-18 | 2001-01-18 | Manufacturing method for chip scale package |
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| Publication Number | Publication Date |
|---|---|
| KR20020061811A true KR20020061811A (en) | 2002-07-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010002827A KR20020061811A (en) | 2001-01-18 | 2001-01-18 | Manufacturing method for chip scale package |
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| Country | Link |
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| KR (1) | KR20020061811A (en) |
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2001
- 2001-01-18 KR KR1020010002827A patent/KR20020061811A/en not_active Application Discontinuation
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