CN103354228A - Semiconductor packaging part and manufacturing method thereof - Google Patents
Semiconductor packaging part and manufacturing method thereof Download PDFInfo
- Publication number
- CN103354228A CN103354228A CN2013102885895A CN201310288589A CN103354228A CN 103354228 A CN103354228 A CN 103354228A CN 2013102885895 A CN2013102885895 A CN 2013102885895A CN 201310288589 A CN201310288589 A CN 201310288589A CN 103354228 A CN103354228 A CN 103354228A
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- chip
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- semiconductor package
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- mold compound
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a semiconductor packaging part and a manufacturing method thereof. The semiconductor packaging part comprises a substrate, a chip positioned on the substrate, a bonding layer placed between the substrate and the chip, a conductive structure dispersed in the bonding layer and a conductive molding compound, wherein the chip is attached to the substrate via the bonding layer, the chip is electrically connected with the substrate via the conductive structure, and the conductive molding compound packages the chip and is connected to the ground. According to the semiconductor packaging part of the invention, the chip is prevented from interference of electromagnetic waves, and extra technology is not required.
Description
Technical field
The application relates to a kind of semiconductor package part and manufacture method thereof, and more particularly, the application relates to a kind of semiconductor package part and manufacture method thereof of improving electromagnetic wave shielding, signal integrity and radiating effect.
Background technology
For many integrated circuit (IC) chip, use more and more high-frequency signal.Yet high-frequency signal often is accompanied by the problem of signal integrity and electromagnetic wave shielding.In addition, for the larger semiconductor package part of power consumption, how to dispel the heat also is a difficult problem, for example, often dispels the heat with thermal paste etc. in the prior art.
Fig. 1 is the schematic diagram according to the semiconductor package part of prior art.With reference to Fig. 1, comprise according to the semiconductor package part of prior art: substrate 10; Chip 11 is positioned in the substrate 10, invests substrate 10 by adhesive layer 20, and is electrically connected with lead frame 12 by bonding wire 14; Encapsulating resin 15, encapsulate chip 11; Screen 16 is formed on the outer surface of encapsulating resin 15, is subject to Electromagnetic Interference to prevent chip 10.
In addition, semiconductor package part according to prior art also comprises ground pad 18, vertical conductive structure 17 and conductive weld 19, wherein, vertically conductive structure 17 provides electrical connection between ground pad 18 and screen 16, and a part and conductive weld 19 by vertical conductive structure 17, screen 16 are electrically connected to ground lead 13 with ground pad 18.Therefore, although screen 16 only is formed on the outer surface of encapsulating resin 15, can form from ground pad 18 to ground lead by screen 16 13 path.
That is, according to the semiconductor package part of prior art, in order to prevent electromagnetic interference, need to form independent screen 16 at the outer surface of encapsulating resin 15, thereby need independent manufacturing process, increase manufacturing cost.
Summary of the invention
In order to overcome the problems of the prior art, the invention provides a kind of semiconductor package part, described semiconductor package part comprises: substrate; Chip is positioned in the substrate; Adhesive layer between substrate and chip, invests substrate with chip; Conductive structure is dispersed in the adhesive layer, and chip is electrically connected with substrate; Conduction mold compound, encapsulate chip and ground connection.
According to embodiments of the invention, described semiconductor package part also comprises the ground pad that is arranged in substrate and the ground connection soldered ball that is positioned at the substrate below, and described conduction mold compound is electrically connected to the ground connection soldered ball via ground pad.Described adhesive layer is made by insulating material, prevents that chip is electrically connected with the conduction mold compound.
According to embodiments of the invention, described adhesive layer is made by Parylene.Described conduction mold compound is made or is made by epoxy resin and conductive compound by epoxy resin and metallic conduction particle.
The present invention also provides a kind of semiconductor chip, and described semiconductor package part comprises: substrate; Chip is positioned in the substrate; Bonding wire is electrically connected to substrate with chip; Insulating barrier covers chip and bonding wire; The conduction mold compound, encapsulate chip and ground connection, wherein, insulating barrier prevents that chip and bonding wire are electrically connected with the conduction mold compound.
The invention provides a kind of manufacture method of semiconductor package part, described manufacture method may further comprise the steps: substrate is provided; By adhesive layer chip is invested substrate, and by the conductive structure that is arranged in the adhesive layer chip is electrically connected with substrate; With conduction mold compound encapsulate chip, and described conduction mold compound ground connection.
The present invention also provides a kind of manufacture method of semiconductor package part, and the manufacture method of described semiconductor package part may further comprise the steps: substrate is provided; With chip laminate above substrate; By bonding wire chip is electrically connected to substrate; Be coated with insulating layer coating at chip and bonding wire; With conduction mold compound encapsulate chip, and described conduction mold compound ground connection.
By adopting the conduction mold compound to come encapsulate chip, the back side of chip is electrically connected with ground pad, thereby can prevents that chip is subjected to Electromagnetic Interference, and can quick heat radiating.Therefore, according to the present invention, do not need other structure to prevent electromagnetic interference, simplify the structure, reduced manufacturing cost.
Description of drawings
Describe in conjunction with the drawings embodiments of the invention in detail, many feature and advantage of the present invention will become clearer, in the accompanying drawings:
Fig. 1 is the schematic diagram according to the semiconductor package part of prior art;
Fig. 2 is the cutaway view of the semiconductor package part of the first exemplary embodiment according to the present invention;
Fig. 3 is the cutaway view of the semiconductor package part of the second exemplary embodiment according to the present invention.
Embodiment
Hereinafter, describe with reference to the accompanying drawings semiconductor package part according to the embodiment of the invention in detail.
Fig. 2 is the cutaway view of the semiconductor package part of the first exemplary embodiment according to the present invention.With reference to Fig. 2, the semiconductor package part of the first exemplary embodiment comprises according to the present invention: substrate 100; Chip 130 is positioned in the substrate 100, invests substrate 100 by adhesive layer 150; Conductive structure 140 is dispersed in the adhesive layer 150, and chip 130 is electrically connected with conductive welding disk in the substrate 100; Conduction mold compound 160, encapsulate chip 130, thus protection chip 130 is avoided outside damage; Conductive weld is positioned at substrate 100 belows, is used for chip 130 is electrically connected to external circuit.
According to the first exemplary embodiment of the present invention, conduction mold compound 160 can be made by epoxy resin and metallic conduction particle, perhaps can be made by epoxy resin and other conductive compound.Conduction mold compound 160 is electrically connected to ground connection soldered ball 110 with the back side of chip 130 via ground pad 120, thereby as the electromagnetic wave shielding assembly of semiconductor package part and can play the effect of good heat dissipation path.That is, conduction mold compound 160 is connected to ground connection soldered ball 110 with the surface electrical with the surface opposite that invests substrate 100 of chip 130.Wherein, ground pad 120 is arranged in substrate 100, and ground connection soldered ball 110 is positioned at substrate 100 belows, and ground connection soldered ball 110 is not electrically connected with chip 130.
According to the semiconductor package part of the first exemplary embodiment of the present invention, adhesive layer 150 is formed by insulating material, thereby the surface that is electrically connected with substrate 100 that prevents chip 130 is electrically connected with mold compound 160.
The semiconductor package part of the first exemplary embodiment is by adopting conductive compound to seal above chip according to the present invention, conductive compound can play the effect of electromagnetic wave shielding and heat radiation, and do not need picture independent screen of the prior art, thereby can adopt simple manufacturing process to obtain semiconductor package part.
The below will describe the method for making the semiconductor package part of the first exemplary embodiment according to the present invention in detail, said method comprising the steps of: substrate 100 is provided; By adhesive layer 150 chip 130 is invested substrate 100, and by the conductive structure 140 that is arranged in the adhesive layer 150 chip 130 is electrically connected with substrate 100; With conduction mold compound 160 encapsulate chip 130, and described conduction mold compound ground connection.
Fig. 3 is the cutaway view of the semiconductor package part of the second exemplary embodiment according to the present invention.With reference to Fig. 3, the semiconductor package part of the second exemplary embodiment comprises according to the present invention: substrate 100; Chip 130 is layered in substrate 100 tops, and chip 130 is electrically connected to conductive welding disk in the substrate 100 by bonding wire 170; Insulating barrier 180 covers chip 130 and bonding wire 170; Conduction mold compound 160, encapsulate chip 130, thus protection chip 130 is avoided outside damage.
The semiconductor package part of the second exemplary embodiment can comprise a plurality of chips according to the present invention, for example, can comprise two chips.
According to the second exemplary embodiment of the present invention, insulating barrier 180 can be formed by Parylene, thereby prevents that chip 130, bonding wire 170 are electrically connected with conduction mold compound 160.
According to the second exemplary embodiment of the present invention, the outer surface of the insulating barrier 180 of covering chip 130 (namely, surface with the surface opposite of insulating barrier 180 contact chips 130), conduction mold compound 160, ground pad 120 are electrically connected to ground connection soldered ball 110, thereby prevent that semiconductor package part is subjected to electromagnetic interference, and can be used as good heat dissipation path.Wherein, ground pad 120 is arranged in substrate 100, and ground connection soldered ball 110 is positioned at substrate 100 belows, and ground connection soldered ball 110 is not electrically connected with chip 130.
In addition, according to the second exemplary embodiment of the present invention, semiconductor package part can also comprise the through hole 190 that passes insulating barrier 180 formation.Conduction mold compound 160 filling vias 190 are so the outer surface of insulating barrier 180 is electrically connected to ground connection soldered ball 110, thereby prevents that chip 130 is subjected to Electromagnetic Interference via conduction mold compound 160, through hole 190, ground pad 120.
The below will describe the manufacture method of the semiconductor package part of the second exemplary embodiment according to the present invention in detail, and described manufacture method may further comprise the steps: substrate 100 is provided; Chip 130 is layered in substrate 100 tops; By bonding wire 170 chip 130 is electrically connected to substrate 100; Be coated with insulating layer coating 180 at chip 100 and bonding wire 170; With conduction mold compound 160 encapsulate chip 130, and described conduction mold compound ground connection.
According to semiconductor package part of the present invention and manufacture method thereof, come encapsulate chip by adopting the conduction mold compound, the back side of chip is electrically connected with ground pad, thereby can prevents that chip is subjected to Electromagnetic Interference, and can quick heat radiating.Therefore, according to the present invention, do not need other structure to prevent electromagnetic interference, simplify the structure, reduced manufacturing cost.
Abovely exemplarily show the present invention with reference to accompanying drawing, scope of the present invention is limited by claim and equivalent thereof.
Claims (10)
1. semiconductor package part is characterized in that described semiconductor package part comprises:
Substrate;
Chip is positioned in the substrate;
Adhesive layer between substrate and chip, invests substrate with chip;
Conductive structure is dispersed in the adhesive layer, and chip is electrically connected with substrate;
Conduction mold compound, encapsulate chip and ground connection.
2. semiconductor package part according to claim 1 is characterized in that described semiconductor package part also comprises the ground pad that is arranged in substrate and the ground connection soldered ball that is positioned at the substrate below, and described conduction mold compound is electrically connected to the ground connection soldered ball via ground pad.
3. semiconductor package part according to claim 1 is characterized in that described adhesive layer made by insulating material, prevents that chip is electrically connected with the conduction mold compound.
4. semiconductor package part according to claim 3 is characterized in that described adhesive layer made by Parylene.
5. semiconductor package part according to claim 1 is characterized in that described conduction mold compound made or made by epoxy resin and conductive compound by epoxy resin and metallic conduction particle.
6. semiconductor chip is characterized in that described semiconductor package part comprises:
Substrate;
Chip is positioned in the substrate;
Bonding wire is electrically connected to substrate with chip;
Insulating barrier covers chip and bonding wire;
The conduction mold compound, encapsulate chip and ground connection,
Wherein, insulating barrier prevents that chip and bonding wire are electrically connected with the conduction mold compound.
7. semiconductor package part according to claim 6 is characterized in that described insulating barrier made by Parylene.
8. semiconductor package part according to claim 6 is characterized in that described semiconductor package part also comprises the ground pad that is arranged in substrate and the ground connection soldered ball that is positioned at the substrate below, and described conduction mold compound is electrically connected to ground pad and ground connection soldered ball.
9. semiconductor package part according to claim 6 is characterized in that described semiconductor package part also comprises the through hole that passes insulating barrier, and described conduction mold compound is electrically connected to the ground connection soldered ball via described through hole, ground pad.
10. semiconductor package part according to claim 6 is characterized in that described conduction mold compound made or made by epoxy resin and conductive compound by epoxy resin and metallic conduction particle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102885895A CN103354228A (en) | 2013-07-10 | 2013-07-10 | Semiconductor packaging part and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102885895A CN103354228A (en) | 2013-07-10 | 2013-07-10 | Semiconductor packaging part and manufacturing method thereof |
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| CN103354228A true CN103354228A (en) | 2013-10-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2013102885895A Pending CN103354228A (en) | 2013-07-10 | 2013-07-10 | Semiconductor packaging part and manufacturing method thereof |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105789065A (en) * | 2016-04-08 | 2016-07-20 | 广东欧珀移动通信有限公司 | Chip package structure and preparation method thereof, and terminal device comprising the same |
| TWI692845B (en) * | 2017-12-05 | 2020-05-01 | 日商Ｔｄｋ股份有限公司 | Electronic circuit package using sealing material having conductivity |
| CN111180419A (en) * | 2018-11-09 | 2020-05-19 | 三星电子株式会社 | Semiconductor package and electromagnetic interference shielding structure for semiconductor package |
| CN113594151A (en) * | 2021-06-25 | 2021-11-02 | 苏州汉天下电子有限公司 | Semiconductor package and method of manufacturing the same |
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| US20050184405A1 (en) * | 2004-02-24 | 2005-08-25 | Jin-Chung Bai | Semiconductor package for lowering electromagnetic interference and method for fabricating the same |
| US20050250246A1 (en) * | 2001-09-27 | 2005-11-10 | Hiroshi Ogasawara | Method and apparatus for shielding integrated circuits |
| CN101145526A (en) * | 2006-09-13 | 2008-03-19 | 日月光半导体制造股份有限公司 | Semiconductor package structure having electromagnetic shielding and making method thereof |
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2013
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| US5371404A (en) * | 1993-02-04 | 1994-12-06 | Motorola, Inc. | Thermally conductive integrated circuit package with radio frequency shielding |
| US20050250246A1 (en) * | 2001-09-27 | 2005-11-10 | Hiroshi Ogasawara | Method and apparatus for shielding integrated circuits |
| TW200408019A (en) * | 2002-11-13 | 2004-05-16 | Advanced Semiconductor Eng | Semiconductor package structure with ground and method for manufacturing thereof |
| US20050184405A1 (en) * | 2004-02-24 | 2005-08-25 | Jin-Chung Bai | Semiconductor package for lowering electromagnetic interference and method for fabricating the same |
| CN101145526A (en) * | 2006-09-13 | 2008-03-19 | 日月光半导体制造股份有限公司 | Semiconductor package structure having electromagnetic shielding and making method thereof |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105789065A (en) * | 2016-04-08 | 2016-07-20 | 广东欧珀移动通信有限公司 | Chip package structure and preparation method thereof, and terminal device comprising the same |
| CN105789065B (en) * | 2016-04-08 | 2019-02-12 | Oppo广东移动通信有限公司 | A kind of chip-packaging structure, terminal device and method |
| US10679917B2 (en) | 2016-04-08 | 2020-06-09 | Guangdong Oppo Mobile Telecommunications Corp., Ltd. | Chip package structure, terminal device, and method |
| TWI692845B (en) * | 2017-12-05 | 2020-05-01 | 日商Ｔｄｋ股份有限公司 | Electronic circuit package using sealing material having conductivity |
| CN111180419A (en) * | 2018-11-09 | 2020-05-19 | 三星电子株式会社 | Semiconductor package and electromagnetic interference shielding structure for semiconductor package |
| CN111180419B (en) * | 2018-11-09 | 2023-08-15 | 三星电子株式会社 | Semiconductor package and electromagnetic interference shielding structure for the same |
| CN113594151A (en) * | 2021-06-25 | 2021-11-02 | 苏州汉天下电子有限公司 | Semiconductor package and method of manufacturing the same |
| CN113594151B (en) * | 2021-06-25 | 2024-05-14 | 苏州汉天下电子有限公司 | Semiconductor package and method of manufacturing the same |
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Application publication date: 20131016 |