CN102969303A - Semiconductor packaging structure and production method thereof - Google Patents
Semiconductor packaging structure and production method thereof Download PDFInfo
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- CN102969303A CN102969303A CN2012104180502A CN201210418050A CN102969303A CN 102969303 A CN102969303 A CN 102969303A CN 2012104180502 A CN2012104180502 A CN 2012104180502A CN 201210418050 A CN201210418050 A CN 201210418050A CN 102969303 A CN102969303 A CN 102969303A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49112—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73257—Bump and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Electromagnetism (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The invention provides a semiconductor packaging structure and a production method thereof. The method comprises steps of providing a substrate, arranging a plurality of grounding pads on the substrate, arranging a first semiconductor component and a second semiconductor component on the substrate, placing the grounding pads between the first semiconductor component and the second semiconductor component, and connecting a plurality of conductive welding lines to the grounding pads. By the aid of the structure, the conductive welding lines can shield electromagnetic interference effectively.
Description
Technical field
The present invention relates to a kind of semiconductor package and manufacture method thereof, particularly relate to a kind of semiconductor package and manufacture method thereof with electromagnetic signal shielding construction.
Background technology
In semiconductor production process, integrated antenna package (IC package) is one of important step of processing procedure, in order to protecting the IC chip and to provide outside and be electrically connected, to prevent the destruction of carrying and getting external force in the process of putting or environmental factor.In addition, integrated circuit component also needs to be combined into a system with passive devices such as resistance, electric capacity, the function that competence exertion is set, and Electronic Packaging (Electronic Packaging) namely is be used to the protection of setting up integrated circuit component and organizational structure.Generally speaking, after the integrated circuit (IC) chip processing procedure, begin to carry out Electronic Packaging, comprise that cohering of IC chip is fixing, circuit is online, sealing structure, with the engaging of circuit board, system in combination until product all processing procedures between finishing.
At present, in semiconductor package, have unnecessary noise (noise) or interference between the chip, such as electromagnetic interference (electro-magnetic interference, EMI), this problem is more obvious on the chip of wireless telecommunications especially.At this moment, generally be to use crown cap (metal lid) to come shield electromagnetic signals to disturb.Yet arranging of this crown cap can increase weight and the thickness of semiconductor package, and can increase the cost of manufacture of crown cap.
So, be necessary to provide a kind of semiconductor package and manufacture method thereof, to solve the existing problem of prior art.
Summary of the invention
A purpose of the present invention is to provide a kind of semiconductor package, and described semiconductor package comprises substrate, the first semiconductor element, the second semiconductor element and many conduction bonding wires.One surface of substrate is provided with a plurality of ground mats, first and second semiconductor element is arranged on the substrate, wherein the first semiconductor element comprises one near the first surface of substrate, away from second surface and the conductive layer of substrate, and conductive layer is to be formed on the second surface of described the first semiconductor element.A plurality of ground mats are arranged between first and second semiconductor element, and many conduction bonding wires are connected between the conductive layer and ground mat of the first semiconductor element.
Another object of the present invention is to provide a kind of semiconductor package, described semiconductor package comprises substrate, the first semiconductor element, the second semiconductor element and many conduction bonding wires.One surface of substrate is provided with a plurality of ground mats, first and second semiconductor element is arranged on the substrate, a plurality of ground mats are arranged at the both sides of the first semiconductor element, and at least part of ground mat is between first and second semiconductor element, and many conduction bonding wires are connected between the ground mat of the first semiconductor element both sides.
Another purpose of the present invention is to provide a kind of manufacture method of semiconductor package.In the manufacture method of this semiconductor package, at first, one substrate is provided, wherein a plurality of ground mats are arranged on the substrate, then, the first semiconductor element and the second semiconductor element are set on substrate, wherein ground mat is between the first semiconductor element and the second semiconductor element, the first semiconductor element comprises a first surface near substrate, second surface and a conductive layer away from substrate, conductive layer is to be formed on the second surface of the first semiconductor element, then, many conduction bonding wires is connected between the conductive layer of ground mat and the first semiconductor element.
Semiconductor package of the present invention can shield unnecessary interference by the conduction bonding wire with ground connection between the semiconductor element, electromagnetic interference (EMI/EMC) for example, thereby can effectively isolate the electromagnetic signal of adjacent semiconductor element.Come shielding electromagnetic interference because semiconductor package of the present invention can reduce or omit existing crown cap, thereby reduce overall weight and processing procedure cost.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Fig. 1 shows the profile according to the semiconductor package of the first embodiment of the present invention;
Fig. 2 shows the top view according to the semiconductor package of the first embodiment of the present invention;
Fig. 3 shows according to the line-spacing of the conduction bonding wire of the semiconductor package of one embodiment of the invention and the graph of a relation between the coupling effect;
Fig. 4 A to Fig. 4 C shows the manufacturing flow chart according to the base plate for packaging of one embodiment of the invention;
Fig. 5 shows the top view according to the semiconductor package of the second embodiment of the present invention;
Fig. 6 A, Fig. 6 B and Fig. 6 C show the top view according to the semiconductor package of the 3rd to the 5th embodiment of the present invention;
Fig. 7 shows the top view according to the semiconductor package of the sixth embodiment of the present invention;
Fig. 8, it shows the top view according to the semiconductor package of the seventh embodiment of the present invention;
Fig. 9 shows the profile according to the semiconductor package of the eighth embodiment of the present invention; And
Figure 10 shows the stereogram according to the semiconductor package of the eighth embodiment of the present invention.
Embodiment
Below the explanation of each embodiment be with reference to additional graphic, can be in order to the specific embodiment of implementing in order to illustration the present invention.The direction term that the present invention mentions, such as " on ", D score, 'fornt', 'back', " left side ", " right side ", " interior ", " outward ", " side " etc., only be the direction with reference to annexed drawings.Therefore, the direction term of use is in order to explanation and understands the present invention, but not in order to limit the present invention.
In the drawings, the unit of structural similarity is to represent with same numeral.
Please refer to Fig. 1 and Fig. 2, Fig. 1 shows the profile according to the semiconductor package of the first embodiment of the present invention, and Fig. 2 shows the top view according to the semiconductor package of the first embodiment of the present invention.The semiconductor package 100 of present embodiment comprises substrate 110, the first semiconductor element 120, the second semiconductor element 130, a plurality of ground mat 140, many conduction bonding wires 150 and packing colloid 160.The first semiconductor element 120, the second semiconductor element 130 and ground mat 140 are to be arranged on the substrate 110, and ground mat 140 is at least between the first semiconductor element 120 and the second semiconductor element 130.Conduction bonding wire 150 is to be connected between ground mat 140 and the first semiconductor element 120, is used to form shield effectiveness.Packing colloid 160 is to be formed on the substrate 110, and coats the first semiconductor element 120, the second semiconductor element 130 and many conduction bonding wires 150.
As shown in Figures 1 and 2, substrate 110 comprises at least one line layer 111 and at least one conductive hole 112.When substrate 110 comprises multilayer line layer 111, these a little line layers 111 are electrically connected with conductive hole 112.Ground mat 140 on the substrate 110 is electrically connected at the line layer 111 of substrate 110.Substrate 110 can for example be multilayer printed board.
The first semiconductor element 120 comprises projection 121, conductive layer 122, one near the first surface 123 of substrate and away from the second surface 124 of substrate.The first semiconductor element 120 and the second semiconductor element 130 can be selected from respectively semiconductor chip (chip) or semiconductor package body (package), for example the first semiconductor element 120 can be by for example spherical pin grid array (Ball Grid Array, B GA) encapsulation technology, wafer-level package (Chip Scale Package) technology, flip-chip (Flip chip) technology or other packaged type are arranged on the substrate 110.At this moment, the active surface of the first semiconductor element 120 (first surface 123) is the surface towards substrate 110.The first semiconductor element 120 and the second semiconductor subassembly 130 can for example be arranged on the substrate 110 by projection 121,131 respectively, by projection 121,131 and substrate 110 in circuit be electrically connected.
The first semiconductor element 120 has conductive layer 122, and it is formed at the back side (second surface 124) of the first semiconductor element 120, and conductive layer 122 can be metal (for example copper, nickel, gold, silver) film.In the present embodiment, the first semiconductor element 120 is the semiconductor element (chip or packaging body) of wish shielding, and the second semiconductor element 130 then can be arbitrarily semiconductor element (chip or packaging body) or electronic component (such as passive device).
As shown in Figures 1 and 2, in the present embodiment, ground mat 140 can be arranged in the first semiconductor element 120 around, and with the ground path electrically connect of the inside of substrate, and conduction bonding wire 150 is to be welded between the conductive layer 122 and ground mat 140 of the first semiconductor element 120.Wherein, the material of conduction bonding wire 150 can be copper, gold or other metal material, the live width of each bar conduction bonding wire 150 can be 15 microns (μ m)～30.5 microns, spacing (pitch) between the conduction bonding wire 150 can be less than 300 microns (μ m), for example be 60 μ m～280 μ m, when the spacing of conduction between the bonding wire during greater than 300 microns, not good to the shield effectiveness of Electromagnetic Interference.
As shown in Figures 1 and 2, the packing colloid 160 of present embodiment can be used for coating and protecting the first semiconductor element 120, reaches conduction bonding wire 150 and the second semiconductor element 130.The insulating substrate of described packing colloid 160 can be epoxy resin (epoxy), polymethyl methacrylate (PMMA), Merlon (Polycarbonate) or silica gel, and it avoids being subject to the impact of ambient temperature, humidity or atmosphere in order to the inner element of protection packaging structure.
Please refer to Fig. 3, it shows according to the line-spacing of the conduction bonding wire of the semiconductor package of one embodiment of the invention and the graph of a relation between the coupling effect.Line L1 is expressed as the coupling effect (coupling effect) of encapsulating structure with conduction bonding wire 150, and line L2 represents to have the line-spacing of semiconductor package 100 of conduction bonding wire 150 and the relation between the coupling effect.Compared to the encapsulating structure (shown in line L1) with conduction bonding wire 150, semiconductor package 100 with conduction bonding wire 150 can have lower coupling effect (shown in line L2), that is the effective electromagnetic coupling effect between the shielding electronic components of conduction bonding wire 150, shield effect and have electromagnetic signal.
Please refer to Fig. 4 A to Fig. 4 C, it shows the manufacturing flow chart according to the base plate for packaging of one embodiment of the invention.When making the semiconductor package 100 of present embodiment, at first, shown in Fig. 4 A, provide substrate 110, at this moment, ground mat 140 can be arranged in advance on the substrate 110 and with the inside ground path electrically connect of substrate.Then, shown in Fig. 4 B, the first semiconductor element 120 and the second semiconductor element 130 are set on substrate 110, at this moment, ground mat 140 is at least between the first semiconductor element 120 and the second semiconductor element 130.Then, shown in Fig. 4 C, carry out the routing step, be connected between the conductive layer 122 of ground mat 140 and the first semiconductor element 120 and will conduct electricity bonding wire 150.Then, form packing colloid 160 and coat the first semiconductor element 120, the second semiconductor element 130 and conduction bonding wire 150.
Please refer to Fig. 5, it shows the top view according to the semiconductor package of the second embodiment of the present invention.In a second embodiment, conduction bonding wire 150 can be connected between ground mat 140 and the conductive layer 122 alternately.
Please refer to Fig. 6 A, Fig. 6 B and Fig. 6 C, it shows the top view according to the semiconductor package of the 3rd to the 5th embodiment of the present invention.Ground mat 140 is to be arranged at least between the first semiconductor element 120 and the second semiconductor element 130.In the 3rd to the 5th embodiment, ground mat 140 can only be arranged at a side, two sides or three sides of the first semiconductor element 120.
Please refer to Fig. 7, it shows the top view according to the semiconductor package of the sixth embodiment of the present invention.In the 6th embodiment, each ground mat 140 can be strip, and it can be beaten on same ground mat by many conduction bonding wires around the first semiconductor element 120 simultaneously.
Please refer to Fig. 8, it shows the top view according to the semiconductor package of the seventh embodiment of the present invention.In another embodiment, the first semiconductor element 120 can be arranged on the substrate 110 by for example surface mount layer 125, and need not by soldered ball 121.At this moment, the first semiconductor element 120 can be by for example contact grid array (Land Grid Array, LGA) encapsulation technology, quad flat non-pin package (Quad Flat No-lead Package) technology or other packaged type are arranged on the substrate 110.
Please refer to Fig. 9 and Figure 10, Fig. 9 shows the profile according to the semiconductor package of the eighth embodiment of the present invention, and Figure 10 shows the stereogram according to the semiconductor package of the eighth embodiment of the present invention.In the 8th embodiment, the first semiconductor element 220 can not have conductive layer 122, and ground mat 240 is the both sides that are arranged at the first semiconductor element 220, and at least part of ground mat 240 is between the first semiconductor element 220 and the second semiconductor element 130.Many conduction bonding wire 250 is to be connected between the ground mat 240 of the first semiconductor element 220 both sides, and across crossing the first semiconductor element 220, to shield the first semiconductor element 220.
In sum; although the present invention discloses as above with preferred embodiment; but above preferred embodiment is not to limit the present invention; those of ordinary skill in the art; without departing from the spirit and scope of the present invention; all can do various changes and retouching, so protection scope of the present invention is as the criterion with the scope that claim defines.
Claims (10)
1. semiconductor package, it is characterized in that: described semiconductor package comprises:
One substrate, a surface of described substrate is provided with a plurality of ground mats;
One first semiconductor element, be arranged on the described substrate, wherein said the first semiconductor element comprises one near the first surface of substrate, away from second surface and a conductive layer of substrate, and described conductive layer is to be formed on the described second surface of described the first semiconductor element;
One second semiconductor element is arranged on the described substrate, and wherein said a plurality of ground mats are arranged between described first and second semiconductor element; And
Many conduction bonding wires are connected between the described conductive layer and described ground mat of described the first semiconductor element.
2. semiconductor package according to claim 1, it is characterized in that: described the first semiconductor element is selected from semiconductor chip or semiconductor package body.
3. semiconductor package according to claim 1, it is characterized in that: the spacing between the described conduction bonding wire is less than 300 microns.
4. semiconductor package according to claim 1, it is characterized in that: the live width of each described conduction bonding wire is 15 microns～30.5 microns.
5. semiconductor package according to claim 1, it is characterized in that: described conductive layer is metallic film.
6. semiconductor package according to claim 1 is characterized in that: described ground mat be arranged in described the first semiconductor element around.
7. semiconductor package according to claim 1, it is characterized in that: each described ground mat is elongated, and around described the first semiconductor element, wherein a plurality of conduction bonding wires are beaten simultaneously on same ground mat.
8. semiconductor package according to claim 1, it is characterized in that: described conduction bonding wire is to be connected in alternately between described ground mat and the described conductive layer.
9. semiconductor package, it is characterized in that: described semiconductor package comprises:
One substrate, a surface of described substrate is provided with a plurality of ground mats;
One first semiconductor element is arranged on the described substrate;
One second semiconductor element is arranged on the described substrate, and wherein said a plurality of ground mats are arranged at the both sides of described the first semiconductor element, and at least part of described ground mat is between described first and second semiconductor element; And
Many conduction bonding wires are connected between the described ground mat of described the first semiconductor element both sides.
10. the manufacture method of a semiconductor package, it is characterized in that: described manufacture method comprises:
One substrate is provided, and wherein a plurality of ground mats are arranged on the described substrate;
The first semiconductor element and the second semiconductor element are set on described substrate, wherein said ground mat is between described first and second semiconductor element, described the first semiconductor element comprises a first surface near substrate, away from second surface and a conductive layer of substrate, described conductive layer is to be formed on the described second surface of described the first semiconductor element; And
Many conduction bonding wires are connected between the described conductive layer of described ground mat and described the first semiconductor element.
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| CN2012104180502A CN102969303A (en) | 2012-10-26 | 2012-10-26 | Semiconductor packaging structure and production method thereof |
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| CN2012104180502A CN102969303A (en) | 2012-10-26 | 2012-10-26 | Semiconductor packaging structure and production method thereof |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105552063A (en) * | 2016-02-03 | 2016-05-04 | 深圳佰维存储科技有限公司 | System in a package (SIP) structure |
| CN106340506A (en) * | 2016-10-20 | 2017-01-18 | 江苏长电科技股份有限公司 | Semiconductor packaging structure and manufacturing method thereof |
| US9736925B2 (en) | 2014-01-31 | 2017-08-15 | Stmicroelectronics S.R.L. | Packaged semiconductor device having a shielding against electromagnetic interference and manufacturing process thereof |
| CN111653552A (en) * | 2020-06-16 | 2020-09-11 | 西安科技大学 | Square flat chip packaging structure with high electromagnetic pulse interference resistance |
| CN111653551A (en) * | 2020-06-16 | 2020-09-11 | 西安科技大学 | BGA chip packaging structure with high anti-electromagnetic pulse interference capability |
| CN115119487A (en) * | 2022-04-15 | 2022-09-27 | 平头哥(上海)半导体技术有限公司 | Electromagnetic interference shielding assembly, manufacturing method and electromagnetic interference shielding method |
| WO2022256999A1 (en) * | 2021-06-08 | 2022-12-15 | Yangtze Memory Technologies Co., Ltd. | Electromagnetic interference shielding package structures and fabricating methods thereof |
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