CN102969303A - Semiconductor packaging structure and production method thereof - Google Patents

Semiconductor packaging structure and production method thereof Download PDF

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Publication number
CN102969303A
CN102969303A CN2012104180502A CN201210418050A CN102969303A CN 102969303 A CN102969303 A CN 102969303A CN 2012104180502 A CN2012104180502 A CN 2012104180502A CN 201210418050 A CN201210418050 A CN 201210418050A CN 102969303 A CN102969303 A CN 102969303A
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substrate
semiconductor
semiconductor element
plurality
structure
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CN2012104180502A
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Chinese (zh)
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沈家贤
刘盈男
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日月光半导体制造股份有限公司
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Priority to CN2012104180502A priority Critical patent/CN102969303A/en
Publication of CN102969303A publication Critical patent/CN102969303A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49112Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73257Bump and wire connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Abstract

The invention provides a semiconductor packaging structure and a production method thereof. The method comprises steps of providing a substrate, arranging a plurality of grounding pads on the substrate, arranging a first semiconductor component and a second semiconductor component on the substrate, placing the grounding pads between the first semiconductor component and the second semiconductor component, and connecting a plurality of conductive welding lines to the grounding pads. By the aid of the structure, the conductive welding lines can shield electromagnetic interference effectively.

Description

半导体封装结构及其制造方法 The semiconductor package structure and a manufacturing method

技术领域 FIELD

[0001] 本发明涉及一种半导体封装结构及其制造方法,特别是涉及一种具有电磁信号屏蔽结构的半导体封装结构及其制造方法。 [0001] The present invention relates to a semiconductor package structure and a manufacturing method, particularly to a semiconductor package structure and a manufacturing method of the shielding structure having an electromagnetic signal.

背景技术 Background technique

[0002] 在半导体生产过程中,集成电路封装(IC package)是制程的重要步骤之一,用以保护IC芯片与提供外部电性连接,以防止在输送及取置过程中外力或环境因素的破坏。 [0002] In the semiconductor manufacturing process, integrated circuit package (IC Package) is an important step in the process, to protect the IC chip and providing external electrical connection, and to prevent delivery during the pick and place or external environmental factors damage. 此夕卜,集成电路元件亦需与电阻、电容等被动元件组合成为一个系统,才能发挥既定的功能,而电子封装(Electronic Packaging)即是用于建立集成电路元件的保护与组织架构。 Bu this evening, in combination with the integrated circuit element should also resistors, capacitors and other passive components into a system, in order to play a predetermined function, and the electronic package (Electronic Packaging) that is used to establish an integrated circuit element protection and organization. 一般而言,在集成电路芯片制程之后始进行电子封装,包括IC芯片的黏结固定、电路联机、结构密封、与电路板之接合、系统组合、直至产品完成之间的所有制程。 Generally, after the integrated circuit chip processes begin electronic package comprising an IC chip bonding fixed, the circuit connection, the sealing structure, and engage the circuit board, the combination of the system until the product is completed between all process.

[0003]目前,在半导体封装结构中,芯片之间会有不必要的噪声(noise)或干扰,如电磁干扰(electro-magnetic interference,EMI),特别在无线通讯的芯片上此问题更为明显。 [0003] Currently, in a semiconductor package structure, there will be unwanted noise (Noise) chips or between interference, such as EMI (electro-magnetic interference, EMI), in particular on the chip for wireless communication this problem more evident . 此时,一般是使用金属盖(metal lid)来屏蔽电磁信号干扰。 In this case, generally a metal cap (metal lid) for shielding electromagnetic interference. 然而,此金属盖的设置会增加半导体封装结构的重量及厚度,且会增加金属盖的制作成本。 However, this metal cover is provided to increase the weight and thickness of the semiconductor package structure, and will increase the manufacturing cost of the metal lid.

[0004] 故,有必要提供一种半导体封装结构及其制造方法,以解决现有技术所存在的问题。 [0004] Therefore, there is need to provide a semiconductor package structure and a manufacturing method to solve the problems of the prior art.

发明内容 SUMMARY

[0005] 本发明的一目的在于提供一种半导体封装结构,所述半导体封装结构包括基板、第一半导体元件、第二半导体元件及多条导电焊线。 [0005] The object of the present invention is to provide a semiconductor package, the semiconductor package includes a substrate, a first semiconductor element, a semiconductor element, and a second plurality of electrically conductive bonding wires. 基板的一表面上设有多个接地垫,第一及第二半导体元件设置于基板上,其中第一半导体元件包含一靠近基板的第一表面、远离基板的第二表面及导电层,导电层是形成于所述第一半导体兀件的第二表面上。 A plurality of ground pads provided on the surface of the substrate, the first and second semiconductor elements disposed on the substrate, wherein the first semiconductor element comprises a first surface close to the substrate, the second surface and a conductive layer away from the substrate, a conductive layer It is formed on the second surface of the first semiconductor element Wu. 多个接地垫设置于第一与第二半导体元件之间,多条导电焊线连接于第一半导体元件的导电层与接地垫之间。 A plurality of ground pads disposed between the first and the second semiconductor element, a plurality of electrically conductive bonding wire connected between the conductive layer and the ground pad of the first semiconductor element.

[0006] 本发明的另一目的在于提供一种半导体封装结构,所述半导体封装结构包括基板、第一半导体元件、第二半导体元件及多条导电焊线。 [0006] Another object of the present invention is to provide a semiconductor package, the semiconductor package includes a substrate, a first semiconductor element, a semiconductor element, and a second plurality of electrically conductive bonding wires. 基板的一表面设有多个接地垫,第一及第二半导体元件设置于基板上,多个接地垫设置于第一半导体元件的两侧,且至少部分接地垫是位于第一与第二半导体元件之间,多条导电焊线连接于第一半导体元件两侧的接地垫之间。 A surface of the substrate is provided with a plurality of ground pads, the first and second semiconductor elements disposed on the substrate, a plurality of ground pads provided on both sides of the first semiconductor element, and at least a portion of the ground pad is located between the first and the second semiconductor between the elements, a plurality of bonding wires connected between the first conductive ground pad of the semiconductor element on both sides.

[0007] 本发明的又一目的在于提供一种半导体封装结构的制造方法。 [0007] A further object of the present invention to provide a method for manufacturing a semiconductor package structure. 在此半导体封装结构的制造方法中,首先,提供一基板,其中多个接地垫排列于基板上,接着,设置第一半导体元件及第二半导体元件于基板上,其中接地垫是位于第一半导体元件与第二半导体元件之间,第一半导体兀件包含一靠近基板的第一表面,远离基板的第二表面及一导电层,导电层是形成于第一半导体元件的第二表面上,接着,将多条导电焊线连接于接地垫与第一半导体元件的导电层之间。 In this method of manufacturing a semiconductor package structure, first, a substrate in which a plurality of ground pads arranged on the substrate, then a first semiconductor element and the second semiconductor element on the substrate, wherein the ground pad is located between the first semiconductor between the semiconductor element and the second element, the first element comprising a first semiconductor Wu near a substrate surface, a second surface and a conductive layer, a conductive layer away from the substrate is formed on the second surface of the first semiconductor element, and then the plurality of electrically conductive bonding wire connected between the ground pad and the conductive layer of the first semiconductor element. [0008] 本发明的半导体封装结构可通过将半导体元件之间接地的导电焊线来屏蔽不必要的干扰,例如电磁干扰(EMI/EMC),因而可有效地隔离相邻半导体元件的电磁信号。 [0008] The semiconductor package according to the present invention can be prepared by conducting the ground wire bonding between the semiconductor element to shield unwanted interference, such as electromagnetic interference (EMI / EMC), thus effectively isolating adjacent semiconductor elements of the electromagnetic signal. 由于本发明的半导体封装结构可减少或省略现有金属盖来屏蔽电磁波干扰,因而减少整体重量及制程成本。 Since the semiconductor package of the present invention may reduce or omit the conventional metal lid to shield electromagnetic interference, thereby reducing the overall weight and manufacturing cost.

[0009] 为让本发明的上述内容能更明显易懂,下文特举优选实施例,并配合所附图式,作详细说明如下: [0009] In order to make the above-described present invention can be more fully understood, the following preferred non-limiting embodiment, and with the accompanying drawings, described in detail below:

附图说明 BRIEF DESCRIPTION

[0010] 图I显示依照本发明的第一实施例的半导体封装结构的剖面图; [0011] 图2显示依照本发明的第一实施例的半导体封装结构的上视图; [0010] FIG I shows a cross-sectional view of a semiconductor package in accordance with a first embodiment of the present invention; [0011] Figure 2 shows a top view of a first configuration of a semiconductor package according to embodiments of the present invention;

[0012] 图3显示依照本发明的一实施例的半导体封装结构的导电焊线的线距与耦合效应之间的关系图; [0012] Figure 3 shows the relationship between the distance and the coupling effect of the conductive bonding wire lines semiconductor package according to an embodiment of the present invention;

[0013] 图4A至图4C显示依照本发明的一实施例的封装基板的制造流程图; [0013] FIGS. 4A to 4C show a flowchart for manufacturing a package substrate according to an embodiment of the present invention;

[0014] 图5显示依照本发明的第二实施例的半导体封装结构的上视图; [0014] FIG. 5 shows a top view of a second embodiment of the present invention, a semiconductor packaging structure in accordance with;

[0015] 图6A、图6B及图6C显示依照本发明的第三至第五实施例的半导体封装结构的上视图; [0015] FIGS. 6A, 6B and 6C show third to the present invention in accordance with the view of a semiconductor package according to a fifth embodiment;

[0016] 图7显示依照本发明的第六实施例的半导体封装结构的上视图; [0016] Figure 7 shows a top view of a configuration of a semiconductor package according to a sixth embodiment of the present invention;

[0017] 图8,其显示依照本发明的第七实施例的半导体封装结构的上视图; [0017] FIG. 8, which shows a top view of a semiconductor package according to a seventh embodiment of the present invention;

[0018] 图9显示依照本发明的第八实施例的半导体封装结构的剖面图;以及 [0018] Figure 9 shows a cross-sectional view of a semiconductor package according to an eighth embodiment of the present invention; and

[0019] 图10显示依照本发明的第八实施例的半导体封装结构的立体图。 [0019] Figure 10 shows a perspective view of the present invention in accordance with an eighth embodiment of a semiconductor package structure.

具体实施方式 Detailed ways

[0020] 以下各实施例的说明是参考附加的图式,用以例示本发明可用以实施的特定实施例。 DESCRIPTION [0020] The following examples are reference to the accompanying drawings for illustrating the embodiments may be used to particular embodiments of the present invention. 本发明所提到的方向用语,例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等,仅是参考附加图式的方向。 Direction mentioned present invention, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., are only with reference to additional figures direction. 因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。 Thus, the use of directional terms are used to describe and understand the present invention, not to limit the present invention.

[0021] 在图中,结构相似的单元是以相同标号表示。 [0021] In the drawings, similar structural units are represented by the same reference numerals.

[0022] 请参照图I及图2,图I显示依照本发明的第一实施例的半导体封装结构的剖面图,图2显示依照本发明的第一实施例的半导体封装结构的上视图。 [0022] Referring to FIGS. I and 2, FIG I shows a cross-sectional view of a semiconductor package in accordance with a first embodiment of the present invention, Figure 2 shows a top view of a semiconductor package according to a first embodiment of the present invention. 本实施例的半导体封装结构100包括基板110、第一半导体元件120、第二半导体元件130、多个接地垫140、多条导电焊线150及封装胶体160。 The semiconductor package 100 of the present embodiment includes a substrate 110, a first semiconductor element 120, the second semiconductor element 130, a plurality of ground pads 140, bonding wires 150 and a plurality of conductive encapsulant 160. 第一半导体元件120、第二半导体元件130及接地垫140是设置于基板110上,接地垫140是至少位于第一半导体元件120及第二半导体元件130之间。 A first semiconductor element 120, the second semiconductor element 130 and the ground pad 140 is disposed on the substrate 110, ground pad 140 is positioned between at least a first semiconductor element 130 and the second semiconductor element 120. 导电焊线150是连接于接地垫140与第一半导体元件120之间,用于形成屏蔽效果。 Electrically conductive bonding wire 150 is connected to a ground pad 140 and the first semiconductor element 120, for forming the shielding effect. 封装胶体160是形成于基板110上,并包覆第一半导体元件120、第二半导体元件130及多条导电焊线150。 Encapsulant 160 is formed on the substrate 110, and covers the first semiconductor element 120, bonding wires 130 and a plurality of second conductive semiconductor element 150.

[0023] 如图I及图2所示,基板110包括至少一线路层111及至少一导电孔112。 [0023] FIG. I and 2, the substrate 110 includes at least the at least one conductive via 111 and a wiring layer 112. 当基板110包括多层线路层111,此些线路层111以导电孔112电性连接。 When the substrate 110 comprises a multilayer wiring layers 111, 111 of such circuit layer 112 are electrically connected to the conductive via. 基板110上的接地垫140电性连接于基板110之线路层111。 A ground pad 140 on the substrate 110 is electrically connected to the wiring layer 111 of the substrate 110. 基板110可例如为多层印刷电路基板。 For example, substrate 110 may be a multilayer printed circuit board.

[0024] 第一半导体兀件120包含凸块121、导电层122、一靠近基板的第一表面123及远离基板的第二表面124。 [0024] The first member 120 comprises a semiconductor Wu bumps 121, conductive layer 122, close to a first surface of the substrate 123 and the second surface 124 remote from the substrate. 第一半导体元件120及第二半导体元件130分别可以选自半导体芯片(chip)或半导体封装体(package),例如第一半导体元件120可通过例如球状引脚栅格阵列(Ball Grid Array,B GA)封装技术、芯片级封装(Chip Scale Package)技术、倒装芯片(Flip chip)技术或其它封装方式来设置于基板110上。 A first semiconductor element 120 and the second semiconductor element 130 can be selected from each of the semiconductor chip (Chip) or a semiconductor package (package), for example, a first semiconductor element 120 may be, for example, by a ball pin grid array (Ball Grid Array, B GA ) packaging technology, chip scale packages (chip Scale package) technology, flip chip (flip chip) technology or other packages to 110 disposed on the substrate. 此时,第一半导体元件120的主动表面(第一表面123)是朝向基板110的表面。 At this time, the first active surface of the semiconductor element 120 (the first surface 123) toward the surface of the substrate 110. 第一半导体兀件120及第二半导体组件130可分别例如通过凸块121、131来设置于基板110上,通过凸块121、131与基板110内的线路电性连接。 Wu first semiconductor element 120 and the second semiconductor element 130 may be provided by, for example, each protrusion 121, 131 on the substrate 110, electrically connected to the circuit substrate 110 through bumps 121, 131.

[0025] 第一半导体元件120具有导电层122,其形成于第一半导体元件120的背面(第二表面124),导电层122可为金属(例如铜、镍、金、银)薄膜。 [0025] The semiconductor element 120 having a first conductive layer 122, conductive layer 122 may be a metal (e.g., copper, nickel, gold, silver) film formed on the back surface (second surface 124) of the first semiconductor element 120. 在本实施例中,第一半导体元件120为欲屏蔽的半导体元件(芯片或封装体),而第二半导体元件130则可为任意的半导体元件(芯片或封装体)或电子元件(如被动元件)。 In the present embodiment, the first semiconductor element 120 is a semiconductor element (chip or package) to be shielded, and the second semiconductor element 130 may be any of a semiconductor element (chip or package) or electronic elements (such as passive components ).

[0026] 如图I及图2所示,在本实施例中,接地垫140可排列于第一半导体元件120的周围,并与基板的内部的接地线路电性连结,而导电焊线150是焊接于第一半导体元件120的导电层122与接地垫140之间。 [0026] FIG. I and 2, in the present embodiment, the ground pad 140 may be arranged around the first semiconductor element 120, and the internal substrate is electrically connected to a ground line, and the conductive bonding wires 150 are welded to the first semiconductor element 140 between the conductive layer 122 and the ground pad 120. 其中,导电焊线150的材料可为铜、金或其它金属材料,每一条导电焊线150的线宽可为15微米(iim)〜30. 5微米,导电焊线150之间的间距(pitch)可小于300微米(ii m),例如为60 ii m〜280 ii m,当导电焊线之间的间距大于300微米时,对电磁波干扰的屏蔽效果不佳。 Wherein the electrically conductive bonding wire 150 may be copper, gold or other metal materials, each electrically conductive bond wire 150 may be a line width of 15 microns (iim) ~30. 5 microns, the spacing between the electrically conductive bonding wire 150 (Pitch ) may be less than 300 microns (ii m), for example 60 ii m~280 ii m, when the spacing between the electrically conductive bonding wires greater than 300 microns, poor shielding effect on electromagnetic interference.

[0027] 如图I及图2所示,本实施例的封装胶体160可用于包覆及保护第一半导体元件120、及导电焊线150及第二半导体元件130。 [0027] As shown in FIGS. I and 2, the present embodiment of the encapsulant 160 may be used to cover and protect the first semiconductor element 120, and the conductive bonding wire 150 and the second semiconductor element 130. 所述封装胶体160的绝缘基材可为环氧树脂(epoxy)、聚甲基丙烯酸甲酯(PMMA)、聚碳酸酯(Polycarbonate)或娃胶,其用以保护封装构造内部的元件免于受到外界温度、湿度或大气的影响。 The encapsulant insulating substrate 160 may be an epoxy resin (Epoxy), polymethyl methacrylate (PMMA), polycarbonate (Polycarbonate) or baby gum, which is configured to protect the element from inside the package by the outside temperature, humidity, or atmospheric.

[0028] 导电层122及导电焊线150除做为电磁信号屏蔽功效之外,同时还可具有提升半导体组件的散热之功效。 [0028] The conductive layer 122 and the conductive bonding wires 150 as the other shielding effect than the electromagnetic signal, while also lifting the semiconductor device having the heat dissipation effect.

[0029] 请参照图3,其显示依照本发明的一实施例的半导体封装结构的导电焊线的线距与耦合效应之间的关系图。 [0029] Referring to FIG 3, the relation between the bonding wire conductive semiconductor package according to an embodiment of the present invention with the coupling effect from the line display. 线LI表示为未具有导电焊线150的封装结构的耦合效应(coupling effect),线L2表示具有导电焊线150的半导体封装结构100的线距与稱合效应之间的关系。 LI line coupling effect is represented as the conductive bonding wire package structure 150 (coupling effect) not having the line L2 indicates the relationship between the line of the semiconductor package 150 having conductive bonding wires 100 from engagement with said effect. 相较于未具有导电焊线150的封装结构(如线LI所示),具有导电焊线150的半导体封装结构100可具有较低的耦合效应(如线L2所示),亦即导电焊线150可有效屏蔽电子元件之间的电磁耦合效应,而具有电磁信号屏蔽功效。 The package (as shown by line LI), a conductive bonding wires 150 of the semiconductor package 100 may have a lower coupling effect (as shown by line L2), i.e., non-electrically conductive bonding wire having a conductive wire bonds compared to the 150 150 can effectively shield the effect of electromagnetic coupling between the electronic components, and having an electromagnetic shielding effect signal.

[0030] 请参照图4A至图4C,其显示依照本发明的一实施例的封装基板的制造流程图。 [0030] Referring to FIGS. 4A to 4C, the manufacturing flow chart showing a package substrate according to an embodiment of the present invention. 当制造本实施例的半导体封装结构100时,首先,如图4A所示,提供基板110,此时,接地垫140可预先排列于基板110上并与基板的内部接地线路电性连结。 When the semiconductor package 100 manufactured according to the present embodiment, first, as shown in FIG. 4A, a substrate 110, at this time, the ground pad 140 may be pre-arranged in the interior of the substrate and electrically connected to a ground line on the substrate 110. 接着,如图4B所示,设置第一半导体元件120及第二半导体元件130于基板110上,此时,接地垫140至少是位于第一半导体元件120及第二半导体元件130之间。 Subsequently, as shown in FIG. 4B, a first semiconductor element 120 and the second semiconductor element 130 on the substrate 110, at this time, the ground pad 140 is positioned between at least a first semiconductor element 130 and the second semiconductor element 120. 接着,如图4C所示,进行打线步骤,而将导电焊线150连接于接地垫140与第一半导体元件120的导电层122之间。 Next, as shown in FIG. 4C, a wire bonding step, and the conductive bonding wire 150 connected between the conductive layers 140 and 122 of the first ground pad 120 of the semiconductor element. 接着,形成封装胶体160来包覆第一半导体元件120、第二半导体元件130及导电焊线150。 Subsequently, an encapsulant 160 covers the first semiconductor element 120, the second semiconductor element 130 and the conductive wire bonds 150.

[0031] 请参照图5,其显示依照本发明的第二实施例的半导体封装结构的上视图。 [0031] Referring to FIG 5, which shows a top view of a semiconductor package according to a second embodiment of the present invention. 在第二实施例中,导电焊线150可交错地连接于接地垫140与导电层122之间。 In the second embodiment, the conductive wire bonds 150 may be interleaved 140 connected between a ground pad 122 and the conductive layer.

[0032] 请参照图6A、图6B及图6C,其显示依照本发明的第三至第五实施例的半导体封装结构的上视图。 [0032] Referring to FIG 6A, 6B and 6C, the view showing the structure of a semiconductor package according to the third to fifth embodiments of the present invention. 接地垫140是至少排列于第一半导体元件120与第二半导体元件130之间。 Ground pad 140 is arranged at least between the first semiconductor element 120 and the second semiconductor element 130. 在在第三至第五实施例中,接地垫140可仅设置于第一半导体元件120的一侧、二侧或二侧。 In the third to fifth embodiments, the ground pad 140 may be disposed on a first side of the semiconductor element 120, only two sides or two sides.

[0033] 请参照图7,其显示依照本发明的第六实施例的半导体封装结构的上视图。 [0033] Referring to FIG. 7, which shows a top view of a configuration of a semiconductor package according to a sixth embodiment of the present invention. 在第六实施例中,每一接地垫140可为长条形,其围绕于第一半导体元件120的周围,可多条导电焊线同时打在同一个接地垫上。 In the sixth embodiment, each of the ground pad 140 may be elongated, which surrounds around the first semiconductor element 120, the bonding wire may be a plurality of conductive pads while playing in the same ground.

[0034] 请参照图8,其显示依照本发明的第七实施例的半导体封装结构的上视图。 [0034] Referring to FIG. 8, which shows a top view of a semiconductor package according to a seventh embodiment of the present invention. 在另一实施例中,第一半导体元件120可通过例如表面黏着层125来设置于基板110上,而无需通过焊球121。 In another embodiment, the first semiconductor element 120 may be, for example, the surface of the adhesive layer 125 disposed on the substrate 110, without passing through the solder balls 121. 此时,第一半导体元件120可通过例如触点栅格阵列(Land Grid Array, LGA)封装技术、方形扁平无引脚封装(Quad Flat No-lead Package)技术或其它封装方式来设置于基板110上。 At this time, the first semiconductor element 120 may be disposed on the substrate 110 by, for example, a land grid array (Land Grid Array, LGA) packaging technology, QFN package (Quad Flat No-lead Package) technology or other packages on.

[0035] 请参照图9及图10,图9显示依照本发明的第八实施例的半导体封装结构的剖面图,图10显示依照本发明的第八实施例的半导体封装结构的立体图。 [0035] Referring to FIG. 9 and FIG. 10, FIG. 9 shows a perspective view of the invention of an eighth embodiment of a semiconductor package according to a cross-sectional view of a semiconductor package in an eighth embodiment of the present invention, the display 10 in accordance with FIG. 在第八实施例中,第一半导体元件220可未具有导电层122,接地垫240是设置于第一半导体元件220的两侧,且至少部分接地垫240是位于第一半导体元件220与第二半导体元件130之间。 In the eighth embodiment, the first semiconductor element 220 may not have a conductive layer 122, ground pad 240 is provided on both sides of the first semiconductor element 220, and at least a part of the first ground pad 240 and the second semiconductor element 220 is located between the semiconductor element 130. 多条导电焊线250是连接于第一半导体元件220两侧的接地垫240之间,且横跨过第一半导体元件220,以屏蔽第一半导体元件220。 A plurality of electrically conductive bonding wire 250 is connected to the ground on both sides of the first semiconductor element 220 between the pads 240 and 220 through the first semiconductor element across to shield the first semiconductor element 220.

[0036] 综上所述,虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本发明的精神和范围内,均可作各种更动与润饰,因此本发明的保护范围以权利要求界定的范围为准。 [0036] In summary, although the above disclosed embodiments of the present invention, a preferred, but not the above-described preferred embodiments within the spirit and scope of the invention to limit the present invention, those of ordinary skill in the art, without departing are various changes or modifications may be made, and the scope of the invention defined by the claims in the scope of equivalents.

Claims (10)

1. 一种半导体封装结构,其特征在于:所述半导体封装结构包括: 一基板,所述基板的一表面上设有多个接地垫; 一第一半导体元件,设置于所述基板上,其中所述第一半导体元件包含一靠近基板的第一表面、远离基板的第二表面及一导电层,所述导电层是形成于所述第一半导体兀件的所述第二表面上; 一第二半导体元件,设置于所述基板上,其中所述多个接地垫设置于所述第一与第二半导体元件之间;以及多条导电焊线,连接于所述第一半导体元件的所述导电层与所述接地垫之间。 A semiconductor package, characterized in that: said semiconductor package structure comprising: a substrate, a plurality of ground pads on a surface of the substrate; a first semiconductor element provided on the substrate, wherein said first element comprises a first semiconductor substrate near a surface, a second surface and a conductive layer away from the substrate, the conductive layer is formed on the second surface of said first semiconductor Wu member; a second a second semiconductor element provided on the substrate, wherein said plurality of ground pads disposed between the first and the second semiconductor element; and a plurality of electrically conductive bonding wire connecting the semiconductor element to the first conductive layer and the ground pad between.
2.根据权利要求I所述的半导体封装结构,其特征在于:所述第一半导体元件选自半导体芯片或半导体封装体。 The semiconductor package according to claim I of the structure, wherein: said first semiconductor chip or a semiconductor element selected from a semiconductor package.
3.根据权利要求I所述的半导体封装结构,其特征在于:所述导电焊线之间的间距小于300微米。 The semiconductor package according to claim according to structure I, wherein: the distance between the conductive bonding wire is less than 300 microns.
4.根据权利要求I所述的半导体封装结构,其特征在于:每一所述导电焊线的线宽为15微米〜30. 5微米。 The semiconductor package according to claim according to structure I, wherein: each of said conductive bonding wires of a line width of 15 ~ 30 m 5 m.
5.根据权利要求I所述的半导体封装结构,其特征在于:所述导电层为金属薄膜。 The semiconductor package according to claim according to structure I, wherein: said conductive layer is a metal thin film.
6.根据权利要求I所述的半导体封装结构,其特征在于:所述接地垫排列于所述第一半导体元件的周围。 The semiconductor package according to claim I of the structure, characterized in that: said ground pads arranged around the first semiconductor element.
7.根据权利要求I所述的半导体封装结构,其特征在于:每一所述接地垫呈长条形,并围绕于所述第一半导体元件的周围,其中多个导电焊线同时打在同一个接地垫上。 The semiconductor package according to claim according to structure I, wherein: each of said ground pad elongated strip and surrounds around the first semiconductor element, wherein the plurality of electrically conductive bonding wires simultaneously hit the same a ground pad.
8.根据权利要求I所述的半导体封装结构,其特征在于:所述导电焊线是交错地连接于所述接地垫与所述导电层之间。 The semiconductor package according to claim according to structure I, wherein: between said conductive bonding wires are alternately connected to the ground pad and the conductive layer.
9. 一种半导体封装结构,其特征在于:所述半导体封装结构包括: 一基板,所述基板的一表面设有多个接地垫; 一第一半导体元件,设置于所述基板上; 一第二半导体元件,设置于所述基板上,其中所述多个接地垫设置于所述第一半导体元件的两侧,且至少部分所述接地垫是位于所述第一与第二半导体元件之间;以及多条导电焊线,连接于所述第一半导体元件两侧的所述接地垫之间。 A semiconductor package, characterized in that: said semiconductor package structure comprising: a substrate, a surface of the substrate is provided with a plurality of ground pads; a first semiconductor element provided on the substrate; a first a second semiconductor element provided on the substrate, wherein said plurality of ground pads provided on both sides of the first semiconductor element, and at least a portion of the ground pad is located between the first and the second semiconductor element ; and a plurality of electrically conductive bonding wires connected to both sides of the semiconductor element between said first ground pad.
10. 一种半导体封装结构的制造方法,其特征在于:所述制造方法包括: 提供一基板,其中多个接地垫排列于所述基板上; 设置第一半导体元件及第二半导体元件于所述基板上,其中所述接地垫是位于所述第一与第二半导体元件之间,所述第一半导体元件包含一靠近基板的第一表面,远离基板的第二表面及一导电层,所述导电层是形成于所述第一半导体元件的所述第二表面上;以及将多条导电焊线连接于所述接地垫与所述第一半导体元件的所述导电层之间。 A method of manufacturing a semiconductor packaging structure, wherein: said manufacturing method comprising: providing a substrate, wherein the plurality of ground pads are arranged on said substrate; a first semiconductor element and the second semiconductor element to the on a substrate, wherein the ground pad is located between the first and the second semiconductor element, the first semiconductor element comprises a first surface close to the substrate, the second surface and a conductive layer away from the substrate, the the conductive layer is formed on the second surface of the first semiconductor element; and a plurality of electrically conductive bonding wire connected between the conductive layer of the first semiconductor element and the ground pad.
CN2012104180502A 2012-10-26 2012-10-26 Semiconductor packaging structure and production method thereof CN102969303A (en)

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