CN115119487A

CN115119487A - Electromagnetic interference shielding assembly, manufacturing method and electromagnetic interference shielding method

Info

Publication number: CN115119487A
Application number: CN202210396062.3A
Authority: CN
Inventors: 马超; 刘欢; 靖向萌; 范文锴
Original assignee: Pingtouge Shanghai Semiconductor Co Ltd
Current assignee: Pingtouge Shanghai Semiconductor Co Ltd
Priority date: 2022-04-15
Filing date: 2022-04-15
Publication date: 2022-09-27

Abstract

The embodiment of the specification provides an electromagnetic interference shielding assembly, a manufacturing method and an electromagnetic interference shielding method, wherein the electromagnetic interference shielding assembly comprises: the chip comprises a chip and a circuit board, wherein the bottom of a substrate of the chip is electrically connected with the circuit board; the first ground of the base plate is communicated with the second ground of the circuit board through the connecting component meeting the preset size condition. The scheme can be suitable for circuits with limited physical space and provides an electromagnetic interference shielding scheme with wider application range.

Description

Electromagnetic interference shielding assembly, manufacturing method and electromagnetic interference shielding method

Technical Field

The embodiment of the specification relates to the technical field of electromagnetic shielding, in particular to an electromagnetic interference shielding assembly.

Background

Electromagnetic Interference (EMI) is electronic noise that interferes with the cable signal and degrades signal integrity, and the source of EMI can be a source of radiated Interference. For example, in a Printed Circuit Board (PCB) and a Circuit implemented by the PCB, a pin of a chip or the like may be a radiation interference source: emitting electromagnetic waves and affecting the normal operation of the circuit. Therefore, emi shielding is critical to the circuit.

In the related art, electromagnetic interference generated by a radiation interference source is generally shielded by placing a wave-absorbing material and a metal shielding case near the radiation interference source of a chip in a circuit. However, both the wave-absorbing material and the metal shielding case need to occupy a certain physical space. Therefore, it cannot be applied to a circuit having a limited physical space. Therefore, it is desirable to provide a solution with a wider range of applicability.

Disclosure of Invention

In view of this, the embodiments of the present specification provide an electromagnetic interference shielding assembly. One or more embodiments of the present specification also relate to an emi shielding assembly manufacturing method, an emi shielding method, and a computing device, which solve the technical problems of the prior art.

According to a first aspect of embodiments herein, there is provided an electromagnetic interference shielding assembly comprising:

the chip comprises a chip and a circuit board, wherein the bottom of a substrate of the chip is electrically connected with the circuit board;

the first ground of the base plate is communicated with the second ground of the circuit board through the connecting component meeting the preset size condition.

According to a second aspect of embodiments herein, there is provided a method of manufacturing an electromagnetic interference shield assembly, comprising:

acquiring a circuit board, a target chip and a connecting assembly which accords with a preset size condition;

electrically connecting the substrate bottom of the target chip with the circuit board;

and communicating the first ground of the substrate with the second ground of the circuit board by using the connecting component to obtain the electromagnetic interference shielding component.

According to a third aspect of embodiments herein, there is provided an electromagnetic interference shielding method including:

determining a target chip and a target circuit board in a target circuit, wherein the target circuit board is electrically connected with the bottom of a substrate of the target chip;

in the target circuit, a connecting component for conducting the first ground of the substrate with the second ground of the circuit board is arranged, wherein the connecting component meets the preset size condition.

According to a fourth aspect of embodiments herein, there is provided a computing device comprising:

the electromagnetic interference shielding assembly of the first aspect is provided above.

One embodiment of the present specification provides an electromagnetic interference shield assembly comprising: the chip comprises a chip and a circuit board, wherein the bottom of a substrate of the chip is electrically connected with the circuit board; the first ground of the base plate is communicated with the second ground of the circuit board through the connecting component which accords with the preset size condition.

Therefore, the ground on the substrate is conducted with the ground of the PCB through the connecting component to form the Faraday cage. The faraday cage can enclose a radiation interference source between the chip substrate and the circuit board, thereby realizing the shielding of electromagnetic interference generated by the enclosed radiation interference source. And, the coupling assembling accords with the predetermined dimensional condition. Thus, for a circuit with limited physical space, the size condition may be set to fit the physical space of the circuit: less than or equal to the size of the physical space allocated to the EMI shielding assembly in the circuit. Therefore, electromagnetic shielding can be achieved without extra physical space, and the shielding assembly for ensuring electromagnetic interference can be suitable for circuits with limited physical space, and is wider in application range.

Drawings

FIG. 1 is a diagram illustrating a first scenario in which a chip generates electromagnetic interference in a circuit;

FIG. 2 is a diagram illustrating a second scenario in which a chip generates electromagnetic interference in a circuit;

FIG. 3 is a diagram illustrating a third scenario in which a chip generates electromagnetic interference in a circuit;

FIG. 4 is a diagram illustrating a fourth scenario in which a chip generates electromagnetic interference in a circuit;

FIG. 5 is a diagram illustrating an exemplary configuration of an EMI shielding assembly for EMI shielding by a wave absorbing material;

FIG. 6 is a diagram of an exemplary configuration of an EMI shield assembly for EMI shielding by a metallic shield can;

FIG. 7 is a schematic diagram of an EMI shielding assembly, according to one embodiment of the present disclosure;

FIG. 8 is a schematic structural diagram of another EMI shielding assembly provided in accordance with an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of another EMI shielding assembly provided in accordance with an embodiment of the present disclosure;

FIG. 10 is a schematic structural diagram of another EMI shielding assembly provided in accordance with an embodiment of the present disclosure;

FIG. 11 is a schematic structural diagram of another EMI shielding assembly provided in accordance with an embodiment of the present disclosure;

FIG. 12a is a side view of an electromagnetic interference shield assembly, in accordance with one embodiment of the present disclosure;

FIG. 12b is a top view of an EMI shield assembly in accordance with an embodiment of the present disclosure;

FIG. 13a is a side view of another EMI shielding assembly, in accordance with one embodiment of the present disclosure;

FIG. 13b is a top view of another EMI shielding assembly in accordance with one embodiment of the present disclosure;

FIG. 14a is a side view of an alternative EMI shielding assembly in accordance with one embodiment of the present disclosure;

FIG. 14b is a top view of another EMI shielding assembly, in accordance with one embodiment of the present disclosure;

FIG. 15 is a flow chart of a method of manufacturing an EMI shielding assembly in accordance with one embodiment of the present disclosure;

FIG. 16 is a flow chart of a method of EMI shielding provided in accordance with one embodiment of the present description;

FIG. 17 is a block diagram of a computing device, according to one embodiment of the present description;

FIG. 18 is a block diagram of another computing device provided in one embodiment of the present description.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present description. This description may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, as those skilled in the art will be able to make and use the present disclosure without departing from the spirit and scope of the present disclosure.

The terminology used in the description of the one or more embodiments is for the purpose of describing the particular embodiments only and is not intended to be limiting of the description of the one or more embodiments. As used in one or more embodiments of the present specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used in one or more embodiments of the present specification refers to and encompasses any and all possible combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, etc. may be used herein in one or more embodiments to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first can also be referred to as a second and, similarly, a second can also be referred to as a first without departing from the scope of one or more embodiments of the present description. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.

First, the noun terms referred to in one or more embodiments of the present specification are explained.

Crystal grain (Die): physical implementation of the chip circuitry. Each wafer can be implemented with thousands of chip circuits, and each cell on the wafer is a die.

Substrate (Substrate): in general, the substrate is a copper clad laminate.

Printed Circuit Board (PCB): also known as printed wiring boards, are important electronic components, support bodies for electronic components, and carriers for electrical interconnection of electronic components.

Wire Bonding (Wire Bonding): the utility model provides a use thin metal wire, utilize heat, pressure, ultrasonic energy to make metal lead wire and base plate pad close welding joint, realize the information intercommunication between chip and the electrical interconnection between the base plate. Under ideal control conditions, electron sharing or atomic interdiffusion can occur between the lead and the substrate, so that atomic-scale bonding between the two metals is realized.

Faraday Cage (Faraday Cage): is a cage formed of metal or a good conductor. The faraday cage is an equi-potential body, the internal potential difference is zero, and the electric field is zero.

With the development of electronic technology, the signal rate is higher and higher, and the EMI radiation problem is more and more prominent. The EMI problem is processed aiming at an electromagnetic interference source on a chip, and the EMI radiation problem can be reduced from the source. For convenience of understanding, the following description will be made of a scenario in which the chip generates electromagnetic interference in a circuit by taking the chip with four package structures as an example.

Illustratively, referring to fig. 1, fig. 1 is a diagram illustrating a first scenario in which a chip generates electromagnetic interference in a circuit. In fig. 1, the Chip package structure is a Flip Chip Ball Grid Array (FCBGA) package. Wherein, the chip includes: die, Substrate electrically connected with Die through solder balls, and PCB electrically connected with bottom of Substrate through solder balls. Electromagnetic interference of the FCBGA packaged chip is generated at the bottom of the substrate where it is connected to the PCB and is in the form of radiation.

Illustratively, referring to fig. 2, fig. 2 is a diagram illustrating a second scenario in which a chip generates electromagnetic interference in a circuit. In fig. 2, the package structure of the chip is an AIP (Antenna in package) package. The AIP package is a package structure in which an antenna and a chip are integrated in a package based on a package material and a process. Wherein, the chip includes: die, Substrate electrically connected with Die through solder balls, antenna packaged in the Substrate, and PCB electrically connected with bottom of the Substrate through solder balls. Electromagnetic interference of the chip of the AIP package is generated at the connection of the bottom of the substrate and the PCB, and at the antenna, and the electromagnetic interference is in the form of radiation.

Illustratively, referring to fig. 3, fig. 3 is a diagram illustrating a third scenario in which a chip generates electromagnetic interference in a circuit. In fig. 3, the package structure of the chip is an AOP (Antenna on package) package. Wherein, the chip includes: die, Substrate electrically connected with Die through solder balls, antenna mounted on the upper surface of the Substrate, and PCB electrically connected with the bottom of the Substrate through solder balls. The electromagnetic interference of the chip of the AOP package is generated at the connection of the bottom of the substrate and the PCB, and at the antenna, and the electromagnetic interference is in the form of radiation.

Illustratively, referring to fig. 4, fig. 4 is a diagram illustrating a fourth scenario in which a chip generates electromagnetic interference in a circuit. In fig. 4, the package structure of the chip is a POP (package on package) package. The POP packaging is used for stacking and assembling components, namely packaging body stacking packaging, and can be used for re-integrating the packaging bodies of logic and storage chips with the same appearance. Wherein, the chip includes: die1 and Die2 connected by wires and located in the same package area, Die3 connected to the bottom of Substrate1, Substrate2 electrically connected to Die3 by pins, and PCB electrically connected to the bottom of the Substrate by solder balls. Electromagnetic interference of the chip of the POP package is generated at the connection of the bottom of the substrate and the PCB and at the package areas of Die1 and Die2, and the electromagnetic interference is in the form of radiation.

In order to reduce the electromagnetic interference in the radiation form generated by the chip in the circuit, the electromagnetic interference generated by the radiation interference source can be shielded by placing a wave-absorbing material and a metal shielding case near the radiation interference source of the chip in the circuit. For ease of understanding, the electromagnetic interference shielding of the FCBGA packaged chip is taken as an example, and the electromagnetic interference shielding manner is exemplarily described below. For example, referring to fig. 5, fig. 5 is a structural example diagram of an electromagnetic interference shielding assembly for electromagnetic interference shielding by a wave-absorbing material, as shown in the figure: a wave absorbing material is placed near the source of electromagnetic interference. The EMI shielding effect of the wave-absorbing material depends on the characteristics and the size of the wave-absorbing material, and if a better shielding effect is to be realized, the size of the wave-absorbing material is relatively larger, which may violate the shielding requirement of a small-sized and small-sized space. In addition, the wave-absorbing material has the characteristic of wave-absorbing frequency band limitation, so that the mode of placing the wave-absorbing material cannot have an effect of inhibiting ultra-wideband EMI radiation. Where ultra-wideband is generally defined as a signal having a bandwidth above 1.5GHz or a bandwidth above 25% of the center frequency. In addition, the chip structure shown in fig. 5 is different from the chip structure shown in fig. 1 in that a package structure is added to the chip structure shown in fig. 5 for protecting Die. Referring to fig. 6, an exemplary structure diagram of the emi shielding assembly of fig. 6 for emi shielding by a metal shielding can is shown: the mode of utilizing metal shielding cover to realize EMI shielding, metal shielding cover need occupy certain physical space and seal including the chip, like this, just can't directly place the radiator on Die, can't adopt this scheme to the higher chip of heat dissipation demand. Also, for chips containing antennas, metal shields can cause antenna dysfunction. In addition, the emi shielding schemes shown in fig. 5 and 6 are not suitable for emi shielding of chips in an AIP package, an AOP package, and a POP package.

To provide a wider range of applications, in this specification, an emi shielding assembly is provided, and the specification relates to an emi shielding assembly manufacturing method, an emi shielding method, and a computing device, which are described in detail in the following embodiments one by one.

Referring to fig. 7, fig. 7 is a schematic structural diagram illustrating an emi shielding assembly according to an embodiment of the present disclosure, including:

a chip 702 and a circuit board 704, wherein the bottom of a substrate 7021 of the chip 702 is electrically connected to the circuit board 704;

the first ground of the base plate 7021 is in communication with the second ground of the circuit board through the connecting member 706 conforming to the predetermined dimensional condition.

Electrical connections refer to all ways of connecting different conductors inside a product. For example, the bottom of the substrate 7021 and the circuit board 704 may be connected by solder balls, wires, or the like. And, the first ground of the base plate 7021 and the second ground of the circuit board are conducted through the connecting component 706 meeting the preset size condition, so that a faraday cage can be formed. The faraday cage can enclose a radiation interference source between the chip substrate and the circuit board, thereby realizing the shielding of electromagnetic interference generated by the enclosed radiation interference source. And, the preset size condition may include: less than or equal to the size of the physical space allocated to the EMI shielding assembly in the circuit.

Moreover, the connection component 706 may specifically include: wires, conductive rubber, conductive plastic, and the like. Illustratively, the wires may be metal leads, such as gold wires, silver wires, copper wires, and the like. In a specific application, the chip 702 may be any of the package structures shown in fig. 1 to 4. In addition, the positions and the number of the first ground and the second ground connection assemblies may be set according to application requirements, which is not limited in this embodiment. Alternative embodiments are described in detail below to facilitate understanding and reasonable layout. In addition, the form of the circuit board 704 may be various. Illustratively, the circuit board 704 may be a ceramic circuit board, an alumina ceramic circuit board, a PCB, an aluminum substrate, a high frequency board, a thick copper board, a PCB, or the like. Any circuit board that can be electrically connected to the bottom of the substrate of the chip can be used in this specification, and this embodiment does not limit this.

One embodiment of the present specification forms a faraday cage by connecting the ground on the substrate with the ground of the PCB through the connecting assembly. The faraday cage can enclose a radiation interference source between the chip substrate and the circuit board, thereby realizing the shielding of electromagnetic interference generated by the enclosed radiation interference source. And, the coupling assembling accords with the predetermined dimensional condition. Thus, for a circuit with limited physical space, the size condition may be set to fit the physical space of the circuit: less than or equal to the size of the physical space allocated to the EMI shielding assembly in the circuit. Therefore, electromagnetic shielding can be achieved without extra physical space, and the shielding assembly for ensuring electromagnetic interference can be suitable for circuits with limited physical space, and is wider in application range.

In an alternative embodiment, the connection member 706 is a metal lead;

both ends of the metal lead 706 are soldered to the first ground and the second ground, respectively.

In a specific application, the first ground and the second ground can be welded together by adopting a wire bonding process. The wire bonding process is used for electrical interconnection between the chips and the substrate and information intercommunication between the chips. Therefore, the present embodiment can more reliably ensure that the connecting component 706 conforms to the preset dimension condition in the scene of shielding the electromagnetic interference source generated by the chip. And, the mode of seam is easily realized.

In an alternative embodiment, chip 702 also contains an antenna and crystal unit;

the crystal unit is mounted on the bottom of the substrate 7021, and the antenna is located above the crystal unit and mounted on the substrate 7021.

In a specific application, referring to fig. 8, a schematic structural diagram of another emi shielding assembly provided in an embodiment of the present description is shown: the antenna 7022 may be mounted on the top exterior surface of the substrate 7021. Alternatively, referring to fig. 9, a schematic structural diagram of another electromagnetic interference shielding assembly provided in an embodiment of the present specification is shown: the antenna 7022 may be mounted inside the substrate 7021. In this way, since the faraday cage formed by the connection assembly does not contain the antenna 7022, the function of the antenna can be guaranteed against the influence of the electromagnetic interference shielding assembly. Therefore, the present invention can be applied to a chip in which an antenna is packaged.

Also, the crystal unit 7023 may be specifically plural. Illustratively, it is reasonable that crystal unit 7023 can be a single crystal Die, a unit composed of a plurality of crystal dies, or the like. Any crystal unit form can be used in the present specification, and the present embodiment does not limit this.

In an optional embodiment, the chip is obtained by performing stack packaging On at least two crystal units by using a Package On Package technology, correspondingly, the number of the substrates is at least two, and at least one crystal unit is mounted On each substrate;

the first ground of the target substrate is communicated with the second ground of the circuit board through the connecting component, wherein the target substrate is the uppermost or the lowermost substrate in the substrates.

For example, referring to fig. 10, fig. 10 is a schematic structural diagram of another emi shielding assembly provided in an embodiment of the present disclosure. The chip 702 is obtained by stacking and packaging the crystal unit 7023 and the crystal unit 7024 by using a Package stacking technique Package OnPackage, and accordingly, the chip includes a substrate 7021 and a substrate 7025. In fig. 10, the target substrate 7025 is shown as a target substrate 7025, so that the substrate 7021 and the substrate 7025 are electrically connected by the stacked package, and therefore, when the substrate 7025 is used as the target substrate, it is ensured that the shielding path formed by the faraday cage between the first ground and the second ground includes the substrate 7021, so that an electromagnetic interference source generated at a connection between the substrate 7021 and the crystal unit 7024 is shielded, more electromagnetic interference can be shielded, and the shielding effect is better.

Alternatively, referring to fig. 11, fig. 11 is a schematic structural diagram of another emi shielding assembly according to an embodiment of the disclosure. The chip 702 is obtained by stacking and packaging the crystal unit 7023 and the crystal unit 7024 by using a Package stacking technique Package On Package, and accordingly, the chip includes a substrate 7021 and a substrate 7025. In fig. 10, the target substrate 7021 is shown, so that the substrate 7021 and the substrate 7025 are electrically connected by the stacked package, and therefore, when the substrate 7021 is used as the target substrate, it is ensured that the shielding path formed by the faraday cage between the first ground and the second ground includes the substrate 7025, so that an electromagnetic interference source generated at the connection between the substrate 7021 and the circuit board 704 is shielded. Furthermore, shielding of electromagnetic interference sources generated at the connection between the substrate 7021 and the crystal 7023 can be achieved. Therefore, more electromagnetic interference can be shielded, and the shielding effect is better.

In an alternative embodiment, the first ground is the ground at which the distance from the radiation source on the substrate reaches a distance threshold.

The distance between the base plate and the radiation source reaches the distance threshold, so that a Faraday cage formed by the connecting assembly can be formed near the electromagnetic interference source, namely the radiation source, and the shielding effect is guaranteed. In addition, the first place does not need to be arranged on the whole substrate, and the method is more convenient, efficient and low in cost.

In an alternative embodiment, the connecting assembly is further dimensioned according to a target frequency band of the shielded electromagnetic interference.

In a specific application, the connecting components have different sizes and different target frequency bands for shielding electromagnetic interference, and the higher the target frequency band is, the smaller the gap between the connecting components and the faraday cage formed by the first ground and the second ground is. Therefore, the size of the connecting component can be set according to the relation between the gap of the Faraday cage formed by the connecting component and the height of the target frequency band. Therefore, the shielding of the electromagnetic interference of each target frequency band can be realized according to the shielding requirement, the electromagnetic interference is not required to be limited to a certain frequency band, and the application range is wider.

In an alternative embodiment, the connecting assembly is a plurality of wires;

the wires are spaced apart from each other, and the spacing distance is set according to the frequency band of the electromagnetic interference to be shielded, and the higher the frequency band is, the smaller the spacing distance is.

By setting different spacing distances between the plurality of wires according to different frequency band shielding requirements, the problem that electromagnetic interference shielding cannot be used in an ultra-high frequency band can be avoided. Therefore, an effect of wider application range of the electromagnetic interference shielding component can be achieved.

In an optional embodiment, the emi shielding assembly may further include:

a protective structure that protects at least the connection assembly, the first ground, and the second ground.

The form of the above-described protective structure may be varied in specific applications. Illustratively, the protective structure may be a protective cover mounted on the circuit board, at least the connection assembly, the first ground, and the second ground being contained within the protective cover. Alternatively, the protective structure may be a resin encapsulation structure, and at least the connecting member, the first ground and the second ground are encapsulated in the resin encapsulation structure by a numerical potting technique. Any protection structure that can protect the connection assembly, the first ground and the second ground can be used in this specification, and this embodiment does not limit this.

For convenience of understanding, in the following, by taking an application scenario in which the connection component is a wire and the number of wires is multiple as an example, the structure of the electromagnetic shielding component provided in the embodiment of the present specification is exemplarily described for chips of various package structures.

Referring to fig. 12a, fig. 12a is a diagram illustrating a side view of an emi shielding assembly according to an embodiment of the disclosure: electromagnetic interference from the FCBGA packaged chip is generated at the substrate bottom to PCB connections, such as solder balls. Therefore, the faraday cage formed by the connection component in fig. 12a, such as the second ground of the wire connection Substrate, can contain the solder balls, thereby achieving the electromagnetic shielding effect. Also, as shown in the emi shielding assembly structure in the test scenario of fig. 12a, the number of solder balls is plural, and therefore, the number of connecting assemblies may be plural. For example, fig. 12b is a top view of an emi shielding assembly according to an embodiment of the present disclosure: in the electromagnetic interference shielding assembly structure in a top view scene, the connecting assemblies can be distributed at multiple positions of the substrate. In addition, the electromagnetic shielding assembly shown in fig. 12a includes a Mold region formed by a shielding structure such as a resin encapsulation structure. Referring to FIG. 13a, FIG. 13a is a diagram illustrating a side view of another EMI shielding assembly according to one embodiment of the present disclosure: for the chip packaged in the AIP, the embodiment of fig. 13a provides an electromagnetic shielding assembly in which the faraday cage formed between the first ground and the second ground by the connecting assembly does not contain the antenna, so that the antenna can be ensured to function normally. For example, another emi shielding assembly as illustrated in fig. 13b is provided in an exemplary top view of the structure of the emi shielding assembly according to an embodiment of the present disclosure: in the electromagnetic interference shielding assembly structure in a top view scene, the distribution of the connecting assemblies does not include the antenna. Referring to FIG. 14a, FIG. 14a is a diagram illustrating a side view of another EMI shielding assembly according to one embodiment of the present disclosure: the electromagnetic interference of the chip of the POP package is generated at the connection position of the bottom of the substrate and the PCB and the package areas of Die1 and Die2, and the faraday cage formed between the first ground and the second ground by the connecting component in fig. 14a includes the electromagnetic interference generated by the two electromagnetic interference sources, thereby realizing the electromagnetic shielding effect. The DRAM chip, i.e., a Dynamic random access Memory (Dynamic random access Memory), is packaged by POP. For example, another emi shielding assembly as illustrated in fig. 14b is provided in an exemplary top view of the structure of the emi shielding assembly according to an embodiment of the present disclosure: in the electromagnetic interference shielding component structure under the overlooking scene, the electromagnetic interference generated at the packaging areas of Die1 and Die2 in the DRAM chip and the electromagnetic interference generated at the connection part of the bottom of the substrate and the PCB are all guided to the second ground of the circuit board from the substrate through the connecting component, so that the realization of electromagnetic interference shielding can be ensured.

Corresponding to the above-mentioned embodiments, the present specification also provides an embodiment of a method for manufacturing an emi shielding assembly, and fig. 15 shows a flowchart of a method for manufacturing an emi shielding assembly according to an embodiment of the present specification. As shown in fig. 15, the manufacturing method may include the steps of:

s1502, obtaining a circuit board, a target chip and a connecting component which meets the preset size condition;

s1504, electrically connecting the bottom of the substrate of the target chip with a circuit board;

s1506, the first ground of the substrate is conducted to the second ground of the circuit board by the connecting component, so as to obtain the emi shielding component.

One embodiment of the present specification forms a faraday cage by connecting the ground on the substrate with the ground of the PCB through the connecting assembly. The faraday cage can enclose a radiation interference source between the chip substrate and the circuit board, thereby realizing the shielding of electromagnetic interference generated by the enclosed radiation interference source. And, the coupling assembling accords with preset size condition. Thus, for a circuit with limited physical space, the size condition may be set to fit the physical space of the circuit: less than or equal to the size of the physical space allocated to the EMI shielding assembly in the circuit. Therefore, electromagnetic shielding can be achieved without extra physical space, and the shielding assembly for ensuring electromagnetic interference can be suitable for circuits with limited physical space, and is wider in application range.

In an alternative embodiment, the connecting member is a metal lead;

accordingly, the above-mentioned conducting the first ground of the substrate and the second ground of the circuit board by using the connecting assembly may specifically include the following steps:

and welding two ends of the metal lead with the first ground of the substrate and the second ground of the circuit board respectively.

In an optional implementation manner, the obtaining of the target chip may specifically include the following steps:

obtaining a crystal unit, an antenna and a substrate;

mounting the crystal unit on the bottom of the substrate;

and mounting the antenna at a target position on the substrate to obtain a target chip, wherein the target position is above the crystal unit.

In an optional implementation manner, the obtaining the target chip may specifically include the following steps:

at least two crystal units are stacked and packaged On at least two substrates by using a Package On Package technology to obtain a target chip, wherein at least one crystal unit is mounted On each substrate;

and communicating the first ground of the target substrate with the second ground of the circuit board by using the connecting assembly, wherein the target substrate is the uppermost or lowermost substrate in the substrates.

In an alternative embodiment, the first ground is a ground at which the distance from the radiation source on the substrate reaches a distance threshold; and/or the presence of a gas in the gas,

the connecting component is a plurality of wires, intervals exist among the wires, the distance of the intervals is set according to the frequency band of the shielded electromagnetic interference, and the higher the frequency band is, the smaller the distance of the intervals is.

In an optional embodiment, the above-mentioned obtaining the electromagnetic interference shielding assembly by conducting the first ground of the substrate and the second ground of the circuit board by using the connecting assembly may specifically include the following steps:

conducting the first ground of the substrate and the second ground of the circuit board by using the connecting assembly to obtain a circuit to be protected;

obtaining a protective structure;

according to a preset adding rule, a protection structure is added in a circuit to be protected to obtain the electromagnetic interference shielding assembly, wherein the preset adding rule is that the protection structure at least protects the connecting assembly, the first ground and the second ground.

In a specific application, in any of the above embodiments of the method for manufacturing an emi shielding assembly, the obtaining of each component may be performed by an automated device such as a robot or manually, and similarly, the connection of each component may be performed by an automated device such as a robot or manually, which is reasonable. Any technical means capable of realizing the above-mentioned manufacturing method can be used in the present specification, and the present embodiment does not limit this.

The above is a schematic scheme of a method of manufacturing an emi shielding assembly according to the present embodiment. It should be noted that the technical solution of the method for manufacturing the electromagnetic interference shielding assembly belongs to the same concept as the above-mentioned technical solution of the electromagnetic interference shielding assembly, and details of the technical solution of the method for manufacturing the electromagnetic interference shielding assembly, which are not described in detail, can be referred to the above-mentioned description of the technical solution of the electromagnetic interference shielding assembly.

Corresponding to the above component embodiments, the present specification further provides an electromagnetic interference shielding method embodiment, and fig. 16 shows a flowchart of an electromagnetic interference shielding method provided by an embodiment of the present specification. As shown in fig. 16, the emi shielding method may include the steps of:

s1602, determining a target chip and a target circuit board in a target circuit, wherein the target circuit board is electrically connected with the bottom of a substrate of the target chip;

and S1604, arranging a connecting component for conducting the first ground of the substrate and the second ground of the circuit board in the target circuit, wherein the connecting component meets the preset size condition.

One embodiment of the present specification forms a faraday cage by connecting the ground on the substrate with the ground of the PCB through the connecting assembly. The faraday cage can enclose a radiation interference source between the chip substrate and the circuit board, thereby realizing the shielding of electromagnetic interference generated by the enclosed radiation interference source. And, the coupling assembling accords with preset size condition. Thus, for a circuit with limited physical space, the size condition may be set to fit the physical space of the circuit: less than or equal to the size of the physical space allocated for emi shielding components in the circuit. Therefore, electromagnetic shielding can be achieved without extra physical space, and the shielding assembly for ensuring electromagnetic interference can be suitable for circuits with limited physical space, and is wider in application range.

In an alternative embodiment, the connecting member is a metal lead;

accordingly, the step of providing the connection assembly for connecting the first ground of the substrate and the second ground of the circuit board in the target circuit may specifically include the following steps:

In an optional implementation manner, the determining a target chip in the target circuit may specifically include the following steps:

and identifying a chip comprising a crystal unit, an antenna and a substrate to obtain a target chip, wherein the crystal unit is arranged at the bottom of the substrate, the antenna is arranged at a target position on the substrate, and the target position is above the crystal unit.

identifying a target chip obtained by performing lamination packaging on at least two substrates and at least two crystal units by using a Package body lamination technology Package OnPackage, wherein at least one crystal unit is arranged on each substrate;

In an optional implementation manner, after the connection component is disposed in the target circuit to conduct the first ground of the substrate with the second ground of the circuit board, the electromagnetic shielding method provided in an embodiment of the present specification may further include the following steps:

obtaining a protective structure;

and adding a protective structure in the circuit to be protected according to a preset adding rule, wherein the preset adding rule is that the protective structure at least protects the connecting component, the first ground and the second ground.

Fig. 17 shows a block diagram of a computing device provided in an embodiment of the present specification. Components of the computing device 1700 include, but are not limited to, an electromagnetic interference shield assembly 1702. In one case, the computing device may be a block diagram of another computing device provided in one embodiment of the present specification shown in fig. 18. Components of the computing device 1800 include, but are not limited to, memory 1810 and processor 1820. The processor 1820 is coupled to the memory 1810 via the bus 1830, and the database 1850 is used for storing data.

Computing device 1800 also includes access device(s) 1840, which access device(s) 1840 enable computing device 1800 to communicate via one or more networks 1860. Among the components of the computing device 1800 shown in FIG. 18, the components that comprise the chip may include EMI shielding components (not shown). Also, examples of the above-described Network include a Public Switched Telephone Network (PSTN), a Local Area Network (LAN), a Wide Area Network (WAN), a Personal Area Network (PAN), or a combination of communication networks such as the internet. The Access device 1840 may include one or more of any type of Network Interface (e.g., a Network Interface Controller (NIC)) whether wired or Wireless, such as an IEEE802.11 Wireless Local Area Network (WLAN) Wireless Interface, a Worldwide Interoperability for Microwave Access (Wi-MAX) Interface, an ethernet Interface, a Universal Serial Bus (USB) Interface, a cellular Network Interface, a bluetooth Interface, a Near Field Communication (NFC) Interface, and so forth.

In one embodiment of the specification, the above-described components of computing device 1800, as well as other components not shown in FIG. 18, may also be connected to each other, such as by a bus. It should be understood that the block diagram of the computing device structure shown in FIG. 18 is for purposes of example only and is not limiting as to the scope of the description. Those skilled in the art may add or replace other components as desired.

The computing device 1800 may be any type of stationary or mobile computing device, including a mobile computer or mobile computing device (e.g., tablet, personal digital assistant, laptop, notebook, netbook, etc.), mobile phone (e.g., smartphone), wearable computing device (e.g., smartwatch, smartglasses, etc.), or other type of mobile device, or a stationary computing device such as a desktop computer or PC. Computing device 1700 may also be a mobile or stationary server.

The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.

It should be noted that, for the sake of simplicity, the foregoing method embodiments are described as a series of acts, but those skilled in the art should understand that the present embodiment is not limited by the described acts, because some steps may be performed in other sequences or simultaneously according to the present embodiment. Further, those skilled in the art should also appreciate that the embodiments described in this specification are preferred embodiments and that acts and modules referred to are not necessarily required for an embodiment of the specification.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The preferred embodiments of the present specification disclosed above are intended only to aid in the description of the specification. Alternative embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the embodiments and the practical application, to thereby enable others skilled in the art to best understand and utilize the embodiments. The specification is limited only by the claims and their full scope and equivalents.

Claims

1. An electromagnetic interference shielding assembly comprising:

2. The EMI shielding assembly of claim 1, said connection assembly being a metal lead;

and two ends of the metal lead are respectively welded with the first ground and the second ground.

3. The emi shielding assembly of claim 1, the chip further comprising an antenna and a crystal unit;

the crystal unit is installed at the bottom of the substrate, and the antenna is located above the crystal unit and installed on the substrate.

4. The EMI shielding assembly of claim 1, the chip is obtained by packaging at least two crystal units in a stack by using a Package On Package technology, accordingly, the number of the substrates is at least two, and at least one crystal unit is mounted On each substrate;

the first ground of target base plate and the second ground of circuit board pass through coupling assembling switches on, wherein, the target base plate is lieing in the top or the bottommost base plate in each base plate.

5. The EMI shield assembly as set forth in any one of claims 1-4, wherein the first ground is a ground that is a distance from a radiation source on the substrate that reaches a threshold distance.

6. The EMI shielding assembly of any one of claims 1-4, said connection assembly further sized according to a target frequency band of the shielded EMI.

7. The EMI shielding assembly as set forth in claim 6, said connecting assembly being a plurality of wires;

intervals exist among all the wires, the distance of the intervals is set according to the target frequency band of the shielded electromagnetic interference, and the higher the frequency band is, the smaller the distance of the intervals is.

8. The EMI shielding assembly of any one of claims 1-4, further comprising:

9. A method of manufacturing an emi shielding assembly, comprising:

10. The method of manufacturing an emi shielding assembly of claim 9, wherein the connecting assembly is a metal lead;

correspondingly, the utilizing the connection assembly to conduct the first ground of the substrate with the second ground of the circuit board includes:

11. The emi shielding assembly manufacturing method of claim 9, the obtaining the target chip comprising:

at least two crystal units are stacked and packaged On at least two substrates by using a Package On Package technology to obtain the target chip, wherein at least one crystal unit is mounted On each substrate;

and communicating the first ground of the target substrate with the second ground of the circuit board by using the connecting component, wherein the target substrate is the uppermost or the lowermost substrate in the substrates.

12. The method of manufacturing an emi shielding assembly of any one of claims 9-11, wherein the first ground is a ground that is a distance from a radiation source on the substrate that reaches a threshold distance; and/or the presence of a gas in the atmosphere,

the coupling assembling is the wire, the quantity of wire is a plurality of, has the interval between each wire, the spaced distance sets up according to shielded electromagnetic interference's frequency band, the frequency band is higher, the spaced distance is littleer.

13. An electromagnetic interference shielding method, comprising:

14. A computing device, comprising: the EMI shielding assembly of any one of claims 1 to 8.