CN106340506A - Semiconductor packaging structure and manufacturing method thereof - Google Patents
Semiconductor packaging structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN106340506A CN106340506A CN201610913788.4A CN201610913788A CN106340506A CN 106340506 A CN106340506 A CN 106340506A CN 201610913788 A CN201610913788 A CN 201610913788A CN 106340506 A CN106340506 A CN 106340506A
- Authority
- CN
- China
- Prior art keywords
- metallic plate
- substrate
- semiconductor package
- chip
- manufacture method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to a semiconductor packaging structure and a manufacturing method thereof. The structure comprises a substrate (1) which includes a grounding line and on the front side of which a metallic plate (2) is mounted through conductive material. The metallic plate (2) is connected with the grounding line, and a hole (3) is arranged in the metallic plate (2). A chip (4) is arranged on the substrate (1) at the hole (3) area, and the plastic packaging material (5) encloses and packs the metallic plate (2) and chip (4). The side surfaces of the substrate (1) and the metallic plate (2) and the external surface of the plastic packaging material (5) are coated with a shielding metallic layer (6), and the shielding metallic layer (6) is connected with the side surface of the metallic plate (2). The semiconductor packaging structure and the manufacturing method thereof solve the problem of poor grounding effect in the prior art, improve production efficiency, simplify process and ensure excellent electromagnetic shielding effect.
Description
Technical field
The present invention relates to a kind of semiconductor package and preparation method thereof, belong to technical field of semiconductor encapsulation.
Background technology
Because radio frequency package structure is easily subject to extraneous electromagnetic interference, when it is mounted on circuit boards, should be especially
Note mutual interference, in order to avoid running occurs extremely.In order to reach the effect of shielding, shield assembly is set above chip,
And shield assembly is grounded, thus can shield chip in order to avoid being subject to extraneous electromagnetic interference.The mode of shield assembly ground connection has
Multiple, have as shown in figure 1, arranging multiple earth conductors 40, screen layer 70 in surface, screen layer 70 and earth conductor 40 connect
Touch, and be grounded, electromagnetic shielding is carried out with this, in this structure, earth conductor is to be placed on one by one on substrate, and the activity duration is relatively
Long, and earth conductor is with tin cream or conducting resinl, is formed by Reflow Soldering or after being heating and curing, it is possible to create height
Degree is variant, leads to may not cut to corresponding position when cutting, this will make screen layer and earth conductor connect
Touch bad, screen layer cannot be grounded, and certainly have impact on function of shielding.
Content of the invention
The technical problem to be solved be for above-mentioned prior art provide a kind of semiconductor package and its
Manufacture method, it can solve the problem that the bad problem of earthing effect in prior art, energy improve production efficiency, Simplified flowsheet, plays
Effectiveness well.
The present invention the adopted technical scheme that solves the above problems is: a kind of semiconductor package, it includes substrate, institute
State substrate and include ground path, described substrate front side is pasted with metallic plate by conductive material, described metallic plate and ground path
It is connected, described metallic plate is provided with perforate, the substrate of described opening area is provided with chip, outside described metallic plate and chip
Enclose and be encapsulated with plastic packaging material, described substrate and sheetmetal side and plastic packaging material outer surface are all coated with shielding metal level, described screen
Cover metal level to be connected with sheetmetal side.
A kind of manufacture method of semiconductor package, the method comprising the steps of:
Step one, take a metallic plate；
Step 2, the metallic plate in step one is done perforate process；
Step 3, the metallic plate after perforate and substrate are fitted by conductive material, the earth lead on metallic plate and substrate
Road is electrically connected with, and forms ground structure；
Step 4, on the substrate of opening area pasting chip；
Step 5, metallic plate and chip periphery carry out plastic packaging material encapsulating；
Step 6, by encapsulating after semi-finished product cut into single unit；
Step 7, single cell surface after cutting is covered shielding metal level.
Four angles of the metallic plate in step one and marginal area have the telltale mark point for identification.
Described telltale mark point is square, cross or trapezoidal.
Described perforate processing mode is radium-shine mode, mechanical punching mode or chemical etching mode.
Described hole is in that matrix-style arranges.
Described coverage mode is chemical vapor deposition, electroless plating, electrolysis plating, the technique side of spraying, printing or sputter
Method.
Compared with prior art, it is an advantage of the current invention that:
1st, full wafer metallic plate and entire substrate are fitted, directly formed ground structure, can Simplified flowsheet, material-saving and when
Between；
2nd, earth conductor does not need single to be configured, and is integrally formed, and improves efficiency, increases product reliability.
Brief description
Fig. 1 is a kind of schematic diagram of existing shield assembly earthing mode.
Fig. 2 is a kind of schematic diagram of semiconductor package of the present invention.
Fig. 3 ~ Fig. 9 is a kind of each operation flow chart of the manufacture method of semiconductor package of the present invention.
Wherein:
Substrate 1
Metallic plate 2
Perforate 3
Chip 4
Plastic packaging material 5
Shielding metal level 6.
Specific embodiment
Below in conjunction with accompanying drawing embodiment, the present invention is described in further detail.
As shown in Fig. 2 one of the present embodiment semiconductor package, it includes substrate 1, described substrate 1, described base
Plate 1 includes ground path, and described substrate 1 front is pasted with metallic plate 2, described metallic plate 2 and ground path by conductive material
It is connected, described metallic plate 2 is provided with perforate 3, the substrate 1 in described perforate 3 region is provided with chip 4, described metallic plate 2 He
Chip 4 periphery is encapsulated with plastic packaging material 5, and described substrate 1 and metallic plate 2 side and plastic packaging material 5 outer surface are all coated with shielding gold
Belong to layer 6, described shielding metal level 6 is connected with metallic plate 2 side.
Its manufacture method is as follows:
Step one, referring to Fig. 3, take a metallic plate, four angles of this metallic plate and marginal area have for identification telltale mark
Point, this telltale mark point can be square, cross or the shape such as trapezoidal；
Step 2, referring to Fig. 4, the metallic plate in step one is done perforate and processes, processing mode can be radium-shine mode, machinery punching
Mode or chemical etching mode；
Described hole is in that matrix-style arranges；
Step 3, referring to Fig. 5, the full wafer metallic plate after perforate and substrate are fitted by conductive material, metallic plate and base
Ground path on plate is electrically connected with, and forms ground structure；
Step 4, referring to Fig. 6, pasting chip on the substrate of opening area, chip can have multiple；
Step 5, referring to Fig. 7, metallic plate and chip periphery carry out plastic packaging material encapsulating；
Step 6, referring to Fig. 8, the semi-finished product after encapsulating are cut into single unit, metallic plate is exposed in side；
Step 7, referring to Fig. 9, single cell surface after cutting is covered shielding metal level, shielding metal level can for gold, silver,
The combination of copper, nickel, chromium, stannum, aluminum etc. or more various metals material, coverage mode can be chemical vapor deposition, electroless plating,
The processes such as electrolysis plating, spraying, printing or sputter.
In addition to the implementation, present invention additionally comprises there being other embodiment, all employing equivalents or equivalence replacement
The technical scheme that mode is formed, all should fall within the scope of the hereto appended claims.
Claims (7)
1. a kind of semiconductor package it is characterised in that: it includes substrate (1), described substrate (1), and described substrate (1) includes
Ground path, described substrate (1) front is pasted with metallic plate (2), described metallic plate (2) and ground path phase by conductive material
Connect, described metallic plate (2) is provided with perforate (3), the substrate (1) in described perforate (3) region is provided with chip (4), described
Metallic plate (2) and chip (4) periphery are encapsulated with plastic packaging material (5), described substrate (1) and metallic plate (2) side and plastic packaging material (5)
Outer surface is all coated with shielding metal level (6), and described shielding metal level (6) is connected with metallic plate (2) side.
2. a kind of manufacture method of semiconductor package is it is characterised in that the method comprising the steps of:
Step one, take a metallic plate；
Step 2, the metallic plate in step one is done perforate process；
Step 3, the metallic plate after perforate and substrate are fitted by conductive material, the earth lead on metallic plate and substrate
Road is electrically connected with, and forms ground structure；
Step 4, on the substrate of opening area pasting chip；
Step 5, metallic plate and chip periphery carry out plastic packaging material encapsulating；
Step 6, by encapsulating after semi-finished product cut into single unit；
Step 7, single cell surface after cutting is covered shielding metal level.
3. a kind of semiconductor package according to claim 2 manufacture method it is characterised in that: the gold in step one
Belong to four angles of plate and marginal area has the telltale mark point for identification.
4. a kind of semiconductor package according to claim 3 manufacture method it is characterised in that: described telltale mark
Point is square, cross or trapezoidal.
5. a kind of semiconductor package according to claim 2 manufacture method it is characterised in that: described perforate is processed
Mode is radium-shine mode, mechanical punching mode or chemical etching mode.
6. a kind of semiconductor package according to claim 2 manufacture method it is characterised in that: the core of described attachment
Piece quantity can have multiple.
7. a kind of semiconductor package according to claim 2 manufacture method it is characterised in that: described coverage mode
It is chemical vapor deposition, electroless plating, electrolysis plating, the process of spraying, printing or sputter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610913788.4A CN106340506A (en) | 2016-10-20 | 2016-10-20 | Semiconductor packaging structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610913788.4A CN106340506A (en) | 2016-10-20 | 2016-10-20 | Semiconductor packaging structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106340506A true CN106340506A (en) | 2017-01-18 |
Family
ID=57840312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610913788.4A Pending CN106340506A (en) | 2016-10-20 | 2016-10-20 | Semiconductor packaging structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106340506A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107507824A (en) * | 2017-09-13 | 2017-12-22 | 尚睿微电子（上海）有限公司 | A kind of encapsulating structure with electro-magnetic screen function and preparation method thereof |
| CN107690228A (en) * | 2017-09-05 | 2018-02-13 | 环维电子(上海)有限公司 | A kind of preparation method of electronics module and a kind of PCB substrate |
| CN110610906A (en) * | 2019-09-24 | 2019-12-24 | 深圳佰维存储科技股份有限公司 | Semiconductor electromagnetic shielding structure and manufacturing method thereof |
| CN111180419A (en) * | 2018-11-09 | 2020-05-19 | 三星电子株式会社 | Semiconductor package and electromagnetic interference shielding structure for semiconductor package |
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| US20050280139A1 (en) * | 2004-06-21 | 2005-12-22 | Broadcom Corporation | Multipiece apparatus for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages and method of making the same |
| CN101728364A (en) * | 2008-10-31 | 2010-06-09 | 日月光半导体制造股份有限公司 | Chip package and manufacturing method thereof |
| CN101814484A (en) * | 2009-02-19 | 2010-08-25 | 日月光半导体制造股份有限公司 | Chip package and manufacturing method thereof |
| CN102376628A (en) * | 2010-08-17 | 2012-03-14 | 环旭电子股份有限公司 | Manufacturing method and package structure for system in package module |
| CN102969303A (en) * | 2012-10-26 | 2013-03-13 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and production method thereof |
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2016
- 2016-10-20 CN CN201610913788.4A patent/CN106340506A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050280139A1 (en) * | 2004-06-21 | 2005-12-22 | Broadcom Corporation | Multipiece apparatus for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages and method of making the same |
| CN101728364A (en) * | 2008-10-31 | 2010-06-09 | 日月光半导体制造股份有限公司 | Chip package and manufacturing method thereof |
| CN101814484A (en) * | 2009-02-19 | 2010-08-25 | 日月光半导体制造股份有限公司 | Chip package and manufacturing method thereof |
| CN102376628A (en) * | 2010-08-17 | 2012-03-14 | 环旭电子股份有限公司 | Manufacturing method and package structure for system in package module |
| CN102969303A (en) * | 2012-10-26 | 2013-03-13 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and production method thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107690228A (en) * | 2017-09-05 | 2018-02-13 | 环维电子(上海)有限公司 | A kind of preparation method of electronics module and a kind of PCB substrate |
| CN107507824A (en) * | 2017-09-13 | 2017-12-22 | 尚睿微电子（上海）有限公司 | A kind of encapsulating structure with electro-magnetic screen function and preparation method thereof |
| CN111180419A (en) * | 2018-11-09 | 2020-05-19 | 三星电子株式会社 | Semiconductor package and electromagnetic interference shielding structure for semiconductor package |
| CN111180419B (en) * | 2018-11-09 | 2023-08-15 | 三星电子株式会社 | Semiconductor package and electromagnetic interference shielding structure for the same |
| CN110610906A (en) * | 2019-09-24 | 2019-12-24 | 深圳佰维存储科技股份有限公司 | Semiconductor electromagnetic shielding structure and manufacturing method thereof |
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| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170118 |
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| RJ01 | Rejection of invention patent application after publication |