CN102368494A - Anti-electromagnetic interference chip packaging structure - Google Patents
Anti-electromagnetic interference chip packaging structure Download PDFInfo
- Publication number
- CN102368494A CN102368494A CN2011103050884A CN201110305088A CN102368494A CN 102368494 A CN102368494 A CN 102368494A CN 2011103050884 A CN2011103050884 A CN 2011103050884A CN 201110305088 A CN201110305088 A CN 201110305088A CN 102368494 A CN102368494 A CN 102368494A
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- China
- Prior art keywords
- chip
- electromagnetic interference
- circuit board
- substrate
- packaging structure
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
The invention discloses an anti-electromagnetic interference chip packaging structure. The anti-electromagnetic interference chip packaging structure mainly comprises: a circuit board, a substrate, a chip, a conducting layer, a packaging body and a metal shell. The structure is characterized in that: the circuit board possesses a bearing surface and a plurality of grounding pads; the substrate is arranged on the circuit board; the chip is arranged on the substrate; the conducting layer is arranged out of the chip and the substrate; the conducting layer is electrically connected with the grounding pads on the circuit board through a conductive line; the packaging body covers out of the conducting layer; the metal shell sticks out of the packaging body and is electrically connected with the grounding pads on the circuit board. The invention discloses the anti-electromagnetic interference chip packaging structure. The structure possesses a double anti-electromagnetism interference ability. Electromagnetic radiation can be led out effectively through grounding. A high efficiency operation of the chip can be ensured. Simultaneously, chip packaging technology costs are low, enforcement is simple and the structure is suitable for patch production.
Description
Technical field
The present invention relates to a kind of encapsulating structure of chip, relate in particular to a kind of novel chip packaging structure that the obstruct electromagnetic interference can be arranged, belong to the chip encapsulation technology field.
Background technology
In the making of integrated circuit, chip is to obtain through steps such as wafer manufacturing, formation integrated circuit and cutting crystal wafers.After the production of integrated circuits of wafer was accomplished, cutting formed chip by wafer can outwards be electrically connected on the carrier; Wherein, carrier can be pin frame or substrate, is electrically connected to carrier and chip can adopt routing to combine or cover the brilliant mode that combines.Like fruit chip and carrier is to electrically connect with the mode that routing combines, then enter into insert sealing making step to constitute chip packing-body.Chip encapsulation technology wraps up chip exactly, contacts with extraneous to avoid chip, prevents a kind of technology of the infringement of outer bound pair chip.Airborne impurity and bad air, so steam all can corrode the precision circuit on the chip, and then cause electric property to descend.Different encapsulation technologies is widely different in manufacturing process and process aspect, and crucial effects is also played to the performance of memory chip self performance in the encapsulation back.Along with the develop rapidly of photoelectricity, little electric manufacturing process technology, electronic product all the time towards littler, gentlier, more cheap direction develops, so the packing forms of chip component also constantly is improved.
Along with people's improves constantly the functional requirement of electronic product, and high performance chips miscellaneous is widely used in the various electric equipments.These merit high performance chipses receive effect of electromagnetic radiation easily in running, upset its running frequency, have reduced the job stability of electric equipment.
Summary of the invention
To the demand; The invention provides a kind of chip-packaging structure of anti-electromagnetic interference; This encapsulating structure is reasonable in design; When guaranteeing chip well packaged performance, give outstanding electro-magnetic screen function, can effectively intercept the electromagenetic wave radiation that peripheral electric equipment discharges, guaranteed the efficient operation of chip.
The present invention is a kind of chip-packaging structure of anti-electromagnetic interference, and the chip-packaging structure of this anti-electromagnetic interference mainly comprises circuit board, substrate, chip, conductive layer, packaging body and metal shell, it is characterized in that; Described circuit board has a loading end and many places ground mat; Substrate is arranged on the circuit board, and chip is arranged on the substrate, and the described chip and the substrate outside are provided with conductive layer; This conductive layer electrically connects through the ground mat on conducting wire and the circuit board; Described packaging body coats is outside conductive layer, and described metal shell is attached to outside the packaging body, and electrically connects with ground mat on the circuit board.
In the present invention's one preferred embodiment, adopt welding procedure to electrically connect between described chip and the substrate.
In the present invention's one preferred embodiment, between described substrate and the circuit board conducting sphere is set, and adopts viscose glue to coat.
In the present invention's one preferred embodiment, described baseplate material can adopt the silicon chip or the copper-clad plate of excellent radiation performance.
In the present invention's one preferred embodiment, described conductive layer base material is a silica gel, and forms the conducting wire through plating, spraying or sputtering process.
In the present invention's one preferred embodiment, described conducting wire is parallel to be distributed on the skin of conductive layer, and its quantity is the 10-40 bar.
In the present invention's one preferred embodiment, the thickness of described conductive layer is generally 20-100um.
The present invention has disclosed a kind of chip-packaging structure of anti-electromagnetic interference, and this structure has dual anti-electromagnetic interference capability, can electromagnetic radiation be drawn through effective grounding, guarantees the efficient operation of chip; Simultaneously, the chip package process cost is low, is easy to implement, and is suitable for producing in batches.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is the structural representation of the chip-packaging structure of the anti-electromagnetic interference of the embodiment of the invention;
The mark of each parts is following in the accompanying drawing: 1, circuit board, 2, substrate, 3, chip, 4, conductive layer, 5, packaging body, 6, metal shell, 7, ground mat, 8, the conducting wire, 9, conducting sphere.
Embodiment
Below in conjunction with accompanying drawing preferred embodiment of the present invention is set forth in detail, thereby protection scope of the present invention is made more explicit defining so that advantage of the present invention and characteristic can be easier to it will be appreciated by those skilled in the art that.
Fig. 1 is the structural representation of the chip-packaging structure of the anti-electromagnetic interference of the embodiment of the invention; The chip-packaging structure of this anti-electromagnetic interference mainly comprises circuit board 1, substrate 2, chip 3, conductive layer 4, packaging body 5 and metal shell 6; It is characterized in that described circuit board 1 has a loading end and many places ground mat 7, substrate 2 is arranged on the circuit board 1; Chip 3 is arranged on the substrate 2; Described chip 3 is provided with conductive layer 4 with substrate 2 outsides, and this conductive layer 4 electrically connects through the ground mat on conducting wire 8 and the circuit board 17, and described packaging body 5 is coated on outside the conductive layer 4; Described metal shell 6 is attached to outside the packaging body 5, and electrically connects with ground mat 7 on the circuit board 1.
Adopt welding procedure to electrically connect between the chip-packaging structure chips 3 of the anti-electromagnetic interference that the present invention mentions and the substrate 2, this welding procedure is generally hot pressing welding, ultrasonic wire bonding method and thermosonic bonding and connects method.
Between substrate 2 and the circuit board 1 conducting sphere 9 is set, conducting sphere 9 can adopt annular or rectangular arranged, realizes the electric connection of substrate 2 and circuit board 1 through conducting sphere 9; Simultaneously, use viscose glue to carry out conducting sphere 9 is coated, improve connective stability; Substrate 2 materials can adopt the silicon chip or the copper-clad plate of excellent radiation performance.
The base material of conductive layer 4 is a silica gel, forms conducting wire 8 through plating, spraying or sputtering process; The conducting wire 8 parallel skins that are distributed in conductive layer 4, its material is generally copper or silver, and quantity is the 10-40 bar, and conductive layer 4 thickness of formation are generally 20-100um; Conducting wire 8 electrically connects with the ground mat 7 of circuit board 1, forms the inner shield structure.
Metal shell 6 is attached to outside the packaging body 5, and electrically connects with ground mat 7 on the circuit board 1, and its material is generally selected copper or aluminium alloy for use, and thickness is 1-2mm; Metal shell 6 has excellent conducting performance and intensity, forms outer shielding structure.
The present invention has disclosed a kind of chip-packaging structure of anti-electromagnetic interference, is characterized in: this structure has dual anti-electromagnetic interference capability, can electromagnetic radiation be drawn through effective grounding, guarantees the efficient operation of chip; Simultaneously, the chip package process cost is low, is easy to implement, and is suitable for producing in batches.
The above; Be merely embodiment of the present invention; But protection scope of the present invention is not limited thereto; Any those of ordinary skill in the art are in the technical scope that the present invention disclosed, and variation or the replacement that can expect without creative work all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range that claims were limited.
Claims (7)
1. the chip-packaging structure of an anti-electromagnetic interference, the chip-packaging structure of this anti-electromagnetic interference mainly comprises circuit board, substrate, chip, conductive layer, packaging body and metal shell, it is characterized in that; Described circuit board has a loading end and many places ground mat; Substrate is arranged on the circuit board, and chip is arranged on the substrate, and the described chip and the substrate outside are provided with conductive layer; This conductive layer electrically connects through the ground mat on conducting wire and the circuit board; Described packaging body coats is outside conductive layer, and described metal shell is attached to outside the packaging body, and electrically connects with ground mat on the circuit board.
2. require the chip-packaging structure of 1 described anti-electromagnetic interference according to power, it is characterized in that, adopt welding procedure to electrically connect between described chip and the substrate.
3. the chip-packaging structure of anti-electromagnetic interference according to claim 2 is characterized in that, between described substrate and the circuit board conducting sphere is set, and adopts viscose glue to coat.
4. require the chip-packaging structure of 3 described anti-electromagnetic interference according to power, it is characterized in that, described baseplate material can adopt the silicon chip or the copper-clad plate of excellent radiation performance.
5. the chip-packaging structure of anti-electromagnetic interference according to claim 1 is characterized in that, described conductive layer base material is a silica gel, and forms the conducting wire through plating, spraying or sputtering process.
6. the chip-packaging structure of anti-electromagnetic interference according to claim 5 is characterized in that, described conducting wire is parallel to be distributed on the skin of conductive layer, and its quantity is the 10-40 bar.
7. the chip-packaging structure of anti-electromagnetic interference according to claim 5 is characterized in that, the thickness of described conductive layer is generally 20-100um.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103050884A CN102368494A (en) | 2011-10-11 | 2011-10-11 | Anti-electromagnetic interference chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103050884A CN102368494A (en) | 2011-10-11 | 2011-10-11 | Anti-electromagnetic interference chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102368494A true CN102368494A (en) | 2012-03-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011103050884A Pending CN102368494A (en) | 2011-10-11 | 2011-10-11 | Anti-electromagnetic interference chip packaging structure |
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| CN (1) | CN102368494A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103715150A (en) * | 2012-09-30 | 2014-04-09 | 申宇慈 | Die cap and flip chip package with die cap |
| CN105489600A (en) * | 2015-12-25 | 2016-04-13 | 苏州东山精密制造股份有限公司 | Light emitting diode (LED) module and display device |
| WO2018076471A1 (en) * | 2016-10-27 | 2018-05-03 | 深圳市大疆创新科技有限公司 | Unmanned aerial vehicle |
| CN109755185A (en) * | 2019-01-03 | 2019-05-14 | 长江存储科技有限责任公司 | The packaging method of package body structure and semiconductor devices |
| CN110431675A (en) * | 2017-03-13 | 2019-11-08 | 欧司朗光电半导体有限公司 | Device with enhancement layer and the method for manufacturing device |
| CN112635436A (en) * | 2020-12-17 | 2021-04-09 | 长江存储科技有限责任公司 | Chip packaging structure and preparation method thereof |
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| US20030116836A1 (en) * | 2001-12-21 | 2003-06-26 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with enhanced electrical and thermal performance and method for fabricating the same |
| CN101276805A (en) * | 2007-06-15 | 2008-10-01 | 日月光半导体制造股份有限公司 | Semiconductor encapsulation structure with electromagnetic interference shield function and manufacturing method thereof |
| US20080258294A1 (en) * | 2007-04-23 | 2008-10-23 | Siliconware Precision Industries Co., Ltd. | Heat-dissipating semiconductor package structure and method for manufacturing the same |
| CN101315919A (en) * | 2007-07-30 | 2008-12-03 | 日月光半导体制造股份有限公司 | Chip packaging structure and technique |
| US20090065911A1 (en) * | 2007-09-12 | 2009-03-12 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and manufacturing method thereof |
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2011
- 2011-10-11 CN CN2011103050884A patent/CN102368494A/en active Pending
Patent Citations (7)
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| US20030116836A1 (en) * | 2001-12-21 | 2003-06-26 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with enhanced electrical and thermal performance and method for fabricating the same |
| US20080258294A1 (en) * | 2007-04-23 | 2008-10-23 | Siliconware Precision Industries Co., Ltd. | Heat-dissipating semiconductor package structure and method for manufacturing the same |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103715150A (en) * | 2012-09-30 | 2014-04-09 | 申宇慈 | Die cap and flip chip package with die cap |
| CN105489600A (en) * | 2015-12-25 | 2016-04-13 | 苏州东山精密制造股份有限公司 | Light emitting diode (LED) module and display device |
| WO2018076471A1 (en) * | 2016-10-27 | 2018-05-03 | 深圳市大疆创新科技有限公司 | Unmanned aerial vehicle |
| CN110431675A (en) * | 2017-03-13 | 2019-11-08 | 欧司朗光电半导体有限公司 | Device with enhancement layer and the method for manufacturing device |
| CN109755185A (en) * | 2019-01-03 | 2019-05-14 | 长江存储科技有限责任公司 | The packaging method of package body structure and semiconductor devices |
| CN112635436A (en) * | 2020-12-17 | 2021-04-09 | 长江存储科技有限责任公司 | Chip packaging structure and preparation method thereof |
| CN112635436B (en) * | 2020-12-17 | 2023-12-15 | 长江存储科技有限责任公司 | Chip packaging structure and preparation method thereof |
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| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
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Application publication date: 20120307 |