CN100511614C - Package method for multi-chip stack and package structure thereof - Google Patents
Package method for multi-chip stack and package structure thereof Download PDFInfo
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- CN100511614C CN100511614C CN 200610082830 CN200610082830A CN100511614C CN 100511614 C CN100511614 C CN 100511614C CN 200610082830 CN200610082830 CN 200610082830 CN 200610082830 A CN200610082830 A CN 200610082830A CN 100511614 C CN100511614 C CN 100511614C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
This invention relates to a package structure for multiple stacked chips including: a base plate, at least one first chip and a second chip, in which, the base plate includes a dielectric layer, a metal layer and a weld cover layer, the metal layer includes a conducting trace area and a shielding area formed on the top of the dielectric layer, the weld cover layer is formed on the conducting trace area of the metal layer, the first and second chips are connected with the trace area separately and set on the cover layer, and the package of the first chip is connected with a surface of the metal layer to set the first chip between the weld cover layer and shielding area of the metal layer, and the package body of the second chip is connected with the other surface of the metal layer to place the chip between the cover layer and the shielding area of the metal layer.
Description
Technical field
The present invention is about a kind of method for packing and encapsulating structure thereof of multi-chip stacking, particularly a kind of substrate with insulating barrier and metal level, with two chip-stacked between insulating barrier and metal level or metal level, make two chips reach the method for packing and the encapsulating structure thereof of high heat radiation and metallic shield effect.
Background technology
Along with the progress of electronics industry and the arriving of digital Age, the consumer is also increasing for the functional requirement of electronic product, therefore, how to break through the technology of semiconductor manufacturing and integrated circuit (IC) design, with the more powerful high frequency chip of manufacturing function, obviously become the important topic of present research.And for the semiconductor package part that adopts high frequency chip, tend to produce very serious electromagnetic wave problem in the operating process, this is to tend to produce very strong electromagnetic wave when carrying out computing or transmission owing to high frequency chip, and electromagnetic wave is transmitted to the external world through packing colloid, cause the electromagnetic interference (EMI) problem of electronic installation on every side, also may reduce simultaneously the electrical quality and the heat dispersion of this packaging part, form a big problem of high-frequency semiconductor packaging part.
General existing solution is: a metallic shield is covered outside the packaging part, and with metallic shield ground connection, to solve the problem of electromagnetic interference, yet metallic shield has the excessive shortcoming with the material cost costliness of weight, and connect the mode of putting and be difficult to carry out automated production, obviously do not meet development trends such as encapsulation technology lightness, low cost, high yield, become the big obstacle in the high frequency chip encapsulation.
Therefore, how to research and develop a kind of method for packing and encapsulating structure thereof of avoiding Electromagnetic Interference, can take into account simultaneously high heat radiation, package requirements such as low-cost and compact, become the problem of solution that association area presses for.
The inventor thinks that above-mentioned shortcoming can improve, and according to the correlation experience of being engaged in for many years in this respect, concentrated observational study, and cooperate theory to be used, thus propose a kind of reasonable in design and effectively improve the invention of above-mentioned shortcoming.
Summary of the invention
Technical problem to be solved by this invention, mainly be to provide a kind of Electromagnetic Interference of avoiding, and can take into account high heat radiation, low-cost and compact method for packing, make two chips reach the effect of high heat radiation and metallic shield, can also simplify the processing procedure of existing anti-electromagnetic wave interference and save the cost of making.Another technical problem that will solve of the present invention is also to provide a kind of with the two chip-stacked method for packing that promote heat radiation and raising metallic shield between metal level in addition, and the encapsulating structure of two kinds of multi-chip stackings.In order to solve the problems of the technologies described above, the invention provides a kind of method for packing of multi-chip stacking, its step comprises: at first, provide an insulating barrier (dielectric layer); Then, form a metal level (metal layer) on insulating barrier, wherein metal level comprises a conductive trace district (conducting trace area) and a shielded area (shieldingarea); Then, in the conductive trace district of metal level, form a welding cover layer (solder mask); Next, use packaging plastic on welding cover layer, to encapsulate at least one first chip and at least one second chip, form the packaging body of first chip and the packaging body of second chip, and make chip and conductive trace district realize being electrically connected; At last, bending insulating barrier and metal level make the surface, shielded area of metal level be connected with the packaging body of first chip and the packaging body of second chip respectively with surface of insulating layer.
In order to solve the problems of the technologies described above, the invention provides a kind of method for packing of multi-chip stacking, its step comprises: at first, provide an insulating barrier (dielectric layer); Then, form a metal level (metal layer) on insulating barrier, wherein metal level comprises a conductive trace district (conducting trace area) and a shielded area (shielding area); Then, in the conductive trace district of metal level, form a welding cover layer (solder mask); Next, use packaging plastic on welding cover layer, to encapsulate at least one first chip and at least one second chip, form the packaging body of first chip and the packaging body of second chip, and make chip and conductive trace district realize being electrically connected; Then, remove the insulating barrier of below, shielded area; At last, bending insulating barrier and metal level are connected two surfaces of the shielded area of metal level respectively with the packaging body of first chip and the packaging body of second chip.
In order to solve the problems of the technologies described above, the invention provides a kind of encapsulating structure of multi-chip stacking, it comprises: a substrate, has first chip, and second chip with packaging body of packaging body.Wherein, substrate comprises an insulating barrier (dielectric layer), a metal level (metal layer) and a welding cover layer (soldermask), wherein metal level comprises a conductive trace district (conductingtrace area) and a shielded area (the shielding area) that is respectively formed at the insulating barrier upper end, and welding cover layer is formed in the conductive trace district of metal level.In addition, first chip is electrically connected with the conductive trace district, and wherein first chip is arranged on the welding cover layer, and a surface of the packaging body of first chip and metal level is connected, and makes first chip between the shielded area of welding cover layer and metal level.In addition, second chip is electrically connected with the conductive trace district, and wherein second chip is arranged on the welding cover layer, and another surface of the packaging body of second chip and metal level is connected, and makes second chip between the shielded area of welding cover layer and metal level.
In order to solve the problems of the technologies described above, the invention provides a kind of encapsulating structure of multi-chip stacking, it comprises: a substrate, has first chip, and second chip with packaging body of packaging body.Wherein, substrate comprises an insulating barrier (dielectric layer), a metal level (metal layer) and a welding cover layer (soldermask), wherein metal level comprises the conductive trace district (conducting tracearea) that is formed on the insulating barrier, and the shielded area (shielding area) that stretches out from the conductive trace district, and welding cover layer is formed in the conductive trace district of metal level.In addition, first chip is electrically connected with the conductive trace district, and wherein first chip is arranged on the welding cover layer, and a surface of the packaging body of first chip and insulating barrier is connected, and makes first chip between welding cover layer and insulating barrier.In addition, second chip is electrically connected with the conductive trace district, and wherein second chip is arranged on the welding cover layer, and the packaging body of second chip is connected with the surface of the shielded area of metal level, makes second chip between the shielded area of welding cover layer and metal level.
In sum, adopt the present invention because of using a substrate with insulating barrier and metal level, chip-stacked with two between insulating barrier and the metal level or between the metal level, this mode not only can make two chips reach high heat radiation and metallic shield effect, and can simplify the processing procedure of existing anti-electromagnetic wave interference and save the cost of making.
Reach technology, means and the effect that predetermined purpose is taked in order further to understand the present invention, see also following about detailed description of the present invention and accompanying drawing, can deeply reach purpose of the present invention, feature and the characteristics understood particularly thus, yet accompanying drawing is only for reference and explanation, is not in order to restriction the present invention.
Description of drawings
The flow chart of first embodiment of the method for packing that Fig. 1 piles up for base band of the present invention and radio frequency chip;
The insulating barrier of first embodiment of the encapsulating structure that Fig. 2 piles up for base band of the present invention and radio frequency chip bends preceding generalized section with metal level;
Generalized section after the insulating barrier of first embodiment of the encapsulating structure that Fig. 3 piles up for base band of the present invention and radio frequency chip and metal level bend;
Fig. 4 for metal level of the present invention be formed on behind the insulating barrier on look schematic diagram;
The flow chart of second embodiment of the method for packing that Fig. 5 piles up for base band of the present invention and radio frequency chip;
The insulating barrier of second embodiment of the encapsulating structure that Fig. 6 piles up for base band of the present invention and radio frequency chip bends preceding generalized section with metal level;
Generalized section after the insulating barrier of second embodiment of the encapsulating structure that Fig. 7 piles up for base band of the present invention and radio frequency chip and metal level bend.
Wherein, description of reference numerals is as follows:
1 insulating barrier
2 metal levels
3 welding cover layers
4 first chips
5 second chips
6 solderings
10 through holes
20 conductive trace districts
21 shielded areas
40 packaging bodies
50 packaging bodies
200 weld pads
201 conductive traces
Embodiment
Please refer to Fig. 1 to Fig. 4, be respectively the generalized section after generalized section before flow chart, insulating barrier and the metal level bending of first embodiment of the method for packing that base band of the present invention and radio frequency chip pile up and insulating barrier bend with metal level.By the flow chart of Fig. 1 in conjunction with Fig. 2 and Fig. 3 as can be known, the invention provides a kind of method for packing of multi-chip stacking, its step comprises: at first, provide an insulating barrier (dielectric layer) 1 (S100); Then, form a metal level (metal layer) 2 on insulating barrier 1, wherein metal level 2 comprises (conducting trace area) 20 and one shielded area, a conductive trace district (shielding area) 21 (S102); Then, in the conductive trace district 20 of metal level 2, form a welding cover layer (solder mask) 3 (S104).
Next, on welding cover layer 3, use packaging plastic (figure does not show) at least one first chip 4 of encapsulation and at least one second chip 5, form the packaging body 40 of first chip 4 and the packaging body 50 of second chip 5, and make chip 4,5 realize being electrically connected (S106) with conductive trace district 20.Wherein, first chip 4 can be a baseband chip (base band chip), and second chip 5 can be a radio frequency chip (RF chip); Perhaps, first chip 4 can be a radio frequency chip (RF chip), and second chip 5 can be a baseband chip (baseband chip).In addition, the mode that encapsulates first chip 4 or second chip 5 includes: wire-bonded (wirebonding), upside-down mounting (Flip chip) or square flat non-pin encapsulation (Quad flat non-leadedpackage, QFN), make chip 4,5 realize being electrically connected with conductive trace district 20.
At last, bending insulating barrier 1 and metal level 2 make 21 surfaces, shielded area of metal level 2 be connected (S108) with the packaging body 40 of first chip 4 and the packaging body 50 of second chip 5 respectively with the surface of insulating barrier 1.Wherein, insulating barrier 1 is realized being connected effect with the packaging body 40 of first chip 4 and the packaging body 50 of second chip 5 respectively by adhesive (figure does not show) with shielding layer 2, and this adhesive can be electroconductive binder (conductive adhesive) or any bonding colloid of electricity that produces gets final product.
Please refer to Fig. 2 and Fig. 3, and cooperate shown in Figure 4ly, the invention provides a kind of encapsulating structure of multi-chip stacking, it comprises: a substrate, has first chip 4, and second chip 5 with packaging body of packaging body.
In addition, substrate comprises an insulating barrier 1, a metal level 2 and a welding cover layer 3.Wherein, insulating barrier 1 can be a flexibility (flexible) PI substrate (polyimide substrate), and is formed with plurality of through holes (via hole) 10 on the insulating barrier 1, is formed with corresponding soldering 6 in the through hole 10.In addition, metal level 2 comprises a conductive trace district 20 and a shielded area 21 that is respectively formed at insulating barrier 1 upper end, and metal level 2 further comprises: a plurality of weld pads 200 that are formed on conductive trace district 20 and a plurality of conductive trace 201 that is electrically connected with soldering 6 with corresponding weld pad 200 respectively.In addition, welding cover layer 3 is formed in the conductive trace district 20 of metal level 2, and above-mentioned PI substrate can be individual layer or bilayer to select conductive trace district 20 according to the electric requirement in when wiring.
In addition, be electrically connected with soldering 6, make first chip 4 realize being electrically connected with conductive trace district 20 by weld pad 200 and conductive trace 201, the first chips 4.Wherein, first chip 4 is arranged on the welding cover layer 3, and a surface of the packaging body 40 of first chip 4 and insulating barrier 1 is connected, and makes first chip 4 between welding cover layer 3 and insulating barrier 1.
In addition, be electrically connected with soldering 6, make second chip 5 realize being electrically connected with conductive trace district 20 by weld pad 200 and conductive trace 201, the second chips 5.Wherein, second chip 5 is arranged on the welding cover layer 3, and the packaging body 50 of second chip 5 is connected with the surface of the shielded area 21 of metal level 2, makes second chip 5 between the shielded area 21 of welding cover layer 3 and metal level 2.
Please refer to Fig. 5 to Fig. 7, be respectively generalized section before flow chart, insulating barrier and the metal level bending of second embodiment of the method for packing that base band of the present invention and radio frequency chip pile up, and the generalized section of insulating barrier after bending with metal level.By the flow chart of Fig. 5 in conjunction with Fig. 6 and Fig. 7 as can be known, the invention provides a kind of method for packing of multi-chip stacking, its step comprises: at first, provide an insulating barrier 1 (S200); Then, form a metal level 2 on insulating barrier 1, wherein metal level 2 comprises a conductive trace district 20 and a shielded area 21 (S202); Then, in the conductive trace district 20 of metal level 2, form a welding cover layer 3 (S204).
Then, on welding cover layer 3, use packaging plastic (figure does not show) at least one first chip 4 of encapsulation and at least one second chip 5, with the packaging body 40 that forms first chip 4 and the packaging body 50 of second chip 5, and make chip 4,5 realize being electrically connected (S206) with this conductive trace district 20; Then, remove the insulating barrier 1 (S208) of 21 belows, shielded area; At last, bending insulating barrier 1 and metal level 2 make two surfaces of the shielded area 21 of metal level 1 be connected (S210) with the packaging body 40 of first chip 4 and the packaging body 50 of this second chip 5 respectively.
Please refer to Fig. 6 and Fig. 7, the second embodiment of the present invention is with first the different of embodiment maximum: the shielded area 21 of the metal level 2 of second embodiment stretches out from conductive trace district 20.That is to say that the insulating barrier 1 of second embodiment is not formed at the shielded area 21 of metal level 2.Therefore, the packaging body 40 of first chip 4 is connected with a surface of metal level 2, makes first chip 4 between the shielded area 21 of welding cover layer 3 and metal level 2; And the packaging body 50 of second chip 5 is connected with another surface of metal level 2, makes second chip 5 between the shielded area 21 of welding cover layer 3 and metal level 2.That is to say that the shielded area 21 of metal level 2 is arranged between the packaging body 50 of the packaging body 40 of first chip 4 and second chip 5, make two chips 4,5 can reach the effect of high heat radiation and metallic shield (avoiding 4, the 5 phase mutual interference of two chips).
In sum, the present invention uses a substrate with insulating barrier 1 and metal level 2, two chips 4,5 are stacked between insulating barrier 1 and the metal level 2 between (as described in first embodiment) or the metal level 2 (as described in second embodiment), this mode not only can make two chips 4,5 reach high heat radiation and metallic shield effect, and can simplify the processing procedure of existing anti-electromagnetic wave interference and save the cost of making.
The above only is the detailed description of the preferable specific embodiment of the present invention and graphic; feature of the present invention is not limited thereto; be not in order to restriction the present invention; protection scope of the present invention should be as the criterion with following claim; all spirit according to claim of the present invention reaches and the similar embodiment of its variation; all should be contained among the category of the present invention, anyly be familiar with this skill person in the present invention's field, the variation that can expect easily or modification are all claim of the present invention and contain.
Claims (10)
1, a kind of method for packing of multi-chip stacking is characterized in that, this method comprises:
One insulating barrier is provided;
Form a metal level on this insulating barrier, wherein this metal level comprises a conductive trace district and a shielded area;
In this conductive trace district of this metal level, form a welding cover layer;
On this welding cover layer, use a packaging plastic encapsulating at least one first chip and at least one second chip,, and this first chip and second chip are electrically connected with this conductive trace district realization with the packaging body that forms one first chip and the packaging body of one second chip; And
Bend this insulating barrier and this metal level, this surface, shielded area of this metal level is connected with the packaging body of this second chip, and this surface of insulating layer is connected with the packaging body of this first chip.
2, the method for packing of multi-chip stacking as claimed in claim 1 is characterized in that, is formed with plurality of through holes on the described insulating barrier, and is formed with corresponding soldering in this through hole.
3, the method for packing of multi-chip stacking as claimed in claim 2 is characterized in that, described metal level comprises: a plurality of weld pads that are formed on this conductive trace district, and a plurality of conductive traces that are electrically connected on respectively between corresponding this weld pad and this soldering; This first chip and this second chip all by this weld pad and this conductive trace, are electrically connected with this soldering.
4, the method for packing of multi-chip stacking as claimed in claim 1 is characterized in that, described insulating barrier is connected with the packaging body of this first chip by an adhesive, and this shielding layer is connected with the packaging body of this second chip by an adhesive.
5, a kind of method for packing of multi-chip stacking is characterized in that, this method comprises:
One insulating barrier is provided;
Form a metal level on this insulating barrier, wherein this metal level comprises a conductive trace district and a shielded area;
In this conductive trace district of this metal level, form a welding cover layer;
Use packaging plastic to encapsulate at least one first chip and at least one second chip on this welding cover layer, form the packaging body of one first chip and the packaging body of one second chip, and this first chip and this second chip are electrically connected with this conductive trace district realization;
Remove this insulating barrier of this below, shielded area; And
Bend this insulating barrier and this metal level, a surface of this shielded area of this metal level is connected with the packaging body of this first chip, another surface of this shielded area of this metal level is connected with the packaging body of this second chip.
6, a kind of encapsulating structure of multi-chip stacking is characterized in that, this structure comprises:
One substrate comprises an insulating barrier, a metal level and a welding cover layer, and wherein this metal level comprises a conductive trace district and a shielded area that is respectively formed at this insulating barrier upper end, and this welding cover layer is formed in this conductive trace district of this metal level;
At least one first chip with packaging body, be electrically connected with this conductive trace district, wherein this first chip is arranged on this welding cover layer, and a surface of the packaging body of this first chip and this insulating barrier is connected, and makes this first chip between this welding cover layer and this insulating barrier; And
At least one second chip with packaging body, be electrically connected with this conductive trace district, wherein this second chip is arranged on this welding cover layer, and the packaging body of this second chip is connected with the surface of this shielded area of this metal level, makes this second chip between this shielded area of this welding cover layer and this metal level.
7, the encapsulating structure of multi-chip stacking as claimed in claim 6 is characterized in that, is formed with plurality of through holes on the described insulating barrier, and is formed with corresponding soldering in this through hole.
8, the encapsulating structure of multi-chip stacking as claimed in claim 7 is characterized in that, described metal level comprises: a plurality of weld pads that are formed at this conductive trace district, and a plurality of conductive traces that are electrically connected on respectively between corresponding this weld pad and this soldering; Therefore, this first chip and this second chip all by this weld pad and this conductive trace, are electrically connected with this soldering.
9, the encapsulating structure of multi-chip stacking as claimed in claim 6 is characterized in that, described insulating barrier is connected with the packaging body of this first chip by an adhesive, and this shielding layer is connected with the packaging body of this second chip by an adhesive.
10, a kind of encapsulating structure of multi-chip stacking, it comprises:
One substrate, comprise an insulating barrier, a metal level and a welding cover layer, wherein this metal level comprises the conductive trace district that is formed on this insulating barrier, and the shielded area that stretches out from this conductive trace district, and this welding cover layer is formed in this conductive trace district of this metal level;
At least one first chip with packaging body, be electrically connected with this conductive trace district, wherein this first chip is arranged on this welding cover layer, and a surface of the packaging body of this first chip and this metal level is connected, and makes this first chip between this shielded area of this welding cover layer and this metal level; And
At least one second chip with packaging body, be electrically connected with this conductive trace district, wherein this second chip is arranged on this welding cover layer, and another surperficial connection of the packaging body of this second chip and this metal level, makes this second chip between this shielded area of this welding cover layer and this metal level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610082830 CN100511614C (en) | 2006-06-13 | 2006-06-13 | Package method for multi-chip stack and package structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200610082830 CN100511614C (en) | 2006-06-13 | 2006-06-13 | Package method for multi-chip stack and package structure thereof |
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| CN101090080A CN101090080A (en) | 2007-12-19 |
| CN100511614C true CN100511614C (en) | 2009-07-08 |
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| CN 200610082830 Active CN100511614C (en) | 2006-06-13 | 2006-06-13 | Package method for multi-chip stack and package structure thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103107164A (en) * | 2013-01-16 | 2013-05-15 | 天津大学 | Radio frequency packaging structure |
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| CN102202827A (en) * | 2010-07-20 | 2011-09-28 | 联发软件设计(深圳)有限公司 | A tin pre-coating method used for a multicolumn quad flat no-lead chip and a rework method |
| CN103094256B (en) * | 2011-11-08 | 2015-12-02 | 华进半导体封装先导技术研发中心有限公司 | A kind of package system |
| CN103311161A (en) * | 2013-06-17 | 2013-09-18 | 华进半导体封装先导技术研发中心有限公司 | Modified flexible substrate packaging device |
| CN103560125B (en) * | 2013-11-05 | 2016-09-21 | 华进半导体封装先导技术研发中心有限公司 | Three-dimension flexible substrate electromagnetic shielding encapsulating structure and manufacture method |
| CN105552501A (en) * | 2016-02-17 | 2016-05-04 | 北京艾达方武器装备技术研究所 | Electromagnetic wave interconnection device and method and application thereof |
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| US10733136B1 (en) * | 2019-03-01 | 2020-08-04 | Western Digital Technologies, Inc. | Vertical surface mount type C USB connector |
| CN111863716B (en) * | 2020-07-28 | 2024-04-12 | 南通通富微电子有限公司 | Chip interconnection method |
| CN114823555B (en) * | 2022-03-04 | 2022-12-13 | 珠海越亚半导体股份有限公司 | Packaging structure and manufacturing method thereof |
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2006
- 2006-06-13 CN CN 200610082830 patent/CN100511614C/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103107164A (en) * | 2013-01-16 | 2013-05-15 | 天津大学 | Radio frequency packaging structure |
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| CN101090080A (en) | 2007-12-19 |
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