CN107622981B - Electronic package and manufacturing method thereof - Google Patents

Electronic package and manufacturing method thereof Download PDF

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Publication number
CN107622981B
CN107622981B CN201610619453.1A CN201610619453A CN107622981B CN 107622981 B CN107622981 B CN 107622981B CN 201610619453 A CN201610619453 A CN 201610619453A CN 107622981 B CN107622981 B CN 107622981B
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China
Prior art keywords
layer
conductive
substrate
top surface
antenna structure
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CN201610619453.1A
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Chinese (zh)
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CN107622981A (en
Inventor
陈彦亨
江政嘉
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Publication of CN107622981A publication Critical patent/CN107622981A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

An electronic package and a method for fabricating the same, the electronic package comprising: the antenna structure is provided with a concave part, so that the surface area of the antenna structure is increased, and the antenna gain can be increased.

Description

Electronic package and manufacturing method thereof
Technical Field
The present invention relates to an electronic package, and more particularly, to an electronic package with an antenna structure and a method for fabricating the same.
Background
With the rapid development of the electronic industry, electronic products are also gradually moving toward multi-function and high-performance. Currently, wireless communication technology is widely applied to various consumer electronic products to receive or transmit various wireless signals. In order to meet the design requirements of consumer electronics, the manufacture and design of wireless communication modules are being developed to be light, thin, short and small, wherein a planar Antenna (Patch Antenna) has the characteristics of small volume, light weight and easy manufacture, and is widely used in wireless communication modules of electronic products such as mobile phones (cell phones), Personal Digital Assistants (PDAs) and the like.
As shown in fig. 1, a conventional semiconductor package 1 having an antenna includes: a substrate 10, a plurality of semiconductor devices 11, an encapsulant 12, at least one conductive pillar 13, and an antenna layer 14. The semiconductor devices 11 and the conductive pillars 13 are disposed on the substrate 10 and electrically connected to the substrate 10. The encapsulant 12 is formed on the substrate 10 to encapsulate the semiconductor devices 11 and the conductive pillars 13. The antenna layer 14 is disposed on the encapsulant 12 and electrically connected to the conductive posts 13.
In the semiconductor package 1, due to the trend of miniaturization of the product, the surface area of the antenna layer 14 is limited by the area reduction of the semiconductor package 1, and the effective area of the antenna layer 14 is reduced accordingly, thereby affecting the antenna gain.
Therefore, how to overcome the above problems of the prior art has become an issue to be solved.
Disclosure of Invention
To overcome the drawbacks of the prior art, the present invention provides an electronic package and a method for fabricating the same, which can increase the surface area of the antenna structure and thus increase the antenna gain.
The electronic package of the present invention includes: a substrate; an electronic element disposed on the substrate; a conductive column vertically arranged on the substrate; a packaging layer formed on the substrate to encapsulate the electronic element and the conductive pillar; and an antenna structure disposed on the packaging layer and having at least one recess.
The invention also provides a manufacturing method of the electronic packaging piece, which comprises the following steps: providing a substrate on which an electronic component is disposed; forming a conductive post and a packaging layer on the substrate, and enabling the packaging layer to wrap the conductive post and the electronic element; and disposing an antenna structure on the packaging layer, wherein the antenna structure has at least one recess.
In the electronic package and the manufacturing method thereof, the electronic element is electrically connected to the substrate.
In the electronic package and the manufacturing method thereof, the conductive pillar is electrically connected to the substrate.
In the electronic package and the method for fabricating the same, the conductive pillar is exposed out of the package layer. For example, the conductive posts are exposed on the surface of the encapsulation layer and flush with the surface of the encapsulation layer.
In the electronic package and the manufacturing method thereof, the antenna structure is electrically connected to the conductive pillar.
As can be seen from the above, the electronic package and the manufacturing method thereof according to the present invention increase the surface area of the antenna structure by designing the antenna structure with the concave portion, so that the electronic package according to the present invention can increase the antenna gain by increasing the surface area of the antenna structure compared to the antenna layer in the prior art.
Drawings
FIG. 1 is a cross-sectional view of a conventional semiconductor package; and
fig. 2A to 2D are schematic cross-sectional views illustrating a method for fabricating an electronic package according to the present invention; fig. 2B 'and 2B ″ are schematic views of other different embodiments of fig. 2B, and fig. 2D' is a schematic view of another embodiment of fig. 2D.
Description of the symbols:
1 semiconductor package
10,20, 20' substrate
11 semiconductor element
12 packaging colloid
13,23 conductive column
14 antenna layer
2, 2' electronic package
20a upper surface
20b lower surface
200, 200' electrical contact pad
201 line layer
21a,21b,21c electronic component
210 solder ball
210' bonding wire
22 encapsulation layer
22a top surface
22b bottom surface
220 through hole
23a exposed surface
24 antenna structure
24a conductive layer
240 concave part
25 bonding layer
26 solder balls.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the contents disclosed in the specification, and are not used for limiting the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, ratio relationship changes or size adjustments should still fall within the scope of the technical contents disclosed in the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "above", "a" and "below" used in the present specification are for clarity of description only, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as the scope of the present invention.
Please refer to fig. 2A to 2D, which are schematic cross-sectional views illustrating a method for fabricating an electronic package 2 according to the present invention.
As shown in fig. 2A, a substrate 20 having an upper surface 20a and a lower surface 20b is provided for mounting a plurality of electronic components 21a,21b,21c on the upper surface 20a of the substrate 20.
The substrate 20 has a circuit layer on its upper surface 20a, which includes a plurality of electrical contact pads 200, 200', 200 ".
In the present embodiment, the substrate 20 is not particularly limited, but may be of various types. For example, the circuit layer of the substrate 20 has at least one internal circuit (not shown), and the internal circuit can selectively and electrically connect each of the electrical contact pads 200, 200', 200 "; alternatively, the substrate 20 ' shown in fig. 2D ' is a core-less type, in which the wiring layer 201 including the plurality of electrical contact pads 200,200 ', 200 "is a fan-out (fan-out) structure, and a plurality of conductive elements such as solder balls 26 may be bonded to the bottom side.
The electronic components 21a,21b,21c are active components (such as the electronic components 21a,21b), passive components (such as the electronic component 21c), or a combination thereof, wherein the active components are, for example, semiconductor chips, and the passive components are, for example, resistors, capacitors, and inductors.
In the present embodiment, the electronic component 21a is a flip chip, that is, the electronic component is electrically connected to a portion of the electrical contact pads 200 on the upper surface 20a of the substrate 20 correspondingly through a plurality of solder balls 210; alternatively, the electronic component 21b is a wire-bonding chip, i.e. a plurality of bonding wires 210 'are correspondingly electrically connected to a portion of the electrical contact pads 200' on the upper surface 20a of the substrate 20.
As shown in fig. 2B, an encapsulation layer 22 and at least one conductive pillar 23 are formed on the upper surface 20a of the substrate 20.
The encapsulation layer 22 encapsulates the electronic components 21a,21b,21c and the conductive pillar 23, and the electronic components 21a,21b,21c are not exposed from the encapsulation layer 22.
The conductive pillar 23 is a copper pillar, which is erected on the electrical contact pad 200 ″ and electrically connected to the electrical contact pad 200 ″.
In the present embodiment, the encapsulation layer 22 has a top surface 22a and a bottom surface 22b opposite to the top surface 22a and bonded to the upper surface 20a of the substrate 20, wherein the conductive pillar 23 is exposed from the top surface 22a of the encapsulation layer 22. Specifically, the exposed surfaces 23a of the conductive posts 23 are flush with the top surface 22a of the encapsulation layer 22.
Furthermore, the manufacturing methods of the encapsulation layer 22 and the conductive pillars 23 are not particularly limited. For example, as shown in fig. 2B', the package layer 22 is formed first, at least one through hole 220 is formed on the package layer 22, and then a conductive material (e.g., copper material or conductive adhesive) is filled into the through hole 220 to form the conductive pillar 23. Alternatively, as shown in fig. 2B ″, the conductive pillars 23 are formed first, and then the package layer 22 is formed.
As shown in fig. 2C, a conductive layer 24a is formed on the exposed surface 23a of the conductive pillar 23 and the top surface 22a of the package layer 22.
The conductive layer 24a is made of copper (Cu), nickel (Ni), iron (Fe), aluminum (Al), stainless steel (Sus), or the like.
In the present embodiment, the conductive layer 24a is formed by electroplating, electroless plating, or physical vapor deposition (sputtering), for example.
As shown in fig. 2D, a plurality of concave portions 240 are formed on the conductive layer 24a, so that the conductive layer 24a and the concave portions 240 form an antenna structure 24, and the antenna structure 24 is electrically connected to the conductive pillar 23.
In other embodiments, as shown in fig. 2D', a bonding layer 25 may be further formed between the package layer 22 and the antenna structure 24 to increase the bonding between the antenna structure 24 and the package layer 22. Specifically, the bonding layer 25 is made of a dielectric material such as Polyoxadiazole (PBO), Polyimide (PI), or Prepreg (PP).
It should be understood that the antenna structure 24 with the recess 240 may also be fabricated and then bonded to the package layer 22.
The electronic package 2, 2' of the present invention increases the surface area of the antenna structure 24 by designing the antenna structure 24 with the patterned recess 240, so that the electronic package 2 of the present invention can increase the antenna gain by increasing the surface area of the antenna structure 24 compared to the antenna layer of the prior art.
The present invention further provides an electronic package 2, 2' including a substrate 20, a plurality of electronic components 21a,21b,21c, at least one conductive pillar 23, a package layer 22, and an antenna structure 24.
The substrate 20 has a plurality of electrical contact pads 200, 200', 200 ".
The electronic components 21a,21b,21c are disposed on the substrate 20 and electrically connected to portions of the electrical contact pads 200, 200'.
The conductive pillars 23 are erected on the substrate 20 and electrically connected to a portion of the electrical contact pads 200 ".
The encapsulation layer 22 is disposed on the substrate 20 to encapsulate the electronic components 21a,21b,21c and the conductive pillar 23. In one embodiment, the conductive pillars 23 are exposed from the package layer 22.
The antenna structure 24 is formed on the package layer 22 and electrically connected to the conductive pillar 23, and the antenna structure 24 has a plurality of recesses 240.
In one embodiment, the electronic package 2' further includes a bonding layer 25 formed between the package layer 22 and the antenna structure 24.
In summary, the electronic package and the manufacturing method thereof of the invention increase the surface area of the antenna structure mainly by the design of the concave portion, so as to increase the antenna gain.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims (12)

1. An electronic package, characterized in that the electronic package comprises:
a substrate;
an electronic element disposed on the substrate;
a conductive column vertically arranged on the substrate;
the packaging layer is provided with a flat top surface and a bottom surface which is opposite to the top surface and is combined to the substrate so as to coat the electronic element and the conductive column;
the antenna structure is provided with a conductive layer arranged above the top surface of the packaging layer, and at least one concave part is formed on the conductive layer so that the conductive layer is provided with at least one concave part; and
and the bonding layer is formed between the top surface of the packaging layer and the antenna structure.
2. The electronic package according to claim 1, wherein the electronic component is electrically connected to the substrate.
3. The electronic package according to claim 1, wherein the conductive post is electrically connected to the substrate.
4. The electronic package according to claim 1, wherein the conductive pillar is exposed at a top surface of the encapsulation layer.
5. The electronic package according to claim 1, wherein the surface of the conductive pillar exposed from the bonding layer is flush with the top surface of the bonding layer.
6. The electronic package according to claim 1, wherein the antenna structure is electrically connected to the conductive post.
7. A method of fabricating an electronic package, the method comprising:
providing a substrate on which an electronic component is disposed;
forming a conductive post and a packaging layer on the substrate, and enabling the packaging layer to wrap the conductive post and the electronic element, wherein the packaging layer is provided with a flat top surface and a bottom surface which is opposite to the top surface and is combined to the substrate; and
the antenna structure is arranged above the top surface of the packaging layer, and a combination layer is formed between the top surface of the packaging layer and the antenna structure, wherein the antenna structure is provided with a conductive layer arranged above the top surface of the packaging layer, and at least one concave part is formed on the conductive layer, so that the conductive layer is provided with at least one concave part.
8. The method of claim 7, wherein the electronic component is electrically connected to the substrate.
9. The method of claim 7, wherein the conductive posts are electrically connected to the substrate.
10. The method of claim 7, wherein the conductive posts are exposed at a top surface of the encapsulation layer.
11. The method of claim 7, wherein the conductive posts are exposed at a surface of the bonding layer flush with a top surface of the bonding layer.
12. The method of claim 7, wherein the antenna structure is electrically connected to the conductive post.
CN201610619453.1A 2016-07-13 2016-08-01 Electronic package and manufacturing method thereof Active CN107622981B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW105122019A TWI620278B (en) 2016-07-13 2016-07-13 Electronic package and the manufacture thereof
TW105122019 2016-07-13

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CN107622981A CN107622981A (en) 2018-01-23
CN107622981B true CN107622981B (en) 2020-05-05

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Publication number Priority date Publication date Assignee Title
TW201947727A (en) * 2018-05-09 2019-12-16 矽品精密工業股份有限公司 Electronic package and method for manufacture the same
CN111642060B (en) * 2020-05-28 2022-11-22 青岛歌尔微电子研究院有限公司 Communication module and manufacturing method thereof

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CN102324416A (en) * 2010-09-16 2012-01-18 日月光半导体制造股份有限公司 Integrate the semiconductor package part of screened film and antenna

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TWI478439B (en) * 2012-06-18 2015-03-21 Univ Nat Sun Yat Sen A system in package with an antenna
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CN101111938A (en) * 2005-01-28 2008-01-23 株式会社半导体能源研究所 Semiconductor device and method of fabricating the same
CN102324416A (en) * 2010-09-16 2012-01-18 日月光半导体制造股份有限公司 Integrate the semiconductor package part of screened film and antenna

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CN107622981A (en) 2018-01-23
TWI620278B (en) 2018-04-01

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