CN110364490A - A kind of chip-packaging structure and its packaging method - Google Patents
A kind of chip-packaging structure and its packaging method Download PDFInfo
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- CN110364490A CN110364490A CN201810322554.1A CN201810322554A CN110364490A CN 110364490 A CN110364490 A CN 110364490A CN 201810322554 A CN201810322554 A CN 201810322554A CN 110364490 A CN110364490 A CN 110364490A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
This application discloses a kind of chip-packaging structure and packaging methods, the encapsulating structure includes the chip groove body for accommodating microwave radio chip, the groove body includes a metal substrate, core plate of the metal substrate as the first chip slot substrate and the second chip slot substrate, so, the metal substrate can be directly as the heat sink of microwave radio chip, because metal substrate has good heating conduction, therefore, metal substrate can provide good heat dissipation channel for microwave radio chip, improve the heat dissipation performance of encapsulating structure.And, in the encapsulating structure, full package structure to microwave radio chip is formd by the way that the intracorporal metal layer of chip slot is arranged in and is set to laminating media layer of the chip slot substrate on the surface of the metal substrate, so, the good Magnetic Shielding Effectiveness of microwave radio chip is realized, to improve the electromagnetic shielding performance of encapsulating structure.In addition, very high integrated level may be implemented in the encapsulating structure.
Description
Technical field
This application involves technical field of semiconductor encapsulation more particularly to a kind of chip-packaging structure and packaging methods.
Background technique
Microwave radio chip is the core technology of field of wireless communication, be international chip design field generally acknowledge be most difficult to design
Integrated circuit kind.In all mobile phones, approximately half of chip cost derives from microwave radio chip.
Currently, the encapsulating structure of common microwave radio chip is mostly single die package, then pass through surface mount
Technology (Surface Mounted Technology, SMT) realizes modular functionality on a printed-wiring board, electromagnetic shielding
Function is also to be realized by way of affixed metal shielding case in SMT process.This encapsulating structure be all carried out by substrate it is scattered
Heat, however the heating conduction of existing substrate is poor, so as to cause the heat dissipation performance of the single die package of microwave radio chip
It is poor.Moreover, the magnetic screen mode of the encapsulating structure is unfavorable for integrating other radio-frequency modules in chip-packaging structure, integrate
Spend lower, along with the development of electronic product, it is small-sized that this encapsulating structure is not able to satisfy electronic product especially mobile terminal product
The demand for development of change.
Summary of the invention
In view of this, this application provides a kind of chip-packaging structure and its packaging method, to improve dissipating for encapsulating structure
Hot property and integrated level.
In order to solve the above-mentioned technical problem, the application adopts the technical scheme that
A kind of chip-packaging structure, comprising:
Chip groove body, the chip groove body include metal substrate and be sequentially located on metal substrate first surface first
Adhesive layer and the first chip slot substrate；It is provided on the first chip slot substrate and matched first chip of the first chip size
Slot；It is provided on first adhesive layer and matched first notching construction of the first chip slot size；
The first metal layer being set on first chip slot and the first notching construction inner surface；
The first chip being set on the first metal layer；It is electrically connected between first chip and the metal substrate
It connects；
And it is set to first lamination dielectric layer of the first chip slot substrate on the surface of the metal substrate,
The first lamination dielectric layer is for coating first chip.
Optionally, the laminated stack chip groove body further include:
The second adhesive layer and the second chip slot substrate being sequentially located on metal substrate second surface；Wherein, the metal
Substrate first surface is opposite with the metal substrate second surface；It is provided on second adhesive layer and the second chip slot size
Matched second notching construction is provided with and matched second chip slot of the second chip size on the second chip slot substrate；
The encapsulating structure further include:
The second metal layer being set on second chip slot and the second notching construction inner surface；
The second chip being set in the second metal layer；It is electrically connected between second chip and the metal substrate
It connects；
And it is set to second lamination dielectric layer of the second chip slot substrate on the surface of the metal substrate,
The second lamination dielectric layer is for coating second chip.
Optionally, the encapsulating structure further include: through the first lamination dielectric layer, chip groove body and the second lamination
The through-hole interconnection of dielectric layer upper and lower surface, the through-hole interconnection are located at the outer of first chip slot and second chip slot
It encloses, metal interconnecting wires is filled in the through-hole interconnection.
Optionally, the metal interconnecting wires are co-axial interconnection lines.
Optionally, the encapsulating structure further include:
The first line layer being set on the first lamination dielectric layer, and be set on the second lamination dielectric layer
The second line layer；The through-hole interconnection is electrically connected with the first line layer and second line layer.
Optionally, the encapsulating structure further include:
The first solder mask being formed on the first line layer, and the second resistance being formed on second line layer
Windowing is provided with according to electrical connection demand at different locations on layer, first solder mask and second solder mask.
Optionally, the encapsulating structure further include:
The third chip at the first solder mask windowing position, the third chip and institute are set to by face-down bonding mode
State the electrical connection of the first chip.
Optionally, the encapsulating structure further include: the electric connection structure being set at the second solder mask windowing position, it is described
Electric connection structure is isolated between different electric connection structures by second solder mask for being electrically connected with external circuit.
A kind of chip packaging method, comprising:
Chip groove body is formed by lamination process for pressing, the microwave radio groove body is including at least metal substrate and successively
The first adhesive layer and the first chip slot substrate on metal substrate first surface；It is provided on the first chip slot substrate
With matched first chip slot of the first chip size；It is provided on first adhesive layer and the first chip slot size matched
One notching construction,
The first metal layer is formed on first chip slot and the first notching construction inner surface；
The first chip is formed on the first metal layer, is electrically connected between first chip and the metal substrate；
It is formed on surface of the first chip slot substrate away from the metal substrate for coating first chip
First lamination dielectric layer.
Optionally, the microwave radio groove body further include: the second adhesive layer being sequentially located on metal substrate second surface
With the second chip slot substrate；Wherein, the metal substrate first surface is opposite with the metal substrate second surface；Described second
Be formed on adhesive layer with matched second notching construction of the second chip slot size, be formed on the second chip slot substrate with
Matched second chip slot of second chip size；
It is described to be formed after chip groove body by lamination process for pressing, further includes:
Second metal layer is formed on second chip slot and the second notching construction inner surface；
The second chip is formed in the second metal layer, is electrically connected between second chip and the metal substrate；
It is formed on surface of the second chip slot substrate away from the metal substrate for coating second chip
Second lamination dielectric layer.
Compared to the prior art, the application has the advantages that
Based on above technical scheme it is found that in chip-packaging structure provided by the embodiments of the present application, metal substrate is as
The core plate of one chip slot substrate and the second chip slot substrate, therefore, metal substrate can dissipating directly as the first, second chip
Hot plate, because metal substrate has good heating conduction, therefore, metal substrate can provide good for the first, second chip
Heat dissipation channel improves the heat dissipation performance of encapsulating structure.Moreover, in the encapsulating structure, by being arranged in the intracorporal gold of chip slot
Belong to layer and be set to laminating media layer of the chip slot substrate on the surface of the metal substrate and forms to first, second
The full package structure of chip realizes the good Magnetic Shielding Effectiveness of the first, second chip, to improve the electromagnetism of encapsulating structure
Shielding properties.It, therefore, can be in the encapsulating structure because the encapsulating structure realizes good Magnetic Shielding Effectiveness to one single chip
Other radio-frequency modules are integrated, therefore, which may be implemented very high integrated level, is conducive to meet electronic product and especially move
The demand for development of dynamic end product miniaturization.
Detailed description of the invention
In order to which the specific embodiment of the application is expressly understood, used when the application specific embodiment is described below
Attached drawing do a brief description.It should be evident that these attached drawings are only the section Examples of the application.
Fig. 1 is chip-packaging structure schematic diagram provided by the embodiments of the present application；
Fig. 2 is chip packaging method flow diagram provided by the embodiments of the present application；
Fig. 3 A to Fig. 3 K is the corresponding structural representation of processing procedures a series of in chip packaging method provided by the embodiments of the present application
Figure.
Description of symbols:
101: metal substrate, 1011: plug socket resin,
102: the first adhesive layers, 1021: the first notching constructions,
103: the first chip slot substrates, 1031: the first chip slots,
104: the first metal layer,
105: the first chips,
106: the first lamination dielectric layers,
107: the second adhesive layers, 1071: the second notching constructions,
108: the second chip slot substrates, 1081: the second chip slots,
109: second metal layer,
110: the second chips,
111: the second lamination dielectric layers,
112: through-hole interconnection,
113: metal interconnecting wires,
114: first line layer,
115: the second line layers,
116: the first solder masks,
117: the second solder masks,
118: third chip,
119: bottom filler,
120: metal soldered ball.
Specific embodiment
As described in the background section, there are heat dissipation performance difference and integrated levels for the encapsulating structure of common microwave radio chip
Low problem, in order to overcome the technical problem, the embodiment of the present application provides a kind of chip-packaging structure, in the encapsulating structure
Including the chip groove body for accommodating microwave radio chip, which includes a metal substrate, and the metal substrate is as the first core
The core plate of film trap substrate and the second chip slot substrate, in this way, the metal substrate can be directly as the heat dissipation of microwave radio chip
Plate, because metal substrate has good heating conduction, therefore, metal substrate can provide good heat dissipation for microwave radio chip
The heat dissipation performance of encapsulating structure is improved in channel.Moreover, in the encapsulating structure, by being arranged in the intracorporal metal layer of chip slot
And it is set to laminating media layer of the chip slot substrate on the surface of the metal substrate and forms to microwave radio chip
Full package structure realize the good magnetic screen effect of microwave radio chip in this way, microwave radio chip is embedded in groove body
Fruit, to improve the electromagnetic shielding performance of encapsulating structure.Further, real to single microwave radio chip because of the encapsulating structure
Show good Magnetic Shielding Effectiveness, therefore, can integrate other radio-frequency modules in the encapsulating structure, therefore, the encapsulating structure
Very high integrated level may be implemented, be conducive to the demand for development for meeting electronic product especially mobile terminal product miniaturization.
The specific embodiment of chip-packaging structure provided by the embodiments of the present application is retouched in detail with reference to the accompanying drawing
It states.
Referring to Figure 1, the encapsulating structure of microwave radio chip provided by the embodiments of the present application includes:
Chip groove body, the chip groove body include metal substrate 101 and are sequentially located on 101 first surface of metal substrate
First adhesive layer 102 and the first chip slot substrate 103；It is provided with and the first chip size on the first chip slot substrate 103
The first chip slot 1031 matched；It is provided on first adhesive layer 102 and matched first notching construction of the first chip slot size
1021,
The first metal layer 104 being set on 1021 inner surface of first chip slot 1031 and the first notching construction；
The first chip 105 being set on the first metal layer 104；Between first chip 105 and the metal substrate 101
Electrical connection；
And it is set to first laminating media of the first chip slot substrate 103 on the surface of the metal substrate 101
Layer 106, the first lamination dielectric layer 106 is for coating first chip 105.
It is to be appreciated that in the embodiment of the present application, the size of the first chip slot 1031 and the first notching construction 1021 can be with
Greater than the size of the first chip 105, opened in this way, the first lamination dielectric layer 106 can also be located at the first chip slot 1031 and first
In gap between slot structure 1021 and the first chip 105, to realize the package to the first chip 105.
In addition, be provided with weld pad on the first chip 105, in order to realize that the first chip 105 and extraneous signal transmit, the
Blind hole is provided on one laminating media layer 106 at position corresponding with the first chip pad, and filled with interconnection gold in the blind hole
Belong to.
It is to be appreciated that in the embodiment of the present application, in order to be conducive to improve the signal transmission performance of encapsulating structure, Metal Substrate
Filling holes with resin 1011 is also provided on plate 101.The aperture of the filling holes with resin 1011 is set as the first aperture.
In order to improve microwave radio chip encapsulating structure integrated level, realize the miniaturization of electronic product, can be in gold
Belong to the groove being also equipped on another surface of substrate 101 for accommodating microwave radio chip, in this way, one as the application can
Embodiment is selected, said chip groove body can further include: the second bonding being sequentially located on 101 second surface of metal substrate
Layer 107 and the second chip slot substrate 108；Wherein, 101 first surface of metal substrate is opposite with the metal substrate second surface；
It is provided on second adhesive layer 107 and matched second notching construction 1071 of the second chip slot size, the second chip slot base
It is provided on plate 108 and matched second chip slot 1081 of the second chip size；
Correspondingly, encapsulating structure provided by the embodiments of the present application can further include:
The second metal layer 109 being set on 1071 inner surface of second chip slot 1081 and the second notching construction；
The second chip 110 being set in the second metal layer 109；Second chip 110 and the metal substrate 101 it
Between be electrically connected；
And it is set to second laminating media of the second chip slot substrate 108 on the surface of the metal substrate 101
Layer 111, the second lamination dielectric layer 111 is for coating second chip 110.
It is to be appreciated that in the embodiment of the present application, the size of the second chip slot 1081 and the second notching construction 1071 can be with
Greater than the size of the second chip 110, opened in this way, the second lamination dielectric layer 111 can also be located at the second chip slot 1081 and second
In gap between slot structure 1071 and the second chip 110, to realize the package to the second chip 110.
In addition, be provided with weld pad on the second chip 110, in order to realize that the second chip 110 and extraneous signal transmit, the
Blind hole is provided on two laminating media layers 111 at position corresponding with the second chip pad, and filled with interconnection gold in the blind hole
Belong to.
In this embodiment, core of the metal substrate 101 as the first chip slot substrate 103 and the second chip slot substrate 108
Plate, therefore, metal substrate 101 can be directly as the heat sinks of the first, second chip 105 and 110, because metal substrate 101 has
There is good heating conduction, therefore, it is logical that metal substrate 101 can provide good heat dissipation for the first, second chip 105 and 110
Road improves the heat dissipation performance of encapsulating structure.
Moreover, because every microwave radio chip is arranged on the intracorporal metal layer of chip slot and is set to chip slot base
Backboard forms the full package structure to microwave radio chip from the laminating media layer on the surface of the metal substrate, realizes micro-
The good Magnetic Shielding Effectiveness of wave radio frequency chip.Therefore, more microwave radio chips be can integrate in the encapsulating structure, thus real
The miniaturization of existing encapsulating structure, and then adapt to the growth requirement of miniaturization of electronic products.
In addition, as another alternative embodiment of the application, above-mentioned encapsulating structure is also in order to provide the transmission performance of signal
It may further include:
Through the intercommunicated of the first lamination dielectric layer 106, chip groove body and the second lamination 111 upper and lower surface of dielectric layer
Hole 112, the through-hole interconnection 112 are located at the periphery of the first chip slot 1031 and second chip slot 1081, and the through-hole interconnection
Be filled with metal interconnecting wires 113 in 112, the metal interconnecting wires 113 for realizing the first chip 105 and the second chip 110 electricity
Connection.In order to further improve the transmission performance of signal, as an example, which can be formed in sets in advance
It sets in the filling holes with resin 1011 on metal substrate 101, under the specific example, the process for forming through-hole interconnection 112 be can wrap
It includes following steps: in 1011 internal drilling of filling holes with resin, forming the through-hole in the second aperture, the through-hole in second aperture is intercommunicated
Then metal is filled into the through-hole in second aperture again in hole 112, to form coaxial metal interconnection line.It is coaxial mutual using this
Line carries out signal transmission, is conducive to the signal transmission performance for improving entire encapsulating structure.
It is to be appreciated that in this embodiment, by the way that the through-hole interconnection 112 inside chip slot body is arranged in, on the one hand realizing
The short distance interconnection of first chip 105 and second chip 110, on the other hand relative to traditional bonding line (wire bond,
WB it) is more advantageous to interconnection line impedance matching, so that interconnection or transmission performance are preferably promoted, in addition, by metal substrate 101
On large aperture filling holes with resin 1011 in production small-bore interconnected pores, form co-axial interconnection lines, it is entire to be more advantageous to raising
The signal transmission performance of encapsulating structure.
In addition, encapsulating structure provided by the embodiments of the present application can also include:
The first line layer 114 being set on the first lamination dielectric layer 106, and it is set to the second lamination dielectric layer
The second line layer 115 on 111；
In addition, the electrical connection in order to realize the first chip 105 and the second chip 110, in the weld pad with the first chip 105
It is provided with blind hole at the position of opposite the first lamination dielectric layer 106 and first line layer 114, in the weldering with the second chip 110
It pads and is also equipped with blind hole, and filling in the blind hole at the position of opposite the second lamination dielectric layer 111 and the second line layer 115
There is interconnection metal, in this way, being laminated dielectric layer 106 and the second lamination dielectric layer by being set to first line layer 114, first
111 and the second blind hole, first line layer 114, the second line layer 115 and through-hole interconnection 112 on line layer 115 can be real
The electrical connection of existing first chip 105 and the second chip 110.
In addition, encapsulating structure provided by the embodiments of the present application can also include the be covered on the first line layer 114
One solder mask 116, and the second solder mask 117 being covered on second line layer 115.Wherein, the first solder mask 116 and
Need to be provided with different windowings according to different electrical connections on two solder masks 117.
In addition, in order to realize level of integrated system and miniaturization, encapsulating structure provided by the embodiments of the present application to the maximum extent
It can also include: the third chip 118 being set to by face-down bonding mode on first solder mask 116, the third chip
Weld pad such as metal soldered ball on 118 back sides passes through the windowing of the first solder mask 116, first line layer 114 and the first lamination
Blind hole on dielectric layer 106 is electrically connected with first chip 105.In addition, in order to reduce third chip 118 and the first chip 105
Between stress, extend the service life of entire encapsulating structure, also filled up between third chip 118 and the first solder mask 116
There is bottom filler 119.
As an example, the third chip 118 can be the driving chip of encapsulating structure.
In addition, in order to realize being electrically connected for encapsulating structure and external circuit, which can also include being set to the
Metal soldered ball 120 at the windowing position of two solder masks 117, passes through the second solder mask 117 between adjacent different metal soldered ball 120
It is isolated.It is to be appreciated that the metal soldered ball 120 can be BGA soldered ball.In addition, metal soldered ball is only the encapsulating structure and outside
A kind of example of the electric connection structure of circuit electrical connection, as the extension of the embodiment of the present application, which can also be
Metal pad, for example, LGA pad.
As the specific example of the application, metal substrate 101 can be thick base copper sheet or other simultaneous with substrate process
The metal plate of appearance.The thickness of the metal substrate 101 is thicker, generally at 100 microns or more.
Core plate of the metal substrate 101 as the first chip slot substrate 103 and the second chip slot substrate 108, can be straight
Ground connection, so that the good earth for the first chip 105 and the second chip 110 provides possibility.In addition, the metal substrate 101 has
There is good heating conduction, therefore, also provides good heat dissipation channel for the first chip 105 and the second chip 110, improve
The heat dissipation performance of encapsulating structure.
As another specific example, the first adhesive layer 102 and the second adhesive layer 107 are generally printed wiring board
(Printed Circuit Board, PCB) is used or substrate prepreg, such as can be FR-4, BT etc..
When forming chip groove body in order to avoid pressing, the intracorporal excessive glue of slot influences the attachment of microwave radio chip, is set to
The first notching construction size on first adhesive layer 102 is slightly larger than the first chip slot size, is set on the second adhesive layer 107
Second notching construction size is slightly larger than the second chip slot size.In addition, the first notching construction size also with the first adhesive layer 102
Material type is related, and similarly, the second notching construction size is also related to the material type of the second adhesive layer 107.Therefore, it first opens
Quantitative relationship and the second notching construction size and the second chip slot size between slot structure size and the first chip slot size
Between quantitative relationship to be determined according to the material type of laminating media layer.
The first metal layer 104 and second metal layer 109 can be with copper metal layers, as an example, the first metal layer 104 and
Two metal layers 109 can be formed on surface in chip slot body by substrate electroless copper.As another example, the first metal layer
104 and second metal layer 109 can also be formed on surface in chip slot body by PVD seed layer process and electroplating technology.
The first metal layer 104 is by the back side for the first chip 105 being disposed thereon and side wrap, the second metal
The back side and side of layer 109 wrap up the second chip 110 being disposed thereon, to be formed between microwave radio chip
Electromagnetic shielding is conducive to the integrated level for improving encapsulating structure.In addition, the first metal layer 104 and second metal layer 109 can be with
Realize the good earth of the first chip 105 and the second chip 110.
First chip 105 and the second chip 110 can be specially microwave radio chip, or power chip, more
Body, the first, second chip 105 and 110 can be GaAs chip.Moreover, the first chip 105 and the second chip 110 can lead to
It crosses conducting resinl attachment or sintering process is realized and the interconnection of metal substrate 101.
The above are the specific implementations of microwave radio chip-packaging structure provided by the embodiments of the present application.The specific implementation
The encapsulating structure of mode is with the following functions:
1) good earth: metal substrate 101 can be directly grounded, and two microwave radio chips are passed through conductive attachment simultaneously
Or sintering process is realized and is interconnected with metal substrate, and good earth effect is formed, in addition, further, using setting in chip slot
The first metal layer 104 and second metal layer 109 on internal surface can also enhance the good earth effect of two microwave radio chips
Fruit.
2) excellent heat dispersion performance: metal substrate 101 is directly as the first chip slot substrate 103 and the second chip slot substrate
108 core plate can be used as the heat sink of the first chip 105 and the second chip 110, because metal substrate 101 heating conduction compared with
It is good, therefore, heat dissipation channel can be more preferably provided, improve heat dissipation performance.
3) short distance interconnection and coaxial interconnection: the first chip 105 and the second chip 110 are directly realized mutually by route in plate
Even, short distance interconnection on the one hand may be implemented, on the other hand interconnection line impedance matching is more conducive to relative to traditional WB line, thus more
It is good to promote interconnection or transmission performance；In addition, the large aperture being arranged on metal substrate 101 can be passed through in through-hole interconnection 112
Aperture production is bored in filling holes with resin 1011, then, then forms co-axial interconnection lines in aperture, which is more conducive to improve
Signal transmission performance.
4) good electromagnetic shielding: the encapsulating structure is embedding by microwave radio chip, realizes microwave radio chip
Full package structure, realized between different microwave radio chips the first chip and the second chip of setting (specially upper and lower level)
Fine Isolated Shield effect, improves the electromagnetic shielding performance of microwave radio chip module.
5) integrated level at low cost is high: the chips such as driving are formed by face-down bonding mode in the periphery of encapsulating structure, it can
Level of integrated system and miniaturization are realized to greatest extent, in addition the packaging technology can be directly based upon the technique processing of organic substrate,
With low cost, it is suitable for the requirement of scale volume production.
The chip-packaging structure provided based on the above embodiment, the embodiment of the present application also provides a kind of chip package sides
Method.
Chip packaging method provided by the embodiments of the present application is described in detail below with reference to Fig. 2 to Fig. 3 K.
As shown in Fig. 2, chip packaging method provided by the embodiments of the present application includes:
S201: it forms chip groove body: chip groove body being formed by lamination process for pressing, the chip groove body is from top to bottom successively
Including the first chip slot substrate 103, the first adhesive layer 102, metal substrate 101, the second adhesive layer 107 and the second chip slot substrate
108。
This step can specifically include:
A1: by the first chip slot substrate 103 made, the first adhesive layer 102, metal substrate 101, the second adhesive layer
107 and second chip slot substrate 108 align be stacked together in the order described above, form laminated construction.
As shown in Figure 3A, in the embodiment of the present application, it is provided with and the first core on the first chip slot substrate 103 made
Matched first chip slot 1031 of chip size.
It is provided on first adhesive layer 102 made and matched first notching construction of the first chip slot size
1021, wherein when forming chip groove body in order to avoid pressing, the intracorporal excessive glue of slot influences the attachment of the first chip, is set to the
The first notching construction size on one adhesive layer 102 is slightly larger than the first chip slot size, in addition, the first notching construction size also with
The material type of first adhesive layer 102 is related.
It is provided on the second adhesive layer 107 made and matched second notching construction 1071 of the second chip slot size.
It is provided on the second chip slot substrate 108 made and matched second chip slot 1081 of the second chip size；
When forming chip groove body in order to avoid pressing, the intracorporal excessive glue of slot influences the attachment of the second chip, is set to the second adhesive layer 107
On the first notching construction size be slightly larger than the first chip slot size, in addition, the second notching construction size also with the second adhesive layer
107 material type is related.
As an example, metal substrate 101 can be with copper metal plate or other metal plates compatible with substrate process.The metal
Substrate 101 has thicker thickness, is generally not less than 100~150 microns.In addition, for the subsequent production for facilitating through-hole interconnection,
It could be formed with the macroporous structure for being plugged with resin, i.e. filling holes with resin 1011 on the metal substrate 101, set the filling holes with resin 1011
Aperture be the first aperture.
As another example, the first adhesive layer 102 and the second adhesive layer 107 can be used for substrate or PCB plate half is consolidated
Change piece.
It is to be appreciated that in the laminated construction that this step A1 is formed, the first chip slot 1031 and the first notching construction 1021
It is opposite up and down.Second chip slot 1081 and the second notching construction about 1071 are opposite, so could be by the first chipset mounted in the
In one chip slot 1031, by the second chipset in the second chip slot 1081.
A2: each layer structure in above-mentioned laminated construction is pressed together using lamination process for pressing, the integral knot of shape
Structure.
This step can be with specifically: using lamination process for pressing customary in the art by each layer knot in above-mentioned laminated construction
Structure presses together, and forms an overall structure.The overall structure is as shown in Figure 3B.
During the pressing process, the first adhesive layer 102 and the second adhesive layer 107 play the role of key.This first, second
Adhesive layer 12 and 17 all has cementation, wherein a surface of the first adhesive layer 102 can be with the first of metal substrate 101
Surface is bonded together, and another surface can be bonded together with the lower surface of the first chip slot 13.Second adhesive layer 107
It can be bonded together on one side with the second surface of metal substrate 101, another side can be with the lower surface of the second chip slot 1081
It is bonded together.In this way, passing through the cementation of the first adhesive layer 102 and the second adhesive layer 107, by above layers construction bonds
It presses together, forms an overall structure.
S202: metal layer is formed in chip slot: on 1021 inner surface of the first chip slot 1031 and the first notching construction
The first metal layer 104 is formed, forms second metal layer on 1071 inner surface of the second chip slot 1081 and the second notching construction
109。
As an example, this step can be tied in the first chip slot 1031 and the first fluting respectively by chemical-copper-plating process
The first metal layer 104, the shape on 1071 inner surface of the second chip slot 1081 and the second notching construction are formed on 1021 inner surface of structure
At second metal layer 109.
As another example, this step can also be by PVD seed layer process and electroplating technology in the first chip slot
1031 and 1021 inner surface of the first notching construction on form the first metal layer 104, in the second chip slot 1081 and the second fluting knot
Second metal layer 109 is formed on 1071 inner surface of structure.
It is to be appreciated that chip slot inner surface not only includes the bottom surface of chip slot, it further include the side of chip slot.
It is as shown in Figure 3 C that the step has executed corresponding the schematic diagram of the section structure.
S203: the first, second chip attachment: forming the first chip 105 on the first metal layer 104, first chip 105
It is electrically connected between the metal substrate 101；The second chip 110 is formed in the second metal layer 109, second chip 110 with
It is electrically connected between the metal substrate 101.
This step can be with specifically: carries out a conducting resinl on 109 surface of the first metal layer 104 and second metal layer first
Or the adhesive layer of other conductive energy is formed, then, according to conducting resinl or the bonding material of other conductive energy
The technological parameter of material mounts upper first chip 105 on the first metal layer 104, and upper second core is mounted in second metal layer 109
Piece 110.When mounting the first chip 105 and the second chip 110, make back gold and the first metal layer on 105 back side of the first chip
104 electrical connections, are electrically connected the back gold on 110 back side of the second chip with second metal layer 109.
The first metal layer 104 and second metal layer 109 are electrically connected between metal substrate 101, therefore, the first chip
It is electrically connected between 105 and metal substrate 101, is electrically connected between the second chip 110 and metal substrate 101.
It is as shown in Figure 3D that the step has executed corresponding the schematic diagram of the section structure.
The lamination of S204: the first, second chip is embedding: deviating from the table of the metal substrate 101 in the first chip slot substrate 103
The first lamination dielectric layer 106 for coating first chip 105 is formed on face, deviating from the second chip slot substrate 108 should
The second lamination dielectric layer 111 for coating second chip 110 is formed on the surface of metal substrate 101.
This step can be with specifically: on two surfaces of chip groove body for being pasted with the first chip 105 and the second chip 110
It is respectively formed the first lamination dielectric layer 106 and the second lamination dielectric layer 111, to realize the first chip 105 and the second chip
110 it is embedding.Effect is preferably wrapped up to the first, second chip in order to realize, is used to form the first lamination dielectric layer 106 and
The material of two laminating media layers 111 has preferable filling capacity, as an example, being used to form 106 He of the first lamination dielectric layer
The material of second dielectric layer 111 can use for PCB or substrate semi-solid preparation material.
In the embodiment of the present application, the size of the first chip slot 1031 and the first notching construction 1021 can be greater than the first core
The size of piece 105, in this way, during the pressing process, the material for being used to form the first lamination dielectric layer 106 can be extruded to
In gap between one chip slot 1031 and the first notching construction 1021 and the first chip 105, in this way, the first lamination dielectric layer
106 can also include in the gap between the first chip slot 1031 and the first notching construction 1021 and the first chip 105
Part, to realize the package to the first chip 105.
Similarly, during the pressing process, the material for being used to form the second lamination dielectric layer 111 can be extruded to the second chip
In gap between slot 1081 and the second notching construction 1071 and the second chip 110, in this way, the second lamination dielectric layer 111 may be used also
To include the part in the gap between the second chip slot 1081 and the second notching construction 1071 and the second chip 110, from
And realize the package to the second chip 110.
The step has executed corresponding the schematic diagram of the section structure as shown in FIGURE 3 E.
S205: it forms through-hole interconnection: being formed through the first lamination dielectric layer 106, chip groove body and the second laminating media
The through-hole interconnection 112 of 111 upper and lower surface of layer.
In order to realize the preferable interconnection performance of the first chip 105 and the second chip 110, by the way of machine drilling,
It is formed in the peripheral region of the first chip slot 1031 and second chip slot 1081 through the first lamination dielectric layer 106, core
The through-hole interconnection 112 of piece groove body and the second lamination 111 upper and lower surface of dielectric layer.The step has executed corresponding cross-section structure
Schematic diagram is as illustrated in Figure 3 F.
It is to be appreciated that after making filling holes with resin 1011 in the first aperture on metal substrate 101, in order to improve signal
Transmission performance, S205 can be with specifically: drill, formed through the first lamination dielectric layer in the corresponding position of filling holes with resin 1011
106, the through-hole in the second aperture of chip groove body and the second lamination 111 upper and lower surface of dielectric layer, the through-hole in second aperture are
For through-hole interconnection 112.
S206: metal interconnecting wires 113 are formed in through-hole interconnection 112:
In order to realize the interconnection of the first chip 105 and the second chip 110, it is also necessary to fill metal into through-hole interconnection 112
Form metal interconnecting wires 113.It is to be appreciated that when through-hole interconnection 112 is small by boring on the filling holes with resin 1011 in the first aperture
Hole formed when, S206 formed metal interconnecting wires 113 be coaxial metal interconnection line, so, it is possible improve signal transporting
Energy.
As an example, this step can with specifically includes the following steps:
Metal is filled into through-hole interconnection 112 by electroplating technology first, metal interconnecting wires 113 is formed, then passes through again
Screen printing mode realizes filling holes with resin, and the remaining resin in surface layer is removed, and then passes through in the corresponding position of chip pad
Laser drilling process realizes the processing and fabricating of the first lamination dielectric layer 106 and the blind hole on the second lamination dielectric layer 111.
The step has executed corresponding the schematic diagram of the section structure as shown in Figure 3 G.
S207: production line layer: first line layer 114 is made on the first lamination dielectric layer 106, in the second laminating media
The second line layer 115 is made on layer 111.
This step can be with specifically: is making First Line on the first lamination dielectric layer 106 by subtraction or plate addition process
Road floor 114 makes the second line layer 115 on the second lamination dielectric layer 111.
Subtractive processes are exactly the plating metal copper for first carrying out whole plate, then carry out pattern mask and make laggard row metal etching
Line layer required for being formed.
And semi-additive process is first to carry out one layer of seed layer production, and the system of graphic mask is then carried out by exposure development
Make and then wants figure with will perform etching to obtain after exposure mask removing removal after exposure mask progress graphic plating.
It is to be appreciated that can also be laminated on dielectric layer 106 and the first chip pad pair first before making line layer
Blind hole is formed by laser drilling process at the position answered, it is corresponding with the second chip pad on the second lamination dielectric layer 111
Blind hole (step has executed corresponding the schematic diagram of the section structure as shown in figure 3h) is formed by laser drilling process at position.Such as
This can also fill metal into the blind hole for being produced on the first lamination dielectric layer 106 while making first line layer 114,
To realize the interconnection of signal.It, can also be to being produced on the second lamination dielectric layer 111 while making the second line layer 115
Interior filling metal, to realize the interconnection of signal.The step has executed corresponding the schematic diagram of the section structure as shown in fig. 31.
S208: production solder mask: the first solder mask 116 is made on first line layer 114, on the second line layer 115
Make the second solder mask 117.
The first solder mask 116 is made on first line layer 114 of technological means customary in the art, in the second route
The second solder mask 117 is made on layer 115, and according to different electrical connection needs, the first solder mask 116 and the second solder mask 117
On be provided with different windowings.The step has executed corresponding the schematic diagram of the section structure as shown in figure 3j.
S209: chip face-down bonding: forming third chip 118 by face-down bonding mode on the first solder mask 116, should
Third chip 118 is electrically connected with first chip 105.
In order to realize that the integrated level of encapsulating structure, this step can be by face-down bonding modes in the first solder mask 116
On, third chip 118 is formed, which passes through the windowing of the first solder mask 116, first line layer 114 and first
Blind hole on laminating media layer 106 is electrically connected with first chip 105.In addition, in order to reduce third chip 118 and the first chip
Stress between 105 extends the service life of entire encapsulating structure, also fills out between third chip 118 and the first solder mask 116
Filled with bottom filler 119.
As an example, the third chip 118 can be the driving chip of encapsulating structure.
The step has executed corresponding the schematic diagram of the section structure as shown in Fig. 3 K.
S210: it plants metal soldered ball: planting metal soldered ball 120 at the windowing position of the second solder mask 117, pass through the metal welding
The realization encapsulating structure of ball 120 is electrically connected with external circuit.
In order to realize being electrically connected for encapsulating structure and external circuit, which can also include:
Metal soldered ball 120 is planted at the windowing position of the second solder mask 117, and encapsulation knot is realized by the metal soldered ball 120
Structure is electrically connected with external circuit.It is isolated between adjacent different metal soldered ball 120 by the second solder mask 117.It needs
Bright, metal soldered ball is only a kind of example for the electric connection structure that the encapsulating structure is electrically connected with external circuit, as the application reality
The extension of example is applied, which can also be metal pad.
It is as shown in Figure 1 that the step has executed corresponding the schematic diagram of the section structure.
The above are the specific implementations of chip packaging method provided by the embodiments of the present application.It, should in the packaging method
Packaging method can be directly based upon the technique processing of organic substrate, have low cost, be suitable for the requirement of scale volume production.
The above are specific embodiments provided by the embodiments of the present application.The protection scope of the application is not limited to described above
Specific embodiment, the technical solution obtained to the modification of above-mentioned specific embodiment, replacement is in the protection scope of the application
Column.
Claims (10)
1. a kind of chip-packaging structure characterized by comprising
Chip groove body, the chip groove body include metal substrate and the first bonding being sequentially located on metal substrate first surface
Layer and the first chip slot substrate；It is provided on the first chip slot substrate and matched first chip slot of the first chip size；
It is provided on first adhesive layer and matched first notching construction of the first chip slot size；
The first metal layer being set on first chip slot and the first notching construction inner surface；
The first chip being set on the first metal layer；It is electrically connected between first chip and the metal substrate；
And it is set to first lamination dielectric layer of the first chip slot substrate on the surface of the metal substrate, it is described
First lamination dielectric layer is for coating first chip.
2. encapsulating structure according to claim 1, which is characterized in that the laminated stack chip groove body further include:
The second adhesive layer and the second chip slot substrate being sequentially located on metal substrate second surface；Wherein, the metal substrate
First surface is opposite with the metal substrate second surface；It is provided on second adhesive layer and is matched with the second chip slot size
The second notching construction, be provided with and matched second chip slot of the second chip size on the second chip slot substrate；
The encapsulating structure further include:
The second metal layer being set on second chip slot and the second notching construction inner surface；
The second chip being set in the second metal layer；It is electrically connected between second chip and the metal substrate；
And it is set to second lamination dielectric layer of the second chip slot substrate on the surface of the metal substrate, it is described
Second lamination dielectric layer is for coating second chip.
3. encapsulating structure according to claim 2, which is characterized in that the encapsulating structure further include: run through described first
The through-hole interconnection of laminating media layer, chip groove body and the second lamination dielectric layer upper and lower surface, the through-hole interconnection is located at described
The periphery of first chip slot and second chip slot, the through-hole interconnection is interior to be filled with metal interconnecting wires.
4. encapsulating structure according to claim 3, which is characterized in that the metal interconnecting wires are co-axial interconnection lines.
5. encapsulating structure according to claim 1-4, which is characterized in that the encapsulating structure further include:
The first line layer being set on the first lamination dielectric layer, and be set on the second lamination dielectric layer the
Two line layers；The through-hole interconnection is electrically connected with the first line layer and second line layer.
6. encapsulating structure according to claim 5, which is characterized in that the encapsulating structure further include:
The first solder mask being formed on the first line layer, and the second welding resistance being formed on second line layer
Layer, windowing is provided with according to electrical connection demand at different locations on first solder mask and second solder mask.
7. structure according to claim 6, which is characterized in that the encapsulating structure further include:
The third chip that the first solder mask opens a window at position, the third chip and described the are set to by face-down bonding mode
The electrical connection of one chip.
8. structure according to claim 5, which is characterized in that the encapsulating structure further include: be set to the second solder mask
Electric connection structure at windowing position, the electric connection structure with external circuit for being electrically connected, between different electric connection structures
It is isolated by second solder mask.
9. a kind of chip packaging method characterized by comprising
Chip groove body is formed by lamination process for pressing, the microwave radio groove body includes at least metal substrate and is sequentially located at
The first adhesive layer and the first chip slot substrate on metal substrate first surface；It is provided on the first chip slot substrate and the
Matched first chip slot of one chip size；It is provided on first adhesive layer and is opened with the first chip slot size matched first
Slot structure,
The first metal layer is formed on first chip slot and the first notching construction inner surface；
The first chip is formed on the first metal layer, is electrically connected between first chip and the metal substrate；
The for coating first chip is formed on surface of the first chip slot substrate away from the metal substrate
One laminating media layer.
10. packaging method according to claim 9, which is characterized in that the microwave radio groove body further include: be sequentially located at
The second adhesive layer and the second chip slot substrate on metal substrate second surface；Wherein, the metal substrate first surface and institute
It is opposite to state metal substrate second surface；It is formed on second adhesive layer and is tied with matched second fluting of the second chip slot size
Structure is formed with and matched second chip slot of the second chip size on the second chip slot substrate；
It is described to be formed after chip groove body by lamination process for pressing, further includes:
Second metal layer is formed on second chip slot and the second notching construction inner surface；
The second chip is formed in the second metal layer, is electrically connected between second chip and the metal substrate；
The for coating second chip is formed on surface of the second chip slot substrate away from the metal substrate
Two laminating media layers.
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| CN112151458A (en) * | 2020-09-24 | 2020-12-29 | 维沃移动通信有限公司 | Functional packaging module and preparation method thereof, functional packaging assembly and electronic equipment |
| CN112466864A (en) * | 2020-11-03 | 2021-03-09 | 扬州船用电子仪器研究所(中国船舶重工集团公司第七二三研究所) | Three-dimensional stacked microwave assembly based on high-temperature co-fired ceramic |
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