TW201240044A - Packaging substrate with well structure filled with insulator and manufacturing method - Google Patents

Packaging substrate with well structure filled with insulator and manufacturing method Download PDF

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Publication number
TW201240044A
TW201240044A TW100118104A TW100118104A TW201240044A TW 201240044 A TW201240044 A TW 201240044A TW 100118104 A TW100118104 A TW 100118104A TW 100118104 A TW100118104 A TW 100118104A TW 201240044 A TW201240044 A TW 201240044A
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Taiwan
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metal
package substrate
well
filled
insulator
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TW100118104A
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Chinese (zh)
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Jen Chen
Gao-Peng Chen
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Rda Microelectronics Beijing Co Ltd
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Publication of TW201240044A publication Critical patent/TW201240044A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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    • H01L23/495—Lead-frames or other flat leads
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    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49537—Plurality of lead frames mounted in one device
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
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    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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Abstract

The invention discloses a packaging substrate with a well structure filled with an insulator and a manufacturing method thereof. The packaging substrate is characterized by being provided with at least one well; and the well is filled with insulating materials to form the well structure, and the upper surface of the well structure is provided with a metal pattern. The method comprises the following steps of: manufacturing at least one well on a metal framework; filling the well with insulating materials to form the well structure; and making the metal pattern on the upper surface of the well structure filled with the insulating materials. Compared with the prior art, the packaging substrate with the well structure filled with the insulator and the manufacturing method thereof have the advantages that the problems of inflexible routing, low radio frequency inductance value and the like of a multi-chip module substrate produced by the prior art are solved; and furthermore, the manufacturing technology is simple, the price is low, the large-area grounding pad is complete, the substrate has good radiating performance, and a high-quality interconnection method is provided.

Description

201240044 六、發明說明： 【發明所屬之技術領域】 本發明涉及多晶片模組的封裝領域，具體地說，本發 明涉及一種帶有絕緣體填充的阱結構的封裝基板及其方法 【先前技術】 多晶片模組（MCM，Multi Chip Module)是在一個封裝 内包含了多個半導體晶片，並且半導體晶片之間的互連是 通過金屬鍵合線及基板上的金屬互連線完成。通常，曰 y 日日 片杈組封裝所採用的基板是一塊多層互連基板，可以由低 溫共燒陶瓷（LTCC，Low Temperature Co-fired Ceramic) 技術或多層層壓基板製造e LGA(Land Grjd Array)封裝是 多晶片模組常用的一種半導體封裝形式，其採用多層層壓 基板，在金屬材料層上可以製作互連走線；相鄰的不同金 屬材料層由絕緣材料層隔離；位於不同金屬材料層上的走 線可以通過貫穿絕緣材料層的過孔相互連接。lga基板的 金屬互連可以用於製作射頻電感元件、表面黏著元“Μ。 ’ Surface Mounted Device)谭接焊墊。用於無線通訊領域 的射頻電路由於需要用電感、電容等無源元件製作匹配網 路和濾波網路，通常^能做到單晶#㈣。採用LGA封裝 形式則可以通過黏著電感、電容等方式以達到封裝集成的 目的。目冑’射頻功率放大器模組以及集成有.射頻；線開 關的射頻前端模組產品絕大多數是採用LGA封裝， =常到4層，同時内部黏著有電感、電容甚至攄二 态寺70件。 201240044 如圖1a所示，為一個採用2層金屬層LGA封裝的多 晶片模組的示意圖。如圖所示，多晶片模組）〇〇中包含兩 個黏著在其上表面金屬層的晶片U1和U2。通過鍵合線 1 08，可以將晶片U1和U2上相應的晶片鍵合焊墊相互連 接起來，或者將晶片U1和U2上的晶片鍵合焊墊連接到 LG A基板上的相應接腳1〇7，也可以將ui和（J2上的晶片 鍵合焊墊連接到LGA基板上表面的相應基板鍵合焊墊上。 將LGA基板上表面金屬層上的走線製作為平面螺旋結構， 可以實現電感元件，如圖1a中所示的平面螺旋電感1〇1及 1 02。由於通常|_GA封裝中金屬層的厚度可以達到幾十甚 至上百微米，使得其製作的平面螺旋電感的寄生電阻很小 ，從而使電感元件有較向的品質因數（Q值），這對於提高射 頻電路的性能是非常有意義的。如圖，a所示，晶片U2上 的晶片鍵合焊墊通過鍵合線1〇8連接到了平面螺旋電感 1 02的一端；平面螺旋電感彳〇2的另外一端通過導通孔 1 03連接到了 LG A基板下表面金屬層的走線1〇4的一端； 走線1 04的另外一端連接到了 |_ga模組的接腳1 〇7，這就 實現了晶片U2上晶片鍵合焊墊與lGA模組接腳1〇7的相 互電氣連接。並且’纟LGA基板上表面上，還可以黏著 SMD元件，如圖1a中所示的1〇9。SMD元件1〇9通常可 以疋電阻電谷、電感、二極體等無源元件，通過鍵合線 108及LGA基板金屬層走線，SMD元件1〇9可以非常方便 地連接到模組内的晶片及模組的接腳。可以看到，LGA封 裝形式為多晶片模組内的信號互連提供了报大的靈活性， 尤其是在射頻應用中，它可以集成高品質的無源元件（如高 4 201240044 Q值的平面螺旋電感、SMD元件等），使得射頻多晶片模組 具有較高的性能。 然而，LGA封裝形式也有一些缺點。首先，lGA基板 的製造技術非常複雜，需要經過一系列材料層壓、鑽孔、 填充導電導熱材料、光刻腐蝕金屬層、電鍍金屬等步驟， 使得LGA封裝的價格昂貴。 其次，由於LG A基板材料通常是用導熱性能不佳的樹 月曰材料製作，在大功率應用下晶片散熱也受到很大限制。 並且，通常LGA背面金屬層都需要走線，就破壞了其背面 接地金屬焊墊的完整性，或使其背面接地金屬焊墊的面積 減小，不利於LGA封裝的半導體元件在peg上的黏著。 無引線方形扁平封裝（QFN，Quad Flat Non·丨eaded package)是一種基於金屬框架的無引腳封裝，其封裝中央 位置有大面積裸露的晶片黏著焊墊（DAp ’ Dje Attach Paddle) ’具有導熱作用。採用集成無源元件（丨pD， Integrated Passive Device)技術，將射頻電路中所需的電 感、電容等無源元件製作在一個半導體晶片上，進而可以 在QFN上實現功能較為簡單的射頻功率放大器模組、前端 模組。如圖1 b所示為一個採用qfn封裝的多晶片模組。 QFN封裝在金屬框架上直接黏著半導體晶片（如圖1b中所 示的晶片U1、U2和U3)，使得製造技術比LGA封裝簡單 得多。然而，相對於LGA封裝形式，qFn金屬框架上不能 提供互連走線’使得多晶片之間僅能通過晶片間金屬鍵合 線互連，不能滿足多數多晶片模組設計要求。 美國專利US71541 69中所提出的技術方案，通過在 201240044 QFN接腳之間安置金屬線形成非相鄰接腳間互連，也未能 很好解決晶片間的互連問題。並且，為了放置這種互連金 屬線，會導致金屬框架DAP背面接地金屬焊墊形狀不規則 且接地面積縮小，而規則的背面接地金屬焊墊是保證工業 生產焊接良率的重要條件。另外，該專利也提出了在接腳 間黏著電容S件’但是實際上很多電容需要黏著在晶片之 間或者與電感元件串聯使用’其方案也不能滿足此要求。 對於射頻功率放大器模組及射頻前端模組而言，其背 面金屬需要直接接地，並且要求有盡可能大的背面接地金 屬焊墊來降低寄生接地電感以提供良好的射頻接地，確保 晶片的電氣性能不會惡化。當前無線通訊產品設計要求射 頻功率放大器模組及射頻前端模組尺寸盡可能小，而其功 率指標並未降低，因此盡可能大的背面接地金屬焊塾也有 利於模組的散熱。 【發明内容】 本發明所要解決的技術問題是提供一種帶有絕緣體填 充的附結構的封裝基板及其製造方法，以解決現有技術所 生產的多晶片模組基板走線不靈活，射頻電感值低等問題 〇 為解決上述技術問題，本發明提供了一種帶有絕緣體 填充的I结構的封裝基板’其特徵在於，所述封裝基板具 有至少-個啡’所述牌中填充有絕緣材料形成啡結構，且 所述阱結構的上表面上具有金屬圖形。 進-步地’其中，所述金屬圖形為與所述封裝基板的 201240044 接腳直接相連的金屬走線、黏著 、基板鍵合焊墊或倒扣安裝半導體晶片的錫;?墊焊接焊塾 走線進#地，其中，所述金屬走線為單層或多層的金屬 種帶有絕緣 為解決上述技術問豸，本發明還提供了 體填充的阱結#的封裝基板製造方&，包括 在金屬框架上製作至少一個阱； 在所述解中填充絕緣材料形成胖結構，在填充完 材料後的所述阱結構的上表面製作金屬圖形。 .進一步地，其中’在金屬框架上下表面進行掩膜處理 ，然後再通過腐蝕或蝕刻在所述金屬框架上製作至少一個 阱。 進一步地，其t，在填充完絕緣材料後的所述阱結構 的上表面通過電鍍金屬或沈積金屬方式製作金屬圖形。 進步地，其中，所述金屬圖形進一步為與所述封裝 基板的接腳直接相連的金屬走線、黏著表面黏著元件的焊 接焊墊、基板鍵合焊墊或倒扣安裝半導體晶片的錫球焊墊 進一步地，其中’所述金屬圖形被絕緣材料覆蓋。 進一步地，其中，所述金屬走線進一步為單層或多層 的金屬走線。 與現有技術相比，本發明所述的帶有絕緣體填充的啡 結構的封裝基板及其製造方法，解決了現有技術所生產的 多晶片模組基板走線不靈活、射頻電感值低等問題；且製 造技術簡單、價格便宜、有完整的大面積接地焊墊、同時 201240044 具有良好的散熱性能，並提供了高品質的内部互連方法 【實施方式】 本發明的主要思想是解決現有的多晶片模組的封裝基 板走線不靈活’射頻電感值低等問題。本發明提供了製造 技術簡單、價格便宜、有完整的大面積接地焊墊、同時具 有良好的散熱性能的多晶片模細封裝基板及方法。以下對 具體實施方式進行詳細描述，但不作為對本發明的限定。 為實現多晶片模組的封裝基板，如圖2a至2j所示， 本發明實施例一提供一種帶有絕緣體填充的阱結構金屬框 架（WES，Well Embedded Substrate)的封裝基板的製造方 法’具體製作流程為： (a) 如圖2a所示，取一塊厚度合適的金屬板2〇1，其 材料可以為銅、鋁、鐵、銅合金或鎳鐵合金等，並且金屬 板201上下表面平整。這裡可以根據實際應用選取材料， 本發明不做具體限定。 (b) 在金屬板201上下表面塗覆或黏著用於定義圖形 的掩膜，如圖2b所示，上表面掩膜2〇2及下表面掩膜2〇3 〇 (c) 如圖2C所示，對所述帶掩膜的金屬板2〇1進行腐 蝕（或蝕刻等等同技術）’從金屬板2〇1上表面向下腐蝕出 阱 204、205、206。 這裡在本發明中，“阱”指的是在金屬板上腐蝕出來 ，並且其腐蝕掉的部分的厚度小於金屬板的厚度，可以參 照圖2c理解“阱”的定義。由上可知，阱的位置由步驟 8 201240044 2b中上表面掩膜202所定義。 (d) 在所述帶有阱204、205、206的金屬板201上下 表面塗覆或黏著用於定義圖形的掩膜，如圖2d所示的上表 面掩膜202及下表面掩膜203。 (e) 對所述帶有牌204、205、206且帶掩膜的金屬板 201進行腐蝕（或蝕刻等等同技術），從金屬板2〇1下表面向 上腐蝕。如圖2e可知，由於在本步驟的腐蝕中，原先的阱 205、206底部的金屬板部分被腐#掉，從而出現如圖& 所示的孔207及208,他們完全貫穿了金屬板2〇1的厚度 ，而阱204仍然保持不變。在這裡需要說明的是，在本發 明中’需要區分“孔’’及‘‘啡”的區別，通過參照圖^， 可以更加容易理解其區別。如圖2e所示，在此步 後，金屬板201上形成了 WES封裝基板接腳216部分及 晶片貼裝區域（DAP)217部分。 ⑴採用樹脂或塑膠等絕緣材料填充上述步驟形 m及孔m、m，如圖2ί所示，得到了上下表面都平 整的臟封裝基板。這-步驟完成之後，在WES封裝基 板上形成了 I结構209及孔結構21Q、211。這裡 的是，本發明中、結構’，“絕緣材料填充、，，而形 成的1結構由底部金屬以及其上的絕緣材料組成。 啡結構中絕緣材料周圍有金屬支撑，所述周圍金屬可以曰 完全讓結構的側圍，也可以是部分包圍。例如在二 2f中，虛線框所示的I结構2〇9,其側圍被周圍金屬所* 全包圍’而在本發明的另外_個實施例中1 & 以被周圍金屬所部分包圍。 、。籌側圍可 201240044 (g) 如圖2g所示’在上述WES封裝基板的阱結構 209的上表面上，採用電鍍金屬（或沈積金屬等等同技術）的 方法，形成金屬走線212。這裡需要注意的是，本步驟形 成的金屬走線212’還包括可以用於金屬線鍵合的鍵合焊 墊（稱為基板鍵合焊墊）、可以用於黏著SMD(Surface Mounted Devices，表面黏著元件）元件的焊接焊墊、可以 用於倒扣安裝半導體晶片的錫球焊墊等；並且，通過增加 沈積絕緣介質層、光刻掩膜等步驟，阱結構209上製作的 金屬走線212可以是多層結構。 (h) 上述幾個步驟已經完成了 wes封裝基板製造的基 本步驟，在基於WES封裝基板的半導體封裝製造中，本步 驟將半導體晶片213黏著在WES封裝基板中金屬板2〇1 的晶片貼裝區域（DAP)217上表面、將Smd元件黏著在製 作於阱結構209上的焊接焊墊上。然後進行金屬線鍵合作 業採用鍵合線214完成晶片鍵合焊墊、基板鍵合焊墊及 WES接腳之間的相應互連，如圖之卜所示。 (1)為了完成基於WES封裝基板的半導體元件的封裝 ，通常在上述完成晶片和SMD元件黏著及鍵合作業的 WES基板上採用密封樹脂215等材料進行密封作業，使得 :E入S封裝基板上表面、晶片*議元件以及鍵合線等都 完全包覆在密封材料中，即發明内容中所述的金屬圖形被 、邑緣材料覆蓋。這就完成了基於WES基板的半導體元件 封裝，如圖2i所示。 干的 如圖3a至3d所示，為採用本發明所提出的WEs基 板封裝的-個多晶片模組’作為本發明的實際操作的第— 201240044 個實施例。一個多晶片模組300，其採用了如上述製作流 程所製作的WES封裝基板，WES封裝基板的上表面金屬 晶片貼裝區域302黏著了兩個半導體晶片U1及U2。兩個 半導體晶片U1及U2上的晶片鍵合焊墊，通過鍵合線303 相互連接；鍵合線303還可以將兩個半導體晶片U1及U2 上的晶片鍵合焊墊連接到相應的WES封裝基板接腳304上 或者晶片貼裝區域302上。 如圖3a所示，DAP部分302及其周圍的接腳304為 金屬材料，陰影部分標示的308、305則為絕緣材料，其 中虛線框所標示的305部分為阱結構，在阱結構305的上 表面’採用前述技術步驟製作了金屬走線，如圖33所示， 包括了平面螺旋電感306、黏著SMD元件307的焊接焊塾 3〇9及其相應走線以及基板的鍵合焊墊31〇等。通過鍵合 線303，可以將平面螺旋電感3〇6、黏著sMd元件3〇7連 接到半導體晶片的鍵合焊墊310、WES基板接腳304等進 行互連，從而可以將製作或黏著在阱結構305上表面的元 件連接到電路之t。這裡需要說明的是’通過電鍍或沈積 方式在阱結構305上表面製作的金屬走線，其厚度通常可 以高達數十微米甚至更高，使得其寄生電阻报小，電感Q 值很兩’這有助於提尚射頻應用多晶片模組的性能。 如圖3b所示為多晶片模組3〇〇的背面示意圖，可以看 到儘管胖結構上製作了金屬走線，晶片貼裝區肖3〇2的背 面仍然是大面積完整且形狀規則的，其完整性由於採用了 阱、構而侍到了保全，這也是本發明所提出的wes基板的 -個發明目的。這裡需要說明的是，WES封裝基板這種面 201240044 積最大化的接地焊墊，為半導體晶片提供了良好的電氣接 地及導熱通路，非常有助於提高射頻應用多晶片模組的性 能。從如圖3c所示的剖面圖（沿A_A切線方向）上，也可以 看到阱結構的阱結構305部分與金屬板、WES封裝基板接 腳304、孔結構308在厚度方向上的關係。如圖％所示為 完成樹脂密封之後的多晶片模組的剖面圖（沿A_A切線方向 )，312為密封材料。 如上所述，可以看到基於WES封裝基板的多晶片模紐 封裝製作技術簡單，僅在普冑QFN封裝製作技術上增加了 牌結構定義及製作、牌結構上金屬連線製作等步驟，複雜 度遠遠低於LGA封裝技術。同時，由於在牌結構上表面可 以製作高Q㈣金屬走線、平面螺旋電感、多層互連線结 構以及黏I SMD元件等，相對於⑽封裝有更大的互連 靈活性》並且，WES封裝基板能夠提供面積最大化的背面 接地金屬焊墊，為半導體晶片提供了良好的電氣接地及導 熱通路。因此，本發明所提出的WES封裝基板結構，製造 技術簡單、價格便宜、有完整的大面積接地焊墊、同時具 有良好的散熱性能’並提供了高品質的内部互連方法〆、 需要說明的是，在上述實施例中，㈣封裝基板上且 有-個獨立㈣㈣3〇5。事實上，根據本發明所提出的 技術方案’在具體實施中可以根據需要在WES封裝基板上 製作多個阱結構。 如圖4a“d所示實際操作的第二個實施例，WES封 裝基板上具有兩個以獨立虛線框表示的畔結構彻及楊( 如圖杓中虛線框所示）。其中解料4〇4的特點是，其側 12 201240044 圍被金屬框架完全包圍’並且可以在其平整的上表面上製 作金屬走線及SMD焊接焊墊等其他圖形，如圖中所示的平 面螺旋電感405、黏著SMD元件406的焊接焊墊411以及 基板鍵合焊墊412。而阱結構41〇的特點是，其側圍被金 屬框架部分包圍，並且可以在其平整的上表面上製作金屬 走線及SMD焊接焊塾等其他圖形，如圖4a中所示的平面 螺旋電感408、連接到WES封裝基板接腳4〇1的金屬走線 407、黏著SMD元件409的焊接焊墊以及基板鍵合焊墊。 如圖4b所示為多晶片模組4〇〇的背面示意圖’可以看到儘 管阱結構404及410上製作了金屬走線，晶片貼裝區域 402的背面仍然是大面積完整且形狀規則的。從如圖&所 示的剖面圖（沿Β·Β切線方向）上，也可以看到阱結構的虛 線框410部分與晶片貼裝區域4〇2、孔結構4〇3、接腳 401在厚度方向上的關係。如圖4d所示為完成樹脂密封之 後的多晶片模組的剖面圖（沿B_B切線方向），414為密封材 料。 此外，本發明實施例還提供另外一種帶有絕緣體填充 的阱結構金屬框架製作（WES，We|| Embedded Substrate) 的封裝基板的製造方法，如圖5a至5d所示，該方法具體 步驟包括： (a) 將一塊厚度合適的金屬板8〇1，上下表面塗覆或黏 著掩膜802、803，然後進行腐蝕（钱刻）。 (b) 將另外一塊厚度合適的金屬板8〇7,上下表面塗覆 或黏著掩膜808、809，然後進行腐蝕（蝕刻卜 (c) 將上述步驟（a)及步驟（b)得到的腐蝕後的兩塊金屬 13 201240044 板拼接在一起，如圖5c所示，可以看到本步驟形成了孔 813、814 及阱 815。 (d)採用樹脂或塑膠等絕緣材料填充上述步驟形成的 阱815及孔813、814，得到阱結構818及孔結構816、 817。如圖5d所示可以看到，這裡形成的阱結構818及孔 結構816、817與如圖2h中所示的阱結構209及孔結構 210、211是等價的。 如圖6a至6c所示，對於上述實施例來說，WES封裝 基板的製造方法的另外一種製作流程： (a) 將一塊厚度合適的金屬板901，上下表面塗覆或黏 著掩膜902、903 ’然後進行腐蝕（触刻）。 (b) 在腐蝕過的金屬板上填充絕緣材料9〇7、9〇8、 909，形成如圖6b所示的結構。 (c) 在上述金屬板905、904及906部分上沈積（或稱 填充）金屬材料’形成金屬911、912、913及914部分， 如圖6c所示《可以看到，這裡形成的阱結構91〇及孔結構 907、908與如圖2h中所示的阱結構209及孔結構21 0、 211是等價的。 需要說明的是，上述WES封裝基板的製造方法及流程 ，僅作為形成WES封裝基板的示例，而非對WES封裝基 板製造方法的限定。任何與上述製造流程具有等同技術效 果的方法，都可以用於製造WES封裝基板，在WES封装 基板上形成絕緣材料填充的阱結構，並在所述阱結構上表 面製作金屬走線。由於所述阱結構嵌入金屬框架，使得 WES封裝基板背面裸露的接地金屬焊塾部分不受阱結構的 201240044 製造影響，仍然可以保持大面積的裸露金屬焊塾。 如上所述’可以看到基於WES封裝基板的多晶片模组 封裝製造技術簡單’僅在普通QFN封裝製造技術上增加了 钟結構義及製造、味結構上金屬連線製造等步驟，複雜 度遠遠低於LGA封裝技術。同時，由於㈣結構上表面可 以製作高Q值的金屬走線、平面螺旋電感、多層互連線結 構以及㈣SMD元件等，相對於QFN封裝有更大的互^ 靈活性。並且’ WES封裝基板能夠提供面積最大化的背面 接地金屬焊墊，為半導體晶片提供了良好的電氣接地及導 熱通路。因此，本發明所提出的WES封裝基板結構，製造 技術簡單、價格便宜、有完整的大面積接地焊墊、同時具 有良好的散熱性能’並提供了高品質的内部互連方法。^ 當然，本發明還可有其他多種實施例，在不背離本發 明精神及其實質的情況下’熟悉本領域的技術人員可根據 本發明做出各種相應的改變和變形，但這些相應的改變和 變形都應屬於本發明所附的權利要求的保護範圍。 【圖式簡單說明】 圖1a為現有的採用2層金屬層LGA封裝的多晶片模 組的示意圖； 圖1b為現有的採用QFN封裝的多晶片模組的示意圖 9 圖2a至圖2i為本發明實施例一所述的帶有絕緣體填 充的味結構的封裝基板的製造方法示意圖； 圖3a為本發明實施例二所述的帶有絕緣體填充的胖結 15 201240044 構的封裝基板的正面示意圖； 圖3b為本發明實施例二所述的帶有絕緣體填充的牌結 構的封裝基板的背面示意圖； 圖3c為本發明實施例二所述的帶有絕緣體填充的阱結 構的封裝基板的沿圖3a和3b所示切線a_a的剖面圖； 圖4a為本發明實施例三所述的帶有絕緣體填充的阱結 構的封裝基板的正面示意圖； 圖4b為本發明實施例三所述的帶有絕緣體填充的阱結 構的封裝基板的背面示意圖； 圖4c為本發明實施例三所述的帶有絕緣體填充的阱結 構的封裝基板沿圖4a和4b所示切線B-B的剖面圖； 圖4d為本發明實施例三所述的帶有絕緣體填充的阱結 構的封裝基板沿圖4a和4b所示切線b_b塑封之後的刊面 rsn · 圃， 圖5a至圖5d為本發明實施例四所述的帶有絕緣體填 充的阱結構的封裝基板的第二種製造方法示意圖； 圖6a至圖6c為本發明實施例五所述的帶有絕緣體填 充的拼結構的封裝基板的第三種製造方法示意圖。 【主要元件符號說明】 1 00多晶片模組 1 1,1 〇2平面螺旋電感 103導通孔 104走線 107接腳 109 SMD元件 2〇1金屬板 203下表面掩膜 108鍵合線 U1，U2，U3 晶片 202上表面掩膜 204,205,206 阱 16 201240044 207,208 孔 210,211 孔結構 213晶片 215密封樹脂 300多晶片模組 303鍵合線 3 0 5阱結構 307 SMD元件 309焊接焊墊 312密封材料 401接腳 403孔結構 404,410阱結構 406,409 SMD 元件 414密封材料 813,814 孔 816,817孔結構 901,904,905,906 907,908孔結構 910阱結構 209阱結構 21 2金屬走線 214鍵合線 217晶片貼裝區域 302晶片貼裝區域 304接腳 306平面螺旋電感 308絕緣材料 310鍵合焊墊 402晶片貼裝區域 405,408平面螺旋電感 407金屬走線 815阱 818阱結構 金屬板 911〜914金屬 17201240044 6. Technical Field of the Invention The present invention relates to the field of packaging of multi-wafer modules, and more particularly to a package substrate with an insulator-filled well structure and a method thereof [Prior Art] A Multi Chip Module (MCM) includes a plurality of semiconductor wafers in one package, and the interconnection between the semiconductor wafers is completed by metal bonding wires and metal interconnection lines on the substrate. Generally, the substrate used in the package is a multilayer interconnection substrate, which can be fabricated by Low Temperature Co-fired Ceramic (LTCC) technology or multi-layer laminate substrate. L LGA (Land Grjd Array) The package is a semiconductor package commonly used in multi-wafer modules. It uses a multi-layer laminate substrate to make interconnect traces on the metal material layer; adjacent layers of different metal materials are separated by a layer of insulating material; The traces on the layer may be connected to each other by vias penetrating through the layer of insulating material. The metal interconnection of the lga substrate can be used to fabricate the RF inductive component and the surface mount component “Surface Mounted Device”. The RF circuit used in the wireless communication field needs to be matched by passive components such as inductors and capacitors. Network and filter network, usually can do single crystal # (4). In LGA package form can be achieved by bonding inductors, capacitors, etc. to achieve the purpose of package integration. See the 'RF power amplifier module and integrated with RF Most of the RF front-end module products of the line switch are packaged in LGA, = often to 4 layers, and there are 70 inductors, capacitors and even two-state temples. 201240044 As shown in Figure 1a, one layer is used. Schematic diagram of a multi-wafer module of a metal layer LGA package. As shown in the figure, a multi-wafer module) includes two wafers U1 and U2 adhered to a metal layer on its upper surface. The bonding wire 108 can be used. The corresponding wafer bonding pads on the wafers U1 and U2 are connected to each other, or the wafer bonding pads on the wafers U1 and U2 are connected to the corresponding pins 1〇7 on the LG A substrate, and ui and (The wafer bonding pad on J2 is connected to the corresponding substrate bonding pad on the upper surface of the LGA substrate. The wiring on the upper metal layer of the LGA substrate is made into a planar spiral structure, and the inductance component can be realized, as shown in Fig. 1a The planar spiral inductors are shown as 1〇1 and 102. Since the thickness of the metal layer in the |_GA package can reach tens or even hundreds of micrometers, the parasitic resistance of the planar spiral inductor produced is small, so that the inductance component is relatively small. The quality factor (Q value) of the direction is very significant for improving the performance of the RF circuit. As shown in Fig. a, the wafer bonding pads on the wafer U2 are connected to the planar spiral inductor 1 through the bonding wires 1〇8. One end of the 02; the other end of the planar spiral inductor 彳〇2 is connected to one end of the trace 1〇4 of the metal layer on the lower surface of the LG A substrate through the via hole 103; the other end of the trace 104 is connected to the |_ga module Pin 1 〇7, which realizes the electrical connection between the wafer bonding pad on the wafer U2 and the lGA module pin 1〇7. And on the upper surface of the 纟LGA substrate, the SMD component can also be adhered, as shown in Fig. 1a. 1 shown in 9. SMD components 1〇9 can usually be used for passive components such as resistors, inductors, diodes, etc., through the bonding wires 108 and the LGA substrate metal layer routing, SMD components 1〇9 can be easily connected to the module Inside the chip and module pins, it can be seen that the LGA package provides great flexibility for signal interconnects in multi-chip modules, especially in RF applications, which can integrate high-quality passives. Components (such as high 4 201240044 Q-value planar spiral inductors, SMD components, etc.), make RF multi-chip modules have higher performance. However, LGA package form also has some shortcomings. First of all, the manufacturing technology of the lGA substrate is very complicated, and it requires a series of materials such as lamination, drilling, filling of an electrically and thermally conductive material, lithographic etching of a metal layer, plating of metal, etc., so that the LGA package is expensive. Secondly, since the LG A substrate material is usually made of a tree-like material with poor thermal conductivity, heat dissipation of the wafer is also greatly limited in high-power applications. Moreover, usually the metal layer on the back side of the LGA needs to be traced, which destroys the integrity of the grounded metal pad on the back side or reduces the area of the grounded metal pad on the back side, which is not conducive to the adhesion of the semiconductor component of the LGA package on the peg. . The Quad Flat Non-丨eaded package (QFN) is a metal frame-based leadless package with a large exposed die pad (DAp 'Dje Attach Paddle) at the center of the package. effect. Using integrated passive components (丨pD, Integrated Passive Device) technology, the passive components such as inductors and capacitors required in the RF circuit are fabricated on a semiconductor wafer, so that a simpler RF power amplifier module can be realized on the QFN. Group, front-end module. Figure 1b shows a multi-chip module in a qfn package. The QFN package directly adheres to the semiconductor wafer on the metal frame (such as wafers U1, U2 and U3 as shown in Figure 1b), making the fabrication much simpler than the LGA package. However, compared to the LGA package form, the interconnect traces are not provided on the qFn metal frame, so that multiple wafers can only be interconnected by inter-wafer metal bond wires, which does not meet most multi-chip module design requirements. The technical solution proposed in U.S. Patent No. 7, 541, 141, to form a non-adjacent inter-connector interconnection by placing metal wires between the 201240044 QFN pins, also fails to solve the interconnection problem between the wafers. Moreover, in order to place such an interconnected metal wire, the grounded metal pad on the back side of the metal frame DAP is irregular in shape and the grounding area is reduced, and the regular back grounded metal pad is an important condition for ensuring the welding yield of the industrial production. In addition, the patent also proposes to adhere a capacitor S between the pins 'but in fact many capacitors need to be adhered between the chips or used in series with the inductive components', which does not meet this requirement. For RF power amplifier modules and RF front-end modules, the back metal needs to be directly grounded, and the largest possible back grounded metal pads are required to reduce the parasitic grounding inductance to provide good RF grounding to ensure the electrical performance of the chip. Will not deteriorate. The current wireless communication product design requires that the RF power amplifier module and the RF front-end module be as small as possible, and the power index is not reduced. Therefore, the largest possible back-grounded metal soldering is also beneficial to the heat dissipation of the module. SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to provide a package substrate with an insulator-filled structure and a manufacturing method thereof, to solve the problem that the multi-chip module substrate produced by the prior art is inflexible and has low RF inductance value. In order to solve the above technical problem, the present invention provides a package substrate with an insulator-filled I structure, characterized in that the package substrate has at least one body, and the card is filled with an insulating material to form a brown structure. And having a metal pattern on the upper surface of the well structure. Further, wherein the metal pattern is a metal trace directly connected to the 201240044 pin of the package substrate, an adhesive, a substrate bonding pad or a tin for mounting a semiconductor wafer; In the case where the metal trace is a single layer or a plurality of layers of metal with insulation to solve the above technical problems, the present invention also provides a package substrate manufacturer of the body filled well junction & At least one well is fabricated on the metal frame; the insulating material is filled in the solution to form a fat structure, and a metal pattern is formed on the upper surface of the well structure after the material is filled. Further, wherein 'the mask is processed on the upper and lower surfaces of the metal frame, and then at least one well is formed on the metal frame by etching or etching. Further, t, a metal pattern is formed by plating metal or depositing metal on the upper surface of the well structure after filling the insulating material. Progressively, wherein the metal pattern is further a metal trace directly connected to a pin of the package substrate, a solder pad of an adhesive surface adhesion component, a substrate bond pad or a solder ball solder of a reverse mounted semiconductor wafer The mat further wherein 'the metal pattern is covered by an insulating material. Further, wherein the metal trace is further a single layer or a plurality of metal traces. Compared with the prior art, the package substrate with the insulator-filled brown structure and the manufacturing method thereof have the problems of inflexible routing and low radio frequency inductance of the multi-chip module substrate produced by the prior art; Moreover, the manufacturing technology is simple, the price is cheap, and there is a complete large-area grounding pad, and the 201240044 has good heat dissipation performance, and provides a high-quality internal interconnection method. [Embodiment] The main idea of the present invention is to solve the existing multi-chip. The package substrate of the module is not flexible, and the RF inductance value is low. The present invention provides a multi-wafer die-package substrate and method which are simple in manufacturing technology, inexpensive, have a large-area grounding pad, and have good heat dissipation performance. The detailed description is not to be construed as limiting the invention. In order to realize a package substrate of a multi-chip module, as shown in FIGS. 2a to 2j, a first embodiment of the present invention provides a method for manufacturing a package substrate with an insulator-filled well-structured metal frame (WES, Well Embedded Substrate). The flow is as follows: (a) As shown in FIG. 2a, a metal plate 2〇1 having a suitable thickness may be taken, and the material thereof may be copper, aluminum, iron, copper alloy or nickel-iron alloy, and the upper and lower surfaces of the metal plate 201 are flat. Here, the material may be selected according to the actual application, and the present invention is not specifically limited. (b) Coating or adhering a mask for defining a pattern on the upper and lower surfaces of the metal plate 201, as shown in Fig. 2b, the upper surface mask 2〇2 and the lower surface mask 2〇3 〇(c) as shown in Fig. 2C It is shown that the masked metal plate 2〇1 is etched (or etched, etc.) and the wells 204, 205, 206 are etched downward from the upper surface of the metal plate 2〇1. Here, in the present invention, "well" means that the thickness of the portion which is etched on the metal plate and which is etched away is smaller than the thickness of the metal plate, and the definition of "well" can be understood with reference to Fig. 2c. From the above, the position of the well is defined by the upper surface mask 202 in step 8 201240044 2b. (d) A mask for defining a pattern, such as an upper surface mask 202 and a lower surface mask 203 as shown in Fig. 2d, is coated or adhered to the upper and lower surfaces of the metal plate 201 with the wells 204, 205, 206. (e) The metal plate 201 with the masks 204, 205, and 206 and the masked metal plate 201 is etched (or an equivalent technique such as etching), and is etched from the lower surface of the metal plate 2〇1. As can be seen from Fig. 2e, due to the corrosion in this step, the portions of the metal plates at the bottom of the original wells 205, 206 are rotted, resulting in holes 207 and 208 as shown in the figure & The thickness of 〇1, while well 204 remains unchanged. It should be noted here that in the present invention, it is necessary to distinguish the distinction between "hole" and "thro", and the difference can be more easily understood by referring to FIG. As shown in Fig. 2e, after this step, a WES package substrate pin 216 portion and a wafer mount region (DAP) 217 portion are formed on the metal plate 201. (1) The step shape m and the holes m and m are filled with an insulating material such as resin or plastic, and as shown in Fig. 2, a dirty package substrate having flat surfaces on both the upper and lower surfaces is obtained. After this step is completed, an I structure 209 and hole structures 21Q, 211 are formed on the WES package substrate. Here, in the present invention, the structure ', the insulating material is filled, and the formed 1 structure is composed of a bottom metal and an insulating material thereon. In the brown structure, there is a metal support around the insulating material, and the surrounding metal can be 曰The side wall of the structure may be completely surrounded. For example, in the 2nd 2f, the I structure 2〇9 shown by the broken line frame, the side wall is completely surrounded by the surrounding metal* and is implemented in another embodiment of the present invention. In the example, 1 & is partially surrounded by the surrounding metal. The side wall can be 201240044 (g) as shown in Fig. 2g 'on the upper surface of the well structure 209 of the above WES package substrate, using electroplated metal (or deposited metal) The method of the equivalent technique forms the metal trace 212. It should be noted here that the metal trace 212' formed in this step further includes a bonding pad (referred to as a substrate bonding pad) that can be used for metal wire bonding. ), can be used for bonding solder pads of SMD (Surface Mounted Devices) components, solder ball pads that can be used for flip-chip mounting of semiconductor wafers, etc.; and by adding a layer of deposited insulating dielectric The metal trace 212 fabricated on the well structure 209 may be a multilayer structure. (h) The above steps have completed the basic steps of manufacturing the Wes package substrate in the semiconductor package manufacturing based on the WES package substrate. In this step, the semiconductor wafer 213 is adhered to the upper surface of the wafer mounting region (DAP) 217 of the metal plate 2〇1 in the WES package substrate, and the Smd device is adhered to the solder pad formed on the well structure 209. Then, the metal wire is applied. The bonding industry uses the bonding wires 214 to complete the corresponding interconnection between the wafer bonding pads, the substrate bonding pads and the WES pins, as shown in the figure. (1) In order to complete the semiconductor components based on the WES package substrate The package is usually sealed with a sealing resin 215 or the like on the WES substrate of the above-mentioned wafer and SMD component adhesion and bonding industry, so that the upper surface of the S-inserted substrate, the wafer, the component, and the bonding wire are all Completely coated in the sealing material, that is, the metal pattern described in the Summary of the Invention is covered by the rim material. This completes the semiconductor component package based on the WES substrate, as shown in Figure 2i. As shown in Figures 3a to 3d, a multi-chip module of the WEs substrate package proposed by the present invention is used as a practical operation of the present invention - 201240044. A multi-chip module 300, The WES package substrate fabricated by the above manufacturing process is used, and the upper surface metal wafer mounting region 302 of the WES package substrate is bonded to the two semiconductor wafers U1 and U2. The wafer bonding pads on the two semiconductor wafers U1 and U2 The bonding wires 303 can also connect the wafer bonding pads on the two semiconductor wafers U1 and U2 to the corresponding WES package substrate pins 304 or the wafer mounting region 302. As shown in FIG. 3a, the DAP portion 302 and the pins 304 around it are made of a metal material, and the 308 and 305 indicated by the hatched portions are insulating materials, wherein the portion of the 305 indicated by the dashed box is a well structure, on the well structure 305. The surface 'made with the above technical steps, metal traces, as shown in FIG. 33, includes a planar spiral inductor 306, a solder pad 3〇9 of the adhesive SMD component 307 and its corresponding traces, and a bonding pad 31 of the substrate. Wait. Through the bonding wire 303, the planar spiral inductor 3〇6, the adhesive sMd device 3〇7 can be connected to the bonding pad 310 of the semiconductor wafer, the WES substrate pin 304, etc. to be interconnected, so that the bonding or bonding can be performed in the well. The components on the upper surface of structure 305 are connected to the circuit t. What needs to be explained here is 'metal traces made on the upper surface of the well structure 305 by electroplating or deposition, the thickness of which can usually be as high as several tens of micrometers or even higher, so that the parasitic resistance is small and the inductance Q is very large. Helps to improve the performance of multi-chip modules for RF applications. As shown in Fig. 3b, the back view of the multi-chip module 3〇〇, it can be seen that despite the metal traces made on the fat structure, the back surface of the wafer mounting area Xiao 3〇2 is still large-area and regular in shape. Its integrity is preserved by the use of traps and structures, which is also an object of the invention of the wes substrate proposed by the present invention. It should be noted that the grounding pad of the WES package substrate with a maximum surface area of 201240044 provides a good electrical grounding and thermal path for the semiconductor wafer, which is very helpful for improving the performance of the multi-chip module for RF applications. From the cross-sectional view (in the tangential direction of A_A) as shown in Fig. 3c, the relationship between the well structure 305 portion of the well structure and the metal plate, the WES package substrate pin 304, and the hole structure 308 in the thickness direction can also be seen. As shown in Fig., a cross-sectional view of the multi-wafer module after completion of the resin sealing (in the tangential direction of A_A), 312 is a sealing material. As described above, it can be seen that the multi-wafer die-bond package fabrication technology based on the WES package substrate is simple, and only the steps of the card structure definition and fabrication, the metal structure of the card structure are added, and the complexity is complicated in the Pu'er QFN package fabrication technology. Far less than LGA packaging technology. At the same time, because of the high Q (qua) metal traces, planar spiral inductors, multilayer interconnect structures, and viscous I SMD components on the upper surface of the card structure, there is greater interconnect flexibility compared to the (10) package and the WES package substrate The back grounded metal pads, which provide the largest area, provide good electrical grounding and thermal path for the semiconductor wafer. Therefore, the WES package substrate structure proposed by the invention has simple manufacturing technology, low price, complete large-area grounding pad, and good heat dissipation performance, and provides a high-quality internal interconnection method. Yes, in the above embodiment, (4) the package substrate has an independent (four) (four) 3 〇 5. In fact, the technical solution proposed in accordance with the present invention can be fabricated in a plurality of well structures on a WES package substrate as needed in a specific implementation. As shown in the second embodiment of the actual operation shown in FIG. 4a, the WES package substrate has two side structures, which are represented by independent dashed boxes, and Yang (shown by a broken line in the figure). The characteristic of 4 is that its side 12 201240044 is completely surrounded by the metal frame' and other patterns such as metal traces and SMD solder pads can be made on the flat upper surface, as shown in the figure, the planar spiral inductor 405, adhesive The solder pad 411 of the SMD component 406 and the substrate bonding pad 412. The well structure 41 is characterized in that its side wall is surrounded by the metal frame portion, and metal traces and SMD soldering can be formed on the flat upper surface thereof. Other patterns such as solder bumps, such as the planar spiral inductor 408 shown in FIG. 4a, the metal trace 407 connected to the WES package substrate pin 4〇1, the solder pad bonding the SMD component 409, and the substrate bonding pad. Figure 4b shows a rear view of the multi-wafer module 4'. It can be seen that despite the metal traces being formed on the well structures 404 and 410, the backside of the wafer-mounting region 402 is still large-area and regular in shape. As shown in & In the cross-sectional view (in the direction of Β·Β tangential direction), the relationship between the portion of the dashed frame 410 of the well structure and the wafer mounting region 4〇2, the hole structure 4〇3, and the pin 401 in the thickness direction can also be seen. Figure 4d is a cross-sectional view of the multi-wafer module after completion of the resin sealing (in the tangential direction of B_B), 414 is a sealing material. In addition, the embodiment of the present invention provides another metal structure with a well-filled well structure. (WES, We|| Embedded Substrate) The manufacturing method of the package substrate, as shown in FIGS. 5a to 5d, the specific steps of the method include: (a) coating a metal plate 8〇1 of a suitable thickness, the upper and lower surfaces are coated or adhered Masks 802, 803, and then carry out etching (money engraving). (b) Another piece of metal plate 8〇7 of appropriate thickness, coated or adhered to the upper and lower surfaces 808, 809, and then etched (etched (c) The etched two metal 13 201240044 plates obtained in the above steps (a) and (b) are spliced together, as shown in Fig. 5c, it can be seen that the steps form holes 813, 814 and wells 815. (d) Fill with insulating materials such as resin or plastic The well 815 and the holes 813, 814 formed in the above steps obtain the well structure 818 and the hole structures 816, 817. As can be seen in Figure 5d, the well structure 818 and the hole structures 816, 817 formed here are as shown in Figure 2h. The illustrated well structure 209 and the hole structures 210, 211 are equivalent. As shown in Figures 6a to 6c, for the above embodiment, another manufacturing process of the WES package substrate manufacturing method is: (a) a suitable thickness The metal plate 901 is coated or adhered to the upper and lower surfaces 902, 903' and then etched (touched). (b) The insulating metal material 9〇7, 9〇8, 909 is filled on the corroded metal plate to form a structure as shown in Fig. 6b. (c) depositing (or filling) a metal material on the portions of the metal plates 905, 904, and 906 to form portions 911, 912, 913, and 914, as shown in Fig. 6c. It can be seen that the well structure 91 formed here is The crucible and pore structures 907, 908 are equivalent to the well structure 209 and the pore structures 21 0, 211 as shown in Figure 2h. It should be noted that the manufacturing method and flow of the above WES package substrate are merely examples of forming a WES package substrate, and are not limited to the WES package substrate manufacturing method. Any method having the same technical effect as the above manufacturing process can be used to fabricate a WES package substrate, an insulating material filled well structure is formed on the WES package substrate, and metal traces are formed on the well structure. Since the well structure is embedded in the metal frame, the exposed ground metal pad portion on the back surface of the WES package substrate is not affected by the 201240044 manufacturing of the well structure, and a large area of exposed metal solder can still be maintained. As described above, 'the multi-chip module package manufacturing technology based on the WES package substrate can be seen to be simple'. In the conventional QFN package manufacturing technology, the steps of the clock structure and the manufacturing, the metal structure of the taste structure are added, and the complexity is far. Far less than LGA packaging technology. At the same time, because (4) the upper surface of the structure can be fabricated with high Q metal traces, planar spiral inductors, multilayer interconnect structures, and (4) SMD components, it has greater flexibility than QFN packages. And the 'WES package substrate provides a back-grounded metal pad with the largest area, providing a good electrical grounding and thermal path for the semiconductor wafer. Therefore, the WES package substrate structure proposed by the present invention has simple manufacturing technology, low cost, complete large-area grounding pad, and good heat dissipation performance, and provides a high-quality internal interconnection method. There are a variety of other embodiments that can be made by those skilled in the art without departing from the spirit and scope of the invention. And modifications are intended to fall within the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1a is a schematic diagram of a conventional multi-chip module using a 2-layer metal layer LGA package; FIG. 1b is a schematic view of a conventional multi-chip module using a QFN package. FIG. 2a to FIG. FIG. 3 is a front view of a package substrate with an insulator-filled fat junction 15 201240044 structure according to a second embodiment of the present invention; FIG. 3b is a schematic rear view of a package substrate with an insulator-filled card structure according to Embodiment 2 of the present invention; FIG. 3c is a view of the package substrate with an insulator-filled well structure according to Embodiment 2 of the present invention; 3a is a cross-sectional view of a tangential line a_a shown in FIG. 3b; FIG. 4a is a front view of a package substrate with an insulator-filled well structure according to Embodiment 3 of the present invention; FIG. 4b is a view of the third embodiment of the present invention with an insulator filling FIG. 4c is a cross-sectional view of the package substrate with an insulator-filled well structure along the tangent BB of FIGS. 4a and 4b according to the third embodiment of the present invention; Figure 4d is a publication rsn · 圃 of the package substrate with an insulator-filled well structure according to the third embodiment of the present invention, which is molded along the tangential line b_b shown in Figures 4a and 4b, and Figures 5a to 5d are implementations of the present invention. FIG. 6 is a schematic diagram showing a second manufacturing method of the package substrate with the insulator-filled well structure according to the fourth embodiment; FIG. 6a to FIG. 6c are the third embodiment of the package substrate with the insulator-filled structure according to the fifth embodiment of the present invention; A schematic diagram of a manufacturing method. [Main component symbol description] 1 00 multi-chip module 1 1,1 〇2 planar spiral inductor 103 via hole 104 trace 107 pin 109 SMD component 2〇1 metal plate 203 lower surface mask 108 bonding wire U1, U2 , U3 wafer 202 upper surface mask 204, 205, 206 well 16 201240044 207, 208 hole 210, 211 hole structure 213 wafer 215 sealing resin 300 multi-chip module 303 bonding wire 3 0 5 well structure 307 SMD component 309 soldering pad 312 sealing material 401 pin 403 Pore structure 404, 410 well structure 406, 409 SMD element 414 sealing material 813, 814 hole 816, 817 hole structure 901, 904, 905, 906 907, 908 hole structure 910 well structure 209 well structure 21 2 metal trace 214 bond wire 217 wafer mounting area 302 wafer mounting area 304 pin 306 plane Spiral Inductor 308 Insulation Material 310 Bonding Pad 402 Wafer Mounting Area 405, 408 Planar Spiral Inductor 407 Metal Trace 815 Well 818 Well Structure Metal Plate 911~914 Metal 17

Claims (1)

201240044 七、申請專利範圍： 1' 一種帶有絕緣體填充的阱結構的封裝基板，主要 係令一封裝基板具有至少一個阱，所述阱中填充有絕緣材 料形成阱結構，且所述阱結構的上表面上具有金屬圖形。 2、 如申請專利範圍第1項所述帶有絕緣體填充的阱 結構的封裝基板，所述金屬圖形為與所述封裝基板的接腳 直接相連的金屬走線、黏著表面黏著元件的焊接焊墊、基 板鍵合焊墊或倒扣安裝半導體晶片的錫球焊塾。 3、 如申請專利範圍第2項所述帶有絕緣體填充的阱 結構的封裝基板，所述金屬走線為單層或多層的金屬走線 4、 一種帶有絕緣體填充的味結構的封裝基板製造方 法，包括： 在金屬框架上製作至少一個牌； 在所述味中填充絕緣材料形成味結構，在填充完絕緣 材料後的所述阱結構的上表面製作金屬圖形。 5、 如申請專利範圍第4項所述帶有絕緣體填充的牌 結構的封裝基板製造方法，在金屬框架上下表面進行掩膜 處理’㈣再通過腐触或㈣在所述金屬框架上製作至少 一個阱。 6、如申請專利範圍第 結構的封裝基板製造方法， 結構的上表面通過電鍍金屬 5項所述帶有絕緣體填充的阱 在填充完絕緣材料後的所述阱 或沈積金屬方式製作金屬圖形 、如申請專利範圍第 6項所述帶有絕緣體填充的阱 201240044 結構的封裝基板製造方法，所述金屬圖形進一步為與所述 封裝基板的接腳直接相連的金屬走線、黏著表面黏著元件 的焊接焊墊、基板鍵合焊墊或倒扣安裝半導體 焊墊。 8、如申請專利範圍第6或7項所述帶有絕緣體填充 费畔。構的封裝基板製造方法，所述金屬圖形被絕材料 覆蓋。 ^ 如申请專利範圍第7項所述帶有絕緣體填充的阱 構的封裝基板製造方法，所述金屬走線進一步為單層或 多層的金屬走線。 八、圖式：（如次頁) 19201240044 VII. Patent Application Range: 1' A package substrate with an insulator-filled well structure, mainly comprising a package substrate having at least one well filled with an insulating material to form a well structure, and the well structure There is a metal pattern on the upper surface. 2. The package substrate with an insulator-filled well structure according to claim 1, wherein the metal pattern is a metal trace directly connected to a pin of the package substrate, and a solder pad of an adhesive surface adhesion component. , a substrate bonding pad or a solder ball solder bump mounted on a semiconductor wafer. 3. The package substrate with an insulator-filled well structure according to claim 2, wherein the metal trace is a single or multi-layer metal trace 4, and a package substrate with an insulator-filled odor structure The method comprises: fabricating at least one card on a metal frame; filling the odor with an insulating material to form a scent structure, and forming a metal pattern on an upper surface of the well structure after filling the insulating material. 5. A method of manufacturing a package substrate with an insulator-filled card structure according to claim 4, wherein a masking process is performed on the upper and lower surfaces of the metal frame. (4) at least one of the metal frames is formed by a corrosion contact or (4). trap. 6. The method of manufacturing a package substrate according to the structure of the patent application, wherein the upper surface of the structure is formed by electroplating a metal-filled well with a well-filled well to form a metal pattern, such as the well or deposited metal after filling the insulating material, such as The method for manufacturing a package substrate having the structure of the insulator-filled well 201240044 according to claim 6, wherein the metal pattern is further a metal trace or a bonding surface adhesive component directly connected to the pin of the package substrate. Pad, substrate bond pad or flip-chip mounting semiconductor pads. 8. If there is an insulation filling fee as described in item 6 or 7 of the patent application. A method of manufacturing a package substrate, the metal pattern being covered by a material. The method of manufacturing a package substrate with an insulator-filled well according to claim 7, wherein the metal trace is further a single layer or a plurality of metal traces. Eight, the pattern: (such as the next page) 19
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