JPH1140740A - Multi-chip module and manufacture thereof - Google Patents

Multi-chip module and manufacture thereof

Info

Publication number
JPH1140740A
JPH1140740A JP18946897A JP18946897A JPH1140740A JP H1140740 A JPH1140740 A JP H1140740A JP 18946897 A JP18946897 A JP 18946897A JP 18946897 A JP18946897 A JP 18946897A JP H1140740 A JPH1140740 A JP H1140740A
Authority
JP
Japan
Prior art keywords
insulating film
base substrate
chip
metal
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18946897A
Other languages
Japanese (ja)
Inventor
Kenji Sekine
健治 関根
Koji Yamada
宏治 山田
Matsuo Yamazaki
松夫 山▲崎▼
Osamu Kagaya
修 加賀谷
Kiichi Yamashita
喜市 山下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP18946897A priority Critical patent/JPH1140740A/en
Publication of JPH1140740A publication Critical patent/JPH1140740A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To allow signal input/output terminals and supply voltage supplying electrodes to be provided from the side of a base board, in order to minimize the lengths of leads when a multi-chip module is incorporated into a mother board or the like. SOLUTION: Such a groove as to put a portion of a base board (1) in relief so as to be an island is formed at a position where an electrode is formed in the base board. Then, insulating films 5 and 6 are formed so as to embed a bare chip 3 or a like that is mounted on the substrate, after which the base board is thinned while etched or ground from its reverse surface, thereby forming an island conductive portion isolated by the films 5 and 6. As a result, electrodes that are electrically isolated from a grounding conductor are formed on the reverse surface of the substrate.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、マルチチップモジ
ュールの構造およびその製造方法に関する。
The present invention relates to a structure of a multi-chip module and a method for manufacturing the same.

【0002】[0002]

【従来の技術】電子装置の小型化と高性能化の一手段と
して、ベア半導体チップと受動素子を複数個相互に接続
して一つのモジュールにする、いわゆるマルチチップモ
ジュールがある。
2. Description of the Related Art As one means for reducing the size and improving the performance of electronic devices, there is a so-called multi-chip module in which a plurality of bare semiconductor chips and passive elements are connected to each other to form one module.

【0003】従来のベア半導体チップの実装方法の一例
は、特開平3−155144 号に示されるように、ベア半導体
ICチップの厚さより所定分厚い絶縁フィルムに予めベ
ア半導体ICチップの外形形状より所定分大きい穴を形
成し、この絶縁フィルムを支持板に接着剤を介して貼り
合わせ、前記ベア半導体ICチップを接着剤を介して前
記貼り合わせ絶縁フィルムの穴部に接着し、ベア半導体
ICチップと絶縁フィルムの空隙およびベア半導体IC
チップの表面を絶縁フィルムと同種の液状樹脂で絶縁フ
ィルム層と高さが均一になるように塗布した後、熱硬化
し、ベア半導体ICチップ上の導体パッド部の上部の樹
脂をフォトリソグラフィー法で除去した後、全面に導体
膜を形成し、フォトリソグラフィー法で所定の導体配線
を形成している。
As an example of a conventional method for mounting a bare semiconductor chip, as shown in Japanese Patent Application Laid-Open No. 3-155144, an insulating film having a predetermined thickness larger than the thickness of the bare semiconductor IC chip is previously determined by a predetermined distance from the outer shape of the bare semiconductor IC chip. A large hole is formed, the insulating film is bonded to a support plate with an adhesive, and the bare semiconductor IC chip is bonded to the hole of the bonded insulating film with an adhesive, and is insulated from the bare semiconductor IC chip. Film gaps and bare semiconductor ICs
The surface of the chip is coated with a liquid resin of the same type as the insulating film so that the height of the insulating film layer and the insulating film are uniform, then heat-cured, and the resin on the conductor pad portion on the bare semiconductor IC chip is removed by photolithography. After the removal, a conductor film is formed on the entire surface, and a predetermined conductor wiring is formed by photolithography.

【0004】また従来の半導体装置(特にマルチチップ
モジュール)とその製造方法の一例は、特開平5−47856
号に示すように、パッケージに配設された少なくとも1
個のステージにチップをマウントし、前記パッケージと
チップに絶縁膜を塗着し、前記パッケージ上の接続パッ
ドと前記チップ上のパッドに導通するバイアホールを前
記絶縁膜に設け、前記バイアホール間を配線パターンに
よって接続するように構成している。
An example of a conventional semiconductor device (particularly a multi-chip module) and a method of manufacturing the same are disclosed in Japanese Patent Laid-Open No. 5-47856.
As shown in the number, at least one
A chip is mounted on each of the stages, an insulating film is applied to the package and the chip, and a via hole is formed in the insulating film to connect the connection pad on the package and the pad on the chip. It is configured to be connected by a wiring pattern.

【0005】[0005]

【発明が解決しようとする課題】前記特開平3−155144
号および特開平5−47856号では、支持板或いはパッケー
ジが絶縁基板でなっており、一般に絶縁基板の材料は導
電材料および半導体材料に比べ熱伝導率が1桁以上低い
ため、消費電力の大きい電力増幅器等の実装には不適で
ある。
Problems to be Solved by the Invention
In JP-A-5-47856 and JP-A-5-47856, a support plate or a package is an insulating substrate. Generally, the material of the insulating substrate has a heat conductivity lower by one order or more than that of a conductive material and a semiconductor material, and thus the power consumption is large. It is not suitable for mounting an amplifier or the like.

【0006】さらに、特開平5−47856号の実施例では、
チップ裏面のマウント用導体層(例えばAu−Si共晶
または導電性接着剤)と絶縁フィルム上の導体配線との
間に電気的接合がなく、高周波領域での回路動作に安定
性を欠く。
[0006] Further, in the embodiment of JP-A-5-47856,
There is no electrical connection between the mounting conductor layer (e.g., Au-Si eutectic or conductive adhesive) on the back surface of the chip and the conductor wiring on the insulating film, and the circuit operation lacks stability in a high frequency region.

【0007】さらに、特開平3−155144 号に示す従来の
ベア半導体チップの実装方法の一例では、ベア半導体I
Cチップと絶縁フィルム間の空隙およびベア半導体IC
チップの表面を絶縁フィルムと同種の液状樹脂で絶縁フ
ィルム層と高さが均一になるように塗布した後、熱硬化
する工程において、熱硬化時の液状樹脂の収縮によりベ
ア半導体ICチップと絶縁フィルム間の空隙部に窪みが
生じ易い。前記空隙部に窪みが生じると、前記空隙部の
導体配線にショートまたは断線等の不良を生じる。
Further, in an example of a conventional method for mounting a bare semiconductor chip disclosed in Japanese Patent Application Laid-Open No. 3-155144, a bare semiconductor I
Air gap between C chip and insulating film and bare semiconductor IC
After applying the surface of the chip with the same kind of liquid resin as the insulating film so that the height of the insulating film layer and the insulating film layer are uniform, in the step of thermosetting, the bare semiconductor IC chip and the insulating film are shrunk by the liquid resin during thermosetting. Depressions are likely to occur in the gaps between them. When a dent is formed in the gap, a defect such as a short circuit or disconnection occurs in the conductor wiring in the gap.

【0008】さらに、特開平5−47856号に示す半導体装
置とその製造方法の一例においても、液状樹脂の熱硬化
工程において、熱硬化時の液状樹脂の収縮によりパッケ
ージとチップ間の空隙部の絶縁膜に窪みが生じ易く、前
記空隙部の配線パターンにショートまたは断線等の不良
が生じ易い。
Further, in an example of a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 5-47856 and a method of manufacturing the same, in a thermosetting step of a liquid resin, insulation of a gap between a package and a chip is caused by contraction of the liquid resin during thermosetting. The film is likely to be dented, and the wiring pattern in the void is likely to be defective such as short circuit or disconnection.

【0009】さらに、従来例では、マルチチップモジュ
ール単位でキャップを装着することが可能な構造となっ
ていない。このため外部からのダメージに対して機械的
な保護がなされておらず破損し易い。さらに、高周波領
域で動作させる様な場合、電磁シールドが弱くなり他か
らの妨害を受け易くなる等の課題があった。
Further, the conventional example does not have a structure in which a cap can be mounted in a multichip module unit. For this reason, there is no mechanical protection against damage from the outside, and it is easily broken. Further, in the case of operating in a high frequency range, there is a problem that the electromagnetic shield is weakened and is easily susceptible to interference from others.

【0010】[0010]

【課題を解決するための手段】本発明は、上で述べた課
題を解決するため、半導体素子やICチップでなるベア
チップ部品及び金属性の導電ブロック等を搭載する金属
や半導体からなる平面状のベース基板と、その上に搭載
する電極上に金属性のバンプを持つ複数の半導体素子ま
たはICチップでなるベアチップ部品と、前記ベアチッ
プ部品を埋め込むように覆った樹脂状の第1絶縁膜とか
らなり、前記絶縁膜と前記ベアチップ上のバンプとが所
定の同じ高さに平坦化加工され、その上に金属層と絶縁
膜とによって多層配線パターンが形成され、前記バンプ
と前記パターンの一部とが電気的に接続されているマル
チチップモジュールにおいて、前記絶縁膜上の導体の一
部と前記ベース基板とが導電性のブロック又はスルーホ
ールにより接続される位置に予め前記ベース基板の一部
が島状に浮き出る様な溝を設け、前記ベアチップ部品や
金属性の導電ブロックを埋め込むように絶縁膜を形成し
た後、前記ベース基板を裏面よりエッチング又は研削に
より薄層化し、前記絶縁膜で隔離された島状の導体部分
を形成することによって、ベース基板の裏面にアース導
体と電気的に隔離された電極を形成できる。
SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a planar chip made of a metal or a semiconductor on which a bare chip component such as a semiconductor element or an IC chip and a metallic conductive block are mounted. It comprises a base substrate, a bare chip component comprising a plurality of semiconductor elements or IC chips having metal bumps on electrodes mounted thereon, and a resin-like first insulating film covered so as to embed the bare chip component. The insulating film and the bump on the bare chip are flattened to a predetermined height, and a multilayer wiring pattern is formed thereon by a metal layer and an insulating film, and the bump and a part of the pattern are formed. In a multichip module that is electrically connected, a part of a conductor on the insulating film and the base substrate are connected by a conductive block or through hole. At a predetermined position, a groove is formed so that a part of the base substrate protrudes in an island shape, and an insulating film is formed so as to embed the bare chip component and the metallic conductive block. Then, the base substrate is etched or ground from the back surface. By forming an island-shaped conductor portion separated by the insulating film, an electrode electrically isolated from the ground conductor can be formed on the back surface of the base substrate.

【0011】また、前記ベアチップ部品を搭載した面と
反対側の面の単位モジュールサイズに切り出した時に単
位モジュールの側面となる箇所に、予め深さが前記エッ
チング又は研磨により薄層化するときの削りしろより深
くした凹み部を設けておき、前記エッチング又は研削し
た後、単位モジュールサイズに切り出し、モジュールの
側面にできた凹みの部分にはめ込むように逆の凹みを持
った金属製のキャップを設ける。
[0011] In addition, a portion of the side opposite to the surface on which the bare chip component is mounted, which is to be a side surface of the unit module when cut out into a unit module size, has a shaving beforehand when the depth is reduced by the etching or polishing. After forming a concave portion deeper than the margin, after etching or grinding, cut out into a unit module size, and provide a metal cap having a reverse concave so as to fit into the concave portion formed on the side surface of the module.

【0012】[0012]

【発明の実施の形態】以下、本発明の実施例について詳
細に説明する。図1は本発明の実施例のマルチチップモ
ジュールの断面図である。図1では、金属や半導体から
なる平面状のベース基板1−1,1−2と、その上にチ
ップ搭載用の接着層2−1,2−2,2−3を設け、電
極上に金属性(例えばAuまたはAl等)のバンプ4を
持つ複数の半導体素子またはICチップでなるベアチッ
プ部品3と、金属性の導電ブロック11とを搭載し、前
記ベアチップ部品3および導電ブロック11を埋め込む
ように覆った樹脂状の第1絶縁膜5と、その上に金属層
にて形成した第1配線パターン8と第1配線パターン上
に形成したコンデンサ9とその上に金属層にて形成した
第2配線パターン10とさらに第2の絶縁膜6を挟んで
金属層にて形成した第3配線パターン7と全体を覆う金
属製のキャップ12で構成している。このマルチチップ
モジュールでは、信号の入出力端子や電源供給端子とな
る電極はベース基板の裏面に形成され導電ブロック11
により金属層にて形成した第3配線パターン7に接続さ
れる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 is a sectional view of a multichip module according to an embodiment of the present invention. In FIG. 1, planar base substrates 1-1 and 1-2 made of metal or semiconductor, and adhesive layers 2-1 2-2 and 2-3 for chip mounting are provided thereon, and metal A bare chip component 3 consisting of a plurality of semiconductor elements or IC chips having bumps 4 of a property (for example, Au or Al) and a metallic conductive block 11 are mounted, and the bare chip component 3 and the conductive block 11 are embedded therein. A resin-covered first insulating film 5, a first wiring pattern 8 formed on the first wiring pattern by a metal layer, a capacitor 9 formed on the first wiring pattern, and a second wiring formed on the first wiring pattern by a metal layer It comprises a pattern 10, a third wiring pattern 7 formed of a metal layer with a second insulating film 6 interposed therebetween, and a metal cap 12 covering the whole. In this multi-chip module, electrodes serving as signal input / output terminals and power supply terminals are formed on the back surface of the base substrate and are formed on the conductive block 11.
Is connected to the third wiring pattern 7 formed of a metal layer.

【0013】また、図2は本発明の実施例のマルチチッ
プモジュールを裏面から見た図である。図2においてベ
ース基板のアースとなる部分1−1と電極となる部分1
−2とは第1の絶縁膜5により電気的に隔離されてい
る。また、導電性のキャップ12は側面に設けられた凹
み13にはめ込まれて止まるように設けられている。
FIG. 2 is a view of the multichip module according to the embodiment of the present invention as viewed from the back. In FIG. 2, a portion 1-1 serving as a ground of the base substrate and a portion 1 serving as an electrode
−2 is electrically isolated by the first insulating film 5. Further, the conductive cap 12 is provided so as to be fitted and stopped in the recess 13 provided on the side surface.

【0014】図3は本発明の実施例のマルチチップモジ
ュールのベース基板の裏面をエッチング又は研削する前
の状態での断面を示す。ベース基板1を裏面からエッチ
ング又は研削により反対側にベース基板の一部が島状に
浮き出る様に設けた溝の厚さ(図中の点線で示した)の
所まで薄層化することにより第1の絶縁膜5により電極
部分1−2とアース導体部1−1に分離することができ
る。
FIG. 3 shows a cross section of the multichip module according to the embodiment of the present invention before the back surface of the base substrate is etched or ground. The base substrate 1 is thinned by etching or grinding from the back surface to the thickness of a groove (indicated by a dotted line in the figure) provided on the opposite side so that a part of the base substrate emerges in an island shape. The electrode part 1-2 and the ground conductor part 1-1 can be separated by the one insulating film 5.

【0015】図4は本発明のマルチチップモジュールの
他の断面であり、側面で導電性のキャップ12を止めて
いる部分を示す。ベース基板1のベアチップ部品を搭載
した面と反対側の面の単位モジュールサイズに切り出し
た時に単位モジュールの側面となる箇所に、予め深さが
前記エッチング又は研磨により薄層化するときの削りし
ろより深くした凹み部13を設けておき、前記エッチン
グ又は研削により図の点線で示した所まで薄層化し、単
位モジュールサイズに切り出した後、前記凹み13の部
分にはめ込むように逆の凹みを持った金属製のキャップ
12を設けた図である。
FIG. 4 is another cross section of the multichip module of the present invention, showing a portion where the conductive cap 12 is fixed on the side surface. A portion of the base substrate 1 on the side opposite to the surface on which the bare chip component is mounted, which is to be a side surface of the unit module when cut out into a unit module size, has a depth of shaving when previously thinning by etching or polishing. A deep recess 13 was provided, the layer was thinned by the above-mentioned etching or grinding to the point indicated by the dotted line in the figure, cut out to a unit module size, and then had a reverse recess so as to fit into the recess 13. FIG. 3 is a view in which a metal cap 12 is provided.

【0016】図5は本発明のマルチチップモジュールの
断面図であり、図3,図4に示した薄層化を行う点線の
箇所で切断した場合を示す。ベース基板1はアース導体
となる部分1−1と電極となる部分1−2に第1の絶縁
膜5により分離され、単位モジュールサイズ14に切り
出した時に単位モジュールの側面となる箇所に、導電性
のキャップを止める凹み部13を設けている。
FIG. 5 is a cross-sectional view of the multi-chip module of the present invention, showing a case where the multi-chip module is cut along a dotted line for thinning shown in FIGS. The base substrate 1 is separated by a first insulating film 5 into a portion 1-1 serving as a ground conductor and a portion 1-2 serving as an electrode. The concave portion 13 for stopping the cap is provided.

【0017】[0017]

【発明の効果】本発明によれば、平面状のベース基板に
電極上に金属性のバンプを持つ複数のベアチップ部品と
金属性の導電ブロックとを搭載し、これらを樹脂状の第
1絶縁膜で埋め込むように覆い、前記バンプと前記ブロ
ックと前記絶縁膜とを所定の同じ高さに平坦化加工し、
その上多層配線パターンを形成するマルチチップモジュ
ールにおいて前記ベース基板側から信号の入出力端子や
電源電圧を供給するための電極を設けることが可能とな
り、もってマルチチップモジュールをマザーボード等に
組み込むときのリード線部を極力短くでき高周波領域で
の特性を大幅に改善できる。
According to the present invention, a plurality of bare chip components having metal bumps on electrodes and a metal conductive block are mounted on a planar base substrate, and these are formed into a resin-like first insulating film. And cover the bump, the block, and the insulating film with a predetermined same height,
In addition, it is possible to provide a signal input / output terminal and an electrode for supplying a power supply voltage from the base substrate side in a multi-chip module for forming a multilayer wiring pattern. The line portion can be made as short as possible, and the characteristics in the high frequency range can be greatly improved.

【0018】また、本願では、マルチチップモジュール
を単位モジュールサイズに切り出した時に単位モジュー
ルの側面となる箇所に凹み部を形成可能とし、この凹み
部分を利用しモジュール全体を覆う導電性のキャップを
設けることを可能とした。このため外部からのダメージ
に対して機械的な保護がなされると共に、高周波領域で
動作させる様な場合、電磁シールド効果が強くなり他か
らの妨害を受け難くすることができる。
Further, in the present invention, it is possible to form a concave portion on a side surface of the unit module when the multi-chip module is cut into a unit module size, and to provide a conductive cap for covering the entire module using the concave portion. Made it possible. For this reason, mechanical protection is provided against external damage, and when the device is operated in a high-frequency region, the electromagnetic shielding effect is enhanced, and it is possible to reduce the possibility of interference from others.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例のマルチチップモジュールの
断面図。
FIG. 1 is a sectional view of a multichip module according to an embodiment of the present invention.

【図2】本発明の一実施例のマルチチップモジュールの
裏面の上面図。
FIG. 2 is a top view of the back surface of the multichip module according to one embodiment of the present invention.

【図3】本発明の一実施例のマルチチップモジュールの
製造途中の断面図。
FIG. 3 is a cross-sectional view of a multi-chip module according to an embodiment of the present invention in the course of manufacturing.

【図4】図3のマルチチップモジュールの他の位置の断
面図。
FIG. 4 is a sectional view of another position of the multi-chip module of FIG. 3;

【図5】図3のマルチチップモジュールの製造途中の他
の位置の断面図。
FIG. 5 is a sectional view of another position in the course of manufacturing the multi-chip module of FIG. 3;

【符号の説明】[Explanation of symbols]

1…ベース基板、2…接着層、3…ベアチップ、4…バ
ンプ、5…第1の絶縁膜、6…第2の絶縁膜、7…第3
配線パターン、8…第1配線パターン、9…コンデン
サ、10…第2配線パターン、12…キャップ、13…
凹み部、14…単位モジュール。
DESCRIPTION OF SYMBOLS 1 ... Base board, 2 ... Adhesive layer, 3 ... Bare chip, 4 ... Bump, 5 ... First insulating film, 6 ... Second insulating film, 7 ... Third
Wiring pattern, 8: first wiring pattern, 9: capacitor, 10: second wiring pattern, 12: cap, 13 ...
Depressed part, 14 ... Unit module.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 加賀谷 修 東京都国分寺市東恋ケ窪一丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 山下 喜市 東京都国分寺市東恋ケ窪一丁目280番地 株式会社日立製作所中央研究所内 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Osamu Kagaya 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. Inside the Central Research Laboratory

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】金属性のアース導体層を設けた金属や半導
体からなる平面状のベース基板と、その上に搭載する電
極上に金属性のバンプを持つ複数の半導体素子またはI
Cチップでなるベアチップ部品と、前記ベアチップ部品
を埋め込むように覆った樹脂状の第1絶縁膜とからな
り、前記絶縁膜と前記ベアチップ上のバンプとが所定の
同じ高さに平坦化加工され、その上に金属層と絶縁膜と
によって多層配線パターンが形成され、前記バンプと前
記パターンの一部とが電気的に接続されているマルチチ
ップモジュールにおいて前記絶縁膜上の導体の一部と前
記ベース基板とが導電性のブロック又はスルーホールに
より接続され、前記導電性ブロック又はスルーホールと
ベース基板とが接続される箇所が他のベース基板部と絶
縁膜により隔離されベース基板の一部が島状の電極を構
成した構造でなることを特徴とするマルチチップモジュ
ール。
A flat base substrate made of a metal or a semiconductor provided with a metal ground conductor layer, and a plurality of semiconductor elements or a plurality of semiconductor elements having metal bumps on electrodes mounted thereon.
A bare chip component comprising a C chip, and a resin-like first insulating film covering the bare chip component so as to be embedded therein, wherein the insulating film and the bump on the bare chip are flattened to a predetermined same height; In a multi-chip module in which a multilayer wiring pattern is formed by a metal layer and an insulating film on which a bump and a part of the pattern are electrically connected, a part of the conductor on the insulating film and the base The substrate is connected by a conductive block or through-hole, and a portion where the conductive block or through-hole is connected to the base substrate is isolated by another base substrate portion and an insulating film, and a part of the base substrate is in an island shape. A multi-chip module having a structure in which the electrodes are formed.
【請求項2】請求項1に記載のマルチチップモジュール
において、ベース基板の側面の一部に凹みを設け、前記
凹みをストッパーとして働く様に、前記マルチチップモ
ジュール全体を覆う金属製のキャップを設けたことを特
徴とするマルチチップモジュール。
2. The multi-chip module according to claim 1, wherein a recess is provided on a part of the side surface of the base substrate, and a metal cap is provided to cover the entire multi-chip module so that the recess serves as a stopper. A multi-chip module, characterized in that:
【請求項3】金属や半導体からなる平面状のベース基板
の片面に前記ベース基板の一部が島状に浮き出る様な溝
を設け、前記島状に浮き出た部分及び同じ面のその他の
部分に複数の半導体素子またはICチップでなるベアチ
ップ部品および導電性ブロックを導電材を用いて搭載
し、前記ベアチップ部品の各電極上に少なくとも前記ベ
アチップ部品の高さむら以上の高さでなる金属性のバン
プを設け、前記ベアチップ部品および前記バンプおよび
前記ブロックを埋め込むように樹脂状の第1絶縁膜で覆
い、前記バンプおよび前記ブロックおよび前記絶縁膜を
所定の同じ高さに平坦化加工し、その上に金属層と絶縁
膜とにて多層配線パターンを形成して、前記バンプおよ
び前記ブロックと前記パターンの一部とを電気的に接続
し、その後、前記ベース基板を裏面よりエッチング又は
研磨により薄層化することにより電極として前記絶縁膜
により隔離された島状の導体部分を形成してなることを
特徴とするマルチチップモジュール製造方法。
3. A flat base substrate made of a metal or a semiconductor is provided with a groove on one surface thereof so that a part of the base substrate is raised in an island shape, and the groove is formed in the island-shaped portion and other portions on the same surface. A metal bump having a height of at least the unevenness of the bare chip component on each electrode of the bare chip component by mounting a bare chip component and a conductive block including a plurality of semiconductor elements or IC chips using a conductive material. Is provided, and the bare chip component, the bumps, and the blocks are covered with a resin-like first insulating film so as to be embedded therein, and the bumps, the blocks, and the insulating films are flattened to a predetermined same height. A multilayer wiring pattern is formed by a metal layer and an insulating film, and the bumps and the blocks are electrically connected to a part of the pattern. Multichip module fabrication method characterized by comprising the forming an isolated island-like conductive portions by the insulating film as an electrode by thin layer by etching or polishing from the back surface of the scan board.
【請求項4】請求項3に記載のマルチチップモジュール
製造方法において、前記ベアチップ部品を搭載した面と
反対側の面の単位モジュールサイズに切り出した場合に
モジュールの側面となる位置に、予め深さが前記エッチ
ング又は研磨により薄層化するときの削りしろより深
く、かつベース基板の厚さより浅い複数の凹み部を設け
ておき、前記エッチング又は研削した後、単位モジュー
ルサイズに切り出し、ベース基板の側面にできた凹みを
ストッパーとして働く様に、前記マルチチップモジュー
ル全体を覆う金属製のキャップを設けてなることを特徴
とするマルチチップモジュール製造方法。
4. A method for manufacturing a multi-chip module according to claim 3, wherein a predetermined depth is set at a position which becomes a side surface of the module when cut out into a unit module size on a surface opposite to the surface on which the bare chip component is mounted. Is provided with a plurality of recesses deeper than the shaving margin when thinning by etching or polishing, and shallower than the thickness of the base substrate, and after the etching or grinding, cut out into a unit module size, and the side surface of the base substrate A method for manufacturing a multi-chip module, comprising: providing a metal cap that covers the entire multi-chip module so that the recess formed as a stopper functions as a stopper.
JP18946897A 1997-07-15 1997-07-15 Multi-chip module and manufacture thereof Pending JPH1140740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18946897A JPH1140740A (en) 1997-07-15 1997-07-15 Multi-chip module and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18946897A JPH1140740A (en) 1997-07-15 1997-07-15 Multi-chip module and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH1140740A true JPH1140740A (en) 1999-02-12

Family

ID=16241783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18946897A Pending JPH1140740A (en) 1997-07-15 1997-07-15 Multi-chip module and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH1140740A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012129822A1 (en) * 2011-03-31 2012-10-04 锐迪科创微电子(北京)有限公司 Packaging substrate with insulator-filled well structure and manufacturing method thereof
CN113791030A (en) * 2021-09-13 2021-12-14 国网山东省电力公司电力科学研究院 Soil corrosion in-situ detection sensor for buried metal component

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012129822A1 (en) * 2011-03-31 2012-10-04 锐迪科创微电子(北京)有限公司 Packaging substrate with insulator-filled well structure and manufacturing method thereof
CN113791030A (en) * 2021-09-13 2021-12-14 国网山东省电力公司电力科学研究院 Soil corrosion in-situ detection sensor for buried metal component
CN113791030B (en) * 2021-09-13 2024-05-31 国网山东省电力公司电力科学研究院 In-situ detection sensor for soil corrosion of buried metal component

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