JP2000252407A - Multichip module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multichip module which improves the reliability of a buried insulating layer by improving surface flatness of the layer. SOLUTION: A multichip module is provided with a conductive base substrate 10 having a plurality of recessed sections on one surface, at least one semiconductor chip 11 which is mounted in the recessed sections with its circuit forming surface upward, and a buried insulating layer 12 which is provided in the recessed sections to cover at least the above-mentioned one semiconductor element 11 and packed with a large quantity of filler. The filler packed in the insulating layer 12 has a diameter of <=30 μm. In addition, a first interlayer insulating layer 13 having a thickness of >=2.2 μm is formed on the insulating layer 12 and a thin film passive element is formed on the insulating layer 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip module, and more particularly to a technique effective when applied to a resin-embedded high-frequency multi-chip module.

[0002]

2. Description of the Related Art As one means for reducing the size and improving the performance of electronic devices, there is a so-called multi-chip module in which a plurality of bare semiconductor chips and passive elements are interconnected to form a single module. As an example of a conventional method for mounting a bare semiconductor chip, for example, a method described in Japanese Patent Application Laid-Open No. 3-155144 (hereinafter, referred to as Document 1) is known. The method described in this document 1
(1) First, a hole larger than the outer dimensions of the semiconductor IC chip by a predetermined amount is previously formed in an insulating film thicker by a predetermined thickness than the thickness of the semiconductor chip, and the insulating film is bonded to the support plate via an adhesive. (2) Next, the semiconductor chip is adhered to the hole of the bonded insulating film via an adhesive, and the gap between the semiconductor chip and the insulating film and the surface of the semiconductor chip are sealed with a liquid resin of the same kind as the insulating film. After being applied so that the layer and the height become uniform, it is thermally cured. (3) Next, after removing the resin on the pads of the semiconductor chip by photolithography, a conductor film is formed on the entire surface, and predetermined conductor wiring is formed by photolithography. An example of a conventional semiconductor device (particularly, a multi-chip module) and a method of manufacturing the same are disclosed in, for example, JP-A-5-4785.
A method described in Japanese Patent Publication No. 6 (hereinafter referred to as Document 2) is known. According to the method described in Document 2, (1) First, a semiconductor chip is mounted on at least one stage provided in a package, and an insulating film is applied to the package and the semiconductor chip. (2) Next, via holes are provided in the insulating film, which are electrically connected to the connection pads on the package and the pads on the chip, and the via holes are connected by a wiring pattern.

In a semiconductor device manufactured by the methods described in the above-mentioned Documents 1 and 2, a support plate or a package is formed of an insulating substrate. However, in general, the thermal conductivity of the material of the insulating substrate is lower by at least one order of magnitude than that of the conductive material and the semiconductor material. Therefore, in the semiconductor devices manufactured by the methods described in the above-mentioned Documents 1 and 2, the power consumption is low. However, there is a disadvantage that it is unsuitable for a power amplifier or the like having a large size. Further, in the method described in the above document 1, the gap between the bare semiconductor IC chip and the insulating film, and the surface of the semiconductor chip are made of the same kind of liquid resin as the insulating film so that the height of the insulating film layer is made uniform. After the application, in the step of thermosetting, the cavity is easily formed in the gap between the semiconductor chip and the insulating film due to the contraction of the liquid resin during thermosetting, and when the gap is formed in the gap, the conductor wiring in the gap is formed. There is a drawback that defects such as short-circuit or disconnection occur. Further, in a semiconductor device manufactured by the method described in Document 2, between a mounting conductor layer (for example, Au-Si eutectic or a conductive adhesive) on the back surface of a chip and conductor wiring on an insulating film. There is a drawback that there is no electrical connection and the circuit operation in a high frequency region lacks stability. Furthermore, in the method described in Document 2, in the thermosetting step of the liquid resin,
Due to the contraction of the liquid resin at the time of thermosetting, dents are apt to occur in the insulating film in the gap between the package and the chip, and the wiring pattern in the gap is liable to cause defects such as short-circuit or disconnection. There were challenges.

As a means for solving these drawbacks, for example, Yamada et al., “New structure of resin embedded type high frequency MCM and etching / press collective forming method”, Journal of Japan Institute of Electronics Packaging, Vol. 1, No. 4, PP294-300, (1998) (hereinafter,
Called Document 3. 2) is known. The mounting method described in Document 3 is as follows.
(1) A plurality of irregularities are provided in advance on a metal base substrate, a semiconductor chip is mounted in the concave portion, and then the semiconductor chip is covered with an insulating layer (buried insulating layer) made of resin so as to embed the semiconductor chip. The insulating layer and the bump electrode on the semiconductor chip are flattened by grinding or the like so as to have a predetermined height, and the thin film passive element and the wiring layer (metal layer) are formed thereon.
Are formed by a multilayer wiring technique. In the resin-embedded multi-chip module manufactured by the method described in Document 3, the electrode structure is a leadless electrode structure, so that the performance of the multi-chip module can be improved.

[0005]

However, in the method described in the above-mentioned reference (3), the inventors of the present invention have proposed a method of flattening the buried insulating layer so that the surface of the buried insulating layer is ground. It has been found that concave portions (hereinafter, voids) are generated, and this lowers the flatness of the surface of the buried insulating layer. Further, it is difficult to completely flatten the voids even by applying a thick interlayer insulating film layer in the next step. For this reason, in some cases, the voids of the thin film passive component formed on the interlayer insulating layer may be formed. There has been a problem in that damage or disconnection failure in the wiring layer may occur, which may reduce the reliability of the multi-chip module. The present invention has been made to solve the problems of the prior art, and an object of the present invention is to improve the flatness of the surface of a buried insulating layer and improve the reliability in a multichip module. It is to provide a technology that makes it possible. Another object of the present invention is to prevent a thin-film passive component formed on an interlayer insulating film or the like from being damaged or prevent a disconnection failure of a wiring layer and improve reliability in a multi-chip module. It is to provide a new technology. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, the present invention provides a base substrate having a plurality of recesses on one surface and having conductivity, and at least one semiconductor mounted in the plurality of recesses of the base substrate with a circuit formation surface facing upward. A multi-chip module comprising: a chip; and a buried insulating layer that covers the at least one semiconductor chip and is filled with a plurality of fillers provided in a plurality of recesses of the base substrate, wherein the buried insulating layer Characterized in that the diameter of the filler to be filled is 30 μm or less. According to another aspect of the present invention, there is provided a base substrate having a plurality of recesses on one surface and having conductivity, and at least one semiconductor mounted in the plurality of recesses of the base substrate with a circuit formation surface facing upward. A chip, covering the at least one semiconductor chip,
A buried insulating layer filled with a large number of fillers provided in a plurality of recesses of the base substrate, wherein a ratio of the filler filled in the buried insulating layer is 55% by volume to weight. ６５65%. Further, the present invention is characterized in that the semiconductor device further includes a first interlayer insulating layer formed on the buried insulating layer, and the thickness of the first interlayer insulating layer is 2.2 μm or more. According to another aspect of the present invention, there is provided a base substrate having a plurality of recesses on one surface and having conductivity, and at least one semiconductor mounted in the plurality of recesses of the base substrate with a circuit formation surface facing upward. A multi-chip module comprising: a chip; and a buried insulating layer provided in a plurality of recesses of the base substrate so as to cover the at least one semiconductor chip, wherein a dent amount of a surface of the buried insulating layer is zero. .5 μm or less. Further, according to the present invention, a plurality of recesses are provided on one side,
A base substrate having conductivity, at least one semiconductor chip mounted in a plurality of recesses of the base substrate with a circuit forming surface facing upward, and the base covering the at least one semiconductor chip; A multichip module having a buried insulating layer provided in a plurality of recesses of a substrate and a wiring layer formed on the buried insulating layer, wherein the thickness of the wiring layer is less than the surface of the buried insulating layer. It is characterized by being thicker than the maximum dent amount. According to another aspect of the present invention, there is provided a base substrate having a plurality of recesses on one surface and having conductivity, and at least one semiconductor mounted in the plurality of recesses of the base substrate with a circuit formation surface facing upward. A chip, covering the at least one semiconductor chip,
A multi-chip module comprising: a buried insulating layer provided in a plurality of recesses of the base substrate; and a first interlayer insulating layer formed on the buried insulating layer,
The surface of the first interlayer insulating layer has a dent amount of 0.5 μm or less. According to another aspect of the present invention, there is provided a base substrate having a plurality of recesses on one surface and having conductivity, and at least one semiconductor mounted in the plurality of recesses of the base substrate with a circuit formation surface facing upward. A multi-layer comprising a chip, a buried insulating layer provided in the plurality of recesses of the base substrate, covering the at least one semiconductor chip, and a first interlayer insulating layer formed on the buried insulating layer A chip module, wherein a thickness of the first interlayer insulating layer is larger than a maximum recess amount of a surface of the buried insulating layer. According to another aspect of the present invention, there is provided a base substrate having a plurality of recesses on one surface and having conductivity, and at least one semiconductor mounted in the plurality of recesses of the base substrate with a circuit formation surface facing upward. Chips and
A buried insulating layer provided in the plurality of recesses of the base substrate so as to cover the at least one semiconductor chip; a first interlayer insulating layer formed on the buried insulating layer; A multi-chip module having a wiring layer formed on a layer, wherein a thickness of the wiring layer is larger than a maximum recess amount of a surface of the insulating layer. Further, the present invention further includes a second interlayer insulating layer formed on the first interlayer insulating layer, wherein a thin film passive layer is provided on the first interlayer insulating layer and the second interlayer insulating layer. An element is formed.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted. [First Embodiment] FIG. 1 is a cross-sectional view of a principal part showing a basic structure of an example of a multichip module according to a first embodiment of the present invention. The multi-chip module according to the first embodiment is an embodiment in which the present invention is applied to a high-frequency circuit module. In the figure, 10 is a metal base, 11 is a semiconductor chip (bare IC chip), 12 is an insulating resin layer (hereinafter referred to as a buried insulating layer), 13 is a first interlayer insulating layer, and 14 is a second interlayer. Insulating layer, 15 is wiring layer, 1
6 is a resistor, 17 is a dielectric, 18 is an inductor, 19 is an island-shaped electrode post, 20 is an electrode post, and 22 is a grid-shaped partition. FIG. 2 is a diagram illustrating a method for manufacturing the multichip module according to the present embodiment. Less than,
A method for manufacturing the multi-chip module according to the present embodiment will be described with reference to FIG. First, as shown in FIG. 2A, island-shaped electrode posts 19, island-shaped electrode post separation grooves 21, electrode posts 20, and cross beams are formed in a metal substrate 30 by etching and pressing. Partition wall 22,
And the chip position marker 23 are collectively formed. Next, as shown in FIG. 2B, the semiconductor chip 11 is mounted face-up with the circuit formation surface (that is, the surface on which the pad electrode 24 is formed) facing up, and the semiconductor chip 11 is covered. The insulating resin 25 is thickly and collectively applied by a coater 26. Next, as shown in FIG. 2C, the buried insulating layer 12 on the surface side of the metal substrate 30 is formed by a first grinding process.
The electrode posts (19, 20) and the partition wall 22 are simultaneously ground to form a flat surface. In addition, the second grinding is performed until the buried insulating layer 12 in the separation groove 21 is exposed from the back surface side of the metal substrate 30. Thus, the metal base substrate 10 is formed.

Next, as shown in FIG. 2D, the first and second interlayer insulating layers (13, 14), the wiring layer 15, and the resistor 1 are formed on the surface of the substrate by photolithography.
6, the capacitor 17, and the inductor 18 are formed by a multilayer wiring technique. In the multi-chip module of the present embodiment, the electrode structure becomes a leadless electrode structure, and unnecessary inductance components can be reduced as in the case of wire bonding, so that the performance of the multi-chip module can be improved. The partition 22 provided around the module is intended to reinforce the warpage of the substrate, but also functions as a dam for the embedded insulating layer 12 and as an electromagnetic shield. The buried insulating layer 12 contains a filler (also referred to as a filler) in order to match the coefficient of thermal expansion, elastic modulus, and the like of the buried insulating layer 12 with the coefficient of thermal expansion, elastic modulus, and the like of the metal base substrate 10. .

In a conventional resin-embedded multi-chip module such as the multi-chip module of the present embodiment, the embedded insulating layer 12 contains a Si (silicon) filler having a diameter of 100 μm or less. Generally used Si fillers are formed into various sizes in the process of heating and melting a bulk material at 1800 ° C. and subcooling to room temperature. During this supercooling, cavities are formed in the Si filler, and the size depends on the filler diameter of the Si filler. Also, in a conventional resin-embedded multi-chip module, as shown in FIG.
The surface side of the metal substrate is ground and flattened.
As shown in FIG. 8, voids (voids) 31 having a diameter of 5 to 30 μm φ are formed on the surface of the buried insulating layer 12, which is a factor of reducing the flatness of the surface of the buried insulating layer 12. Hereinafter, the reason why voids 31 are formed on the surface of the buried insulating layer 12 during flattening by grinding will be described. FIG. 9 is a schematic diagram for explaining the reason why voids 31 are generated on the surface of the buried insulating layer 12 during planarization by grinding in a conventional resin-embedded multichip module. In FIG. 3A, reference numeral 33 denotes a Si filler in the buried insulating layer 12. The Si filler 33 has a cavity 34 formed during supercooling when the Si filler 33 is formed. Assuming that FIG.
Assuming that the line 35 in (a) is the ground surface of the grinding process,
As shown in FIG. 9B, during the grinding, a part of the Si filler 33 is deleted, and voids are generated on the surface of the buried insulating layer 12. Alternatively, as shown in FIG.
During the grinding process, the Si filler 33 is embedded in the insulating layer 1.
2, voids are generated on the surface of the buried insulating layer 12.

In a semiconductor device other than the conventional resin-embedded multi-chip module, the embedded insulating layer 12
Such voids did not pose a problem because it was not necessary to grind and flatten the surface. It is difficult to completely flatten the voids 31 generated on the surface of the buried insulating layer 12 even by applying a thick first interlayer insulating layer 13 in the next step. Therefore, FIG.
As shown in FIG. 0, in the conventional resin-embedded multi-chip module, an enlarged view is shown in the circle of FIG. 10, but due to the void 31, a thin-film passive component (for example, formed on the first interlayer insulating layer 13) 1, the resistor 16 and the capacitor 17) of FIG. 1, or a disconnection failure of the wiring layer 15 may occur, which is a major factor in lowering the reliability of the multi-chip module. In FIG. 10, 27
Is a via hole.

In the multi-chip module of the present embodiment, a small filler having a diameter of 30 μm or less and having no void is used as the Si filler contained in the buried insulating layer 12. As a result, even when voids 31 are formed on the surface of the buried insulating layer 12, the amount of depression of the surface of the first interlayer insulating layer 13 due to the voids 31 (distance d from the surface shown in FIG. 9C to the bottom surface of the void). Therefore, even if the wiring layer 15 and the capacitor 17 are formed on the first interlayer insulating film 13 by plating or vapor deposition, the capacitor 17 may be damaged, or the wiring layer 15 may be damaged. Disconnection failure can be prevented from occurring. For example, diameter 3
Using a buried insulating layer 12 containing a Si filler of 0 μm or less, the surface of the buried insulating layer 12 is
m of the first interlayer insulating layer 13, and
After the via hole 27 is formed by patterning, the dielectric layer 28 having a thickness of 0.3 μm and the wiring layer 15 having a thickness of 5 μm are formed on the surface of the buried insulating layer 12 by plating or vapor deposition. Disconnection failure of the wiring layer 15 and the dielectric layer 28 due to the void 31 does not occur.

In general, by making the first interlayer insulating layer 13 thicker than the maximum dent amount on the surface of the buried insulating layer 12, the thin film passive element (the thin film capacitor 17, the thin film resistor 1) is formed.
6, micro-shorting, disconnection failure, etc. of the inductor 18) or the wiring layer 15 can be prevented. Further, by making the film thickness of the wiring layer 15 larger than the maximum recess amount of the first interlayer insulating layer 13, it is possible to prevent a micro short circuit, a disconnection failure, and the like of the wiring layer 15. Note that the buried insulating layer 1 was not provided with the first interlayer insulating layer 13.
Even when the wiring layer 15 is formed on the wiring layer 2, by making the wiring layer 15 thicker than the maximum dent amount on the surface of the buried insulating layer 12, micro short-circuiting, disconnection failure, etc. of the wiring layer 15 can be prevented. Can be prevented.

FIG. 3 shows a first interlayer insulating film 1 having a thickness of 5 μm in the multichip module of the present embodiment.
FIG. 4 is a diagram illustrating an example of a wiring layer 15 formed on the wiring 3; In the case of this example, the depression due to the void 31 having a diameter of 30 μm or less contained in the buried insulating layer 12 is greatly improved by the application of the first interlayer insulating layer 13, and the surface of the first interlayer insulating layer 13 is reduced. The dent amount is 0.5 μm. On top of this,
By forming the wiring layer 15 having a thickness of 5 μm, defects such as disconnection can be prevented. FIG. 4 shows a first example of a multi-chip module having a thickness of
FIG. 3 is a diagram showing an example of a dielectric layer 27 formed on an interlayer insulating film 13 of FIG. In the case of this example, the buried insulating layer 1
The amount of depression of the surface on which the dielectric layer 28 is formed due to the voids 31 having a diameter of 30 μm or less contained in 2 is about 0.3 μm. A dielectric layer 27 having a thickness of about 0.3 μm is formed thereon by three-layer sputtering or the like, so that defects such as breakage can be prevented.

As described above, the amount of depression formed on the surface of the buried insulating layer 12, the thickness of the first interlayer insulating layer 13 on which the thin-film passive component or the wiring layer 15 is formed, and the thickness of the thin-film passive component or the wiring layer 15 By limiting the thickness, breakage of the thin-film passive component or disconnection of the wiring layer 15 can be prevented. FIG. 5 is a diagram showing a state where the multichip module of the present embodiment is mounted on motherboard 40. In addition, in FIG. 5, 41 is another module,
Reference numerals 42 to 46 denote electrodes formed on the motherboard 40. FIG. 6 is a graph showing the relationship between the void diameter on the surface of the buried insulating layer 12 and the first interlayer insulating film 13 according to the present embodiment. The allowable range shown in FIG. 6 is a region where the amount of dent on the surface of the buried insulating layer 12 can be flattened by the first interlayer insulating layer 13. The lower boundary line (arrow) indicates a thin film passive component such as the resistor 16, the dielectric 17, and the inductor 18, or a void diameter d on the first interlayer insulating layer 13 which is allowed to form the wiring layer 15. 0.5 μm
Is the upper limit. As can be seen from this graph, for example, when the wiring layer 15 having a thickness of 5 μm is formed on the first interlayer insulating layer 13 having a surface depression (void diameter) of 0.5 μm, the embedded insulating layer 12 and a film thickness of 2.
It is understood that if the first interlayer insulating layer 13 having a thickness of 2 μm or more is applied, the void diameter d of the void 31 generated on the surface of the buried layer insulating layer 12 can be tolerated up to 15 μm. The first
As the thickness of the interlayer insulating layer 13 is smaller, a via hole 27 with higher dimensional accuracy can be formed as the film thickness is smaller, and the coating amount is smaller and the process can be simplified, which is also effective in cost reduction.

FIG. 7 shows a buried insulating layer 1 according to this embodiment.
4 is a graph showing the relationship between the void diameter on No. 2 and the Si filler diameter contained in the buried insulating layer. The allowable range shown in FIG. 7 is based on the result of FIG. 6 by applying the first interlayer insulating layer 13 having a thickness of 2.2 μm when the void diameter on the surface of the buried insulating layer 12 is 0 to 15 μm. The allowable dent amount (void diameter) on the surface of the first interlayer insulating layer 13 is 0.5 μm.
m is shown as an area below m. From the graph of FIG. 7, it can be seen that in order to achieve a void diameter of 0 to 15 μm on the buried insulating layer 12, the Si filler contained in the buried insulating layer 12 requires a Si filler having a diameter of 30 μm or less. . The ratio of the Si filler contained in the buried insulating layer 12 is 55 to 65 by weight / volume ratio.
% Is desirable.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

[0017]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, as the filler to be filled in the buried insulating layer, a small-diameter filler having a diameter of 30 μm or less is used.
Thin-film passive elements (thin-film capacitors,
It is possible to prevent micro-shorts, disconnection defects, etc. of the wiring layer or thin-film resistors and inductors. (2) According to the present invention, the buried insulating layer or the first
Since the amount of dents on the surface of the first interlayer insulating layer is set to 0.5 μm or less, the thin film passive element (thin film capacitor, thin film resistor,
It is possible to prevent micro-shorts, disconnection defects, etc. of the wiring layer or the inductor). (3) According to the present invention, the buried insulating layer or the first
The thickness of the wiring layer formed on the first interlayer insulating layer is larger than the maximum recess amount of the surface of the embedded insulating layer or the first interlayer insulating layer. Micro shorts of the wiring layer formed on the top,
Disconnection failure and the like can be prevented. (4) According to the present invention, the reliability of the multi-chip module can be improved, and the cost of the resin-embedded multi-chip module can be reduced.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view showing a basic structure of an example of a multichip module according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining a method of manufacturing the multi-chip module shown in FIG.

FIG. 3 is a diagram illustrating an example of a wiring layer formed on a first interlayer insulating film having a thickness of 5 μm in the multichip module according to the embodiment of the present invention;

FIG. 4 is a diagram illustrating an example of a dielectric layer formed on a first interlayer insulating film having a thickness of 5 μm in the multichip module according to the embodiment of the present invention;

FIG. 5 is a diagram showing a state in which the multichip module according to the embodiment of the present invention is mounted on a motherboard.

FIG. 6 is a graph showing a relationship between a void diameter on a buried insulating layer and a first interlayer insulating film according to the embodiment of the present invention.

FIG. 7 is a graph showing the relationship between the diameter of a void on a buried insulating layer and the diameter of a Si filler contained in the buried insulating layer according to the embodiment of the present invention.

FIG. 8 is a view showing voids (voids) generated on the surface of a buried insulating layer in a conventional resin-embedded multichip module.

FIG. 9 is a schematic diagram for explaining the reason why voids are generated on the surface of a buried insulating layer during planarization by grinding in a conventional resin-embedded multichip module.

FIG. 10 is a view showing a conventional resin-embedded multi-chip module in which a wiring layer is disconnected due to a void generated on a surface of an embedded insulating layer.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Metal base, 11 ... Semiconductor chip (bare IC chip), 12 ... Insulating resin layer (henceforth a buried insulating layer), 13 ... 1st interlayer insulating layer, 14 ... 2nd interlayer insulating layer, 15 ... wiring layer, 16 ... resistor, 17 ... dielectric, 1
Reference Signs List 8: Inductor, 19: Island-shaped electrode post, 20: Electrode post, 21: Separation groove, 22: Cross-shaped partition, 23
... chip position marker, 24 ... pad electrode, 25 ... insulating resin, 26 ... coater, 27 ... via hole, 28 ... dielectric layer, 31 ... void (hole), 33 ... Si filler, 34
... cavity, 40 ... motherboard, 41 ... other modules,
42-46 ... electrodes.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kiyoshi Yamashita 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. Inside the Central Research Laboratory

Claims (10)

[Claims] 1. A base substrate having a plurality of recesses on one surface and having conductivity, and at least one semiconductor chip mounted in the plurality of recesses of the base substrate with a circuit formation surface facing upward. And a buried insulating layer that covers the at least one semiconductor chip and is filled with a number of fillers provided in the plurality of recesses of the base substrate, wherein the buried insulating layer has A multichip module, wherein the filler to be filled has a diameter of 30 μm or less. 2. A base substrate having a plurality of recesses on one surface and having conductivity, and at least one semiconductor chip mounted in the plurality of recesses of the base substrate with a circuit formation surface facing upward. And a buried insulating layer that covers the at least one semiconductor chip and is filled with a number of fillers provided in the plurality of recesses of the base substrate, wherein the buried insulating layer has A multi-chip module, wherein the ratio of the filler to be filled is in the range of 55 to 65% by volume and weight. 3. A first insulating layer formed on the buried insulating layer.
3. The multi-chip module according to claim 1, further comprising: an interlayer insulating layer, wherein the first interlayer insulating layer has a thickness of 2.2 μm or more. 4. And a second interlayer insulating layer formed on the first interlayer insulating layer, wherein the second interlayer insulating layer is formed on the first interlayer insulating layer.
The multi-chip module according to claim 3, wherein a thin-film passive element is formed. 5. A base substrate having a plurality of recesses on one surface and having conductivity, and at least one semiconductor chip mounted in the plurality of recesses of the base substrate with a circuit formation surface facing upward. And a buried insulating layer provided in the plurality of recesses of the base substrate so as to cover the at least one semiconductor chip, wherein the buried insulating layer has a dent amount on a surface thereof. 0.5 μm
A multichip module characterized by the following. 6. A base substrate having a plurality of recesses on one surface and having conductivity, and at least one semiconductor chip mounted in the plurality of recesses of the base substrate with a circuit formation surface facing upward. A multi-chip module comprising: a buried insulating layer provided in the plurality of recesses of the base substrate so as to cover the at least one semiconductor chip; and a wiring layer formed on the buried insulating layer. The multi-chip module according to claim 1, wherein the wiring layer has a thickness greater than a maximum recess amount of a surface of the buried insulating layer. 7. A base substrate having a plurality of recesses on one surface and having conductivity, and at least one semiconductor chip mounted in the plurality of recesses of the base substrate with a circuit forming surface facing upward. A multi-chip comprising: a buried insulating layer provided in the plurality of recesses of the base substrate so as to cover the at least one semiconductor chip; and a first interlayer insulating layer formed on the buried insulating layer A module, wherein the first interlayer insulating layer has a surface depression amount of 0.5 μm.
m or less. 8. A base substrate having a plurality of recesses on one side and having conductivity, and at least one semiconductor chip mounted in the plurality of recesses of the base substrate with a circuit formation surface facing upward. A multi-chip comprising: a buried insulating layer provided in the plurality of recesses of the base substrate so as to cover the at least one semiconductor chip; and a first interlayer insulating layer formed on the buried insulating layer A multi-chip module, wherein the first interlayer insulating layer has a thickness greater than a maximum recess amount of a surface of the buried insulating layer. 9. A base substrate having a plurality of recesses on one surface and having conductivity, and at least one semiconductor chip mounted in the plurality of recesses of the base substrate with a circuit formation surface facing upward. A buried insulating layer provided in the plurality of recesses of the base substrate so as to cover the at least one semiconductor chip; a first interlayer insulating layer formed on the buried insulating layer; And a wiring layer formed on said insulating layer, wherein said wiring layer has a thickness greater than a maximum recess amount of a surface of said insulating layer. And a second interlayer insulating layer formed on the first interlayer insulating layer, wherein the second interlayer insulating layer is formed on the first interlayer insulating layer and the second interlayer insulating layer.
The multi-chip module according to claim 7, wherein a thin-film passive element is formed.