CN217387150U - Semiconductor packaging structure - Google Patents
Semiconductor packaging structure Download PDFInfo
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- CN217387150U CN217387150U CN202222091385.XU CN202222091385U CN217387150U CN 217387150 U CN217387150 U CN 217387150U CN 202222091385 U CN202222091385 U CN 202222091385U CN 217387150 U CN217387150 U CN 217387150U
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Abstract
The utility model discloses a semiconductor packaging structure, it includes the base plate, embedded in the high density articulamentum of base plate and sets up in at least one chip on substrate surface, and the high density articulamentum includes multilayer metal wiring layer. The semiconductor packaging structure is a plurality of chip packaging structures and/or a single chip packaging structure. The utility model provides a semiconductor packaging structure, through the multilayer metal wiring layer of high density articulamentum, realize single chip packaging structure or a plurality of chip packaging structure, the multilayer metal wiring layer of high density articulamentum has thin line width and narrow interval, has reduced the mistake of wiring and assembly, reduces the installation degree of difficulty; meanwhile, the flexibility of substrate design is increased, and the difficulty degree of substrate typesetting and wiring is reduced.
Description
Technical Field
The utility model belongs to the technical field of the semiconductor package technique and specifically relates to a semiconductor package structure of interconnect structure of embedding base plate is related to.
Background
A System In a Package (SIP) is a Package form In which a plurality of chips are integrated into the same Package body, so that the SIP has more complete System functions, and has the advantages of miniaturization and high integration level. Currently, system-in-package is applied to handheld and wearable communication products, such as power management, radio frequency transceiver, radio frequency power amplifier, radio frequency switch, antenna tuner, bluetooth, etc. in smart phones.
The SIP includes a planar 2D package of a Multi-chip Module (MCM), a 3D package, and a package in which different components are built in a multifunctional substrate, such as an Embedded Multi-Die Interconnect Bridge (EMIB) package proposed by intel.
Currently, in implementing the SIP package structure with a multifunctional substrate, a silicon-based bridge chip is usually embedded in the substrate, and the bridge chip is used as an intermediary to interconnect a plurality of chips flip-chip mounted on the surface of the substrate. The bridge chip is typically made of aluminum.
However, in the multifunctional substrate, the silicon-based bridge chip needs to be fabricated by a foundry, which is complicated and costly, and thus leads to an increase in packaging cost.
Therefore, an interconnect structure with a simple structure and low cost is needed to realize chip interconnection.
In addition, in the flip chip package in the prior art, a chip with bump electrodes on a working surface faces downwards and is directly bonded with a package substrate, and the chip and the package substrate are interconnected through bumps arranged in an array on the chip. In general, a substrate is selected as a package substrate for flip chip packaging, and in order to meet the requirements of integration and high density packaging, one package body needs to be provided with more circuits and more pins, which requires more substrate layers to facilitate layout and design of circuits. However, the more the number of layers of the substrate, the more complicated the manufacturing process, which inevitably leads to an increase in cost.
Therefore, a chip package structure with a simple structure and low cost is also needed to reduce the number of layers of the substrate and reduce the cost.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome the defect that exists among the prior art, provide a simple structure and the not high semiconductor package structure who realizes the chip interconnection of cost.
In order to solve the technical problem, the utility model provides a semiconductor package structure, it includes the base plate, embedded in the high density articulamentum of base plate and set up in at least one chip on substrate surface, and the high density articulamentum includes multilayer metal wiring layer. The semiconductor packaging structure is a plurality of chip packaging structures and/or a single chip packaging structure.
In one aspect, the plurality of chip packaging structures are formed by inversely installing at least two horizontally adjacent chips on the surface of the substrate, and electrically connecting every two horizontally adjacent chips through a metal wiring layer of a high-density connecting layer.
On the other hand, the single chip packaging structure is formed by inversely installing a single chip on the surface of the substrate, and the single chip is electrically connected with the metal wiring layer of the high-density connecting layer.
In some embodiments, the substrate comprises at least one dielectric layer, line layers stacked on the upper and lower surfaces of the dielectric layer, and at least one pad layer, wherein adjacent line layers are electrically connected, and the line layers and the pad layers are electrically connected; the high-density connecting layer is embedded in the dielectric layer, and the metal wiring layer of the high-density connecting layer is electrically connected with the pad layer.
In some embodiments, a high-density connection layer is disposed on the metal layer, the metal layer is temporarily bonded to the substrate, and the high-density connection layer is attached to the dielectric layer of the substrate after debonding and removing the substrate and the metal layer.
In some embodiments, the high-density connection layer is disposed on a carrier substrate, which is attached to the dielectric layer of the base plate.
In some embodiments, the chip is provided with a plurality of conductive bumps, and parts of the conductive bumps are electrically connected with the outermost metal wiring layer of the multi-layer metal wiring layers.
In some embodiments, the metal wiring layer is made of copper as a conductive material, and the thickness of the copper is 1-15 μm. The metal wiring layer uses copper as a conductive material, and has better heat dissipation and charging performance compared with the bridge chip using aluminum as a conductive material.
In some embodiments, the semiconductor package structure further includes a heat spreader covering the chip and disposed on the substrate, and solder balls disposed on a back surface of the substrate. The substrate is also provided with a passive element.
In some embodiments, the carrier substrate is made of one of silicon, plastic, ABF.
In conclusion, the high-density connecting layer has small volume, high density and light weight, is embedded in the dielectric layer of the substrate, saves space and has simple integral structure; the thickness of the substrate can be reduced to allow the devices to be arranged in a more compact manner, thereby improving the integration and performance of the circuit. In addition, the high-density connecting layer can be manufactured by a packaging factory, so that the cost can be reduced.
And the utility model provides a plurality of chip package structure, through the multilayer metal wiring layer of high density articulamentum, realized the electricity between two adjacent chips of level and connect, compare with prior art, still have following beneficial effect:
the high-density connecting layer has high assembly density, is used for interconnecting two chips, has high reliability and is simple to mount;
the multilayer metal wiring layers of the high-density connection layer have fine line width and narrow space, so that wiring and assembly errors are reduced, and the installation difficulty is reduced; meanwhile, the flexibility of substrate design is increased, and the difficulty degree of substrate typesetting and wiring is reduced.
On the other hand, the utility model also provides a single chip package structure, single chip is connected with the metal wiring layer electricity of high density articulamentum to the flip-chip is adorned in the substrate surface, compares with prior art, still has following beneficial effect:
the multilayer metal wiring layers of the high-density connecting layer can replace a part of circuit layers of the substrate, and the circuit bearing capacity of the substrate is expanded.
Drawings
Fig. 1 is a schematic structural view of a high-density connection layer in embodiment 1 of the present invention;
fig. 2 is a schematic structural view of a high-density connection layer embedded in a dielectric layer of a substrate in embodiment 1 of the present invention;
fig. 3 is a schematic structural view of an embodiment of a high-density connection layer embedded substrate according to example 1 of the present invention;
fig. 4 is a schematic structural view of another embodiment of the high-density connection layer embedded substrate according to example 1 of the present invention;
fig. 5 is a schematic structural view of a high-density connection layer in embodiment 2 of the present invention;
fig. 6 is a schematic structural view of a dielectric layer of a substrate embedded with a high-density connection layer according to embodiment 2 of the present invention;
fig. 7 is a schematic structural view of an embodiment of a high-density connection layer embedded substrate according to example 2 of the present invention;
fig. 8 is a schematic structural view of another embodiment of the high-density connection layer embedded substrate according to example 2 of the present invention.
Detailed Description
The following description will further describe embodiments of the present invention with reference to the accompanying drawings and examples. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
The utility model provides a semiconductor packaging structure, it includes the base plate, embedded in the high density articulamentum of base plate and sets up in at least one chip on substrate surface, and the high density articulamentum includes multilayer metal wiring layer. The semiconductor packaging structure is a plurality of chip packaging structures and/or a single chip packaging structure, the plurality of chip packaging structures are formed by inversely arranging at least two horizontally adjacent chips on the surface of the substrate, and every two horizontally adjacent chips are electrically connected through a metal wiring layer of a high-density connecting layer. The single chip packaging structure is formed by inversely installing a single chip on the surface of the substrate, and the single chip is electrically connected with the metal wiring layer of the high-density connecting layer.
The invention is further illustrated by the following specific examples.
Example 1
The utility model discloses a semiconductor packaging structure is a plurality of chip packaging structure, and a plurality of chip packaging structure are at least two levels adjacent chip flip-chip in 2 surfaces of base plate, and two liang of levels adjacent chip realize the electricity through high density articulamentum 1's multilayer metal wiring layer 101 and connect.
The semiconductor packaging structure comprises a substrate 2, a high-density connecting layer 1 embedded in the substrate 2 and two chips arranged on the surface of the substrate, wherein the two chips are horizontally arranged on the surface of the substrate 2 adjacently, the high-density connecting layer 1 comprises a plurality of metal wiring layers 101, and the two chips are electrically connected through the metal wiring layers 101 of the high-density connecting layer 1.
The substrate 2 includes at least one dielectric layer, circuit layers stacked on the upper and lower surfaces of the dielectric layer, and at least one pad layer, wherein adjacent circuit layers are electrically connected, and the circuit layers are electrically connected to the pad layer. The electrical connection may be made by providing conductive vias between adjacent circuit layers, or may be other connection structures known to those skilled in the art. The high-density connection layer 1 is embedded in the dielectric layer, and the metal wiring layer 101 of the high-density connection layer 1 is electrically connected with the pad layer.
The high-density connection layer 1 in this embodiment is provided on the substrate 104. As shown in fig. 1-1 of fig. 1, in the high-density connection layer 1 of this embodiment, a temporary bonding layer 102 is first laid on a substrate 104, a metal layer 103 is sputtered on the surface of the temporary bonding layer 102, and the metal layer 103 is one or more of aluminum, titanium tungsten, and copper, so that laser can be blocked when laser is used for debonding, so as to prevent the metal wiring layer 101 in the high-density connection layer 1 from being damaged due to direct irradiation of laser on the high-density connection layer 1. In particular, the substrate 104 may be a wafer level substrate 104 similar to glass. Thereafter, as shown in 1-2 in fig. 1, the high-density connection layer 1 is disposed on the metal layer 103. Finally, as shown in fig. 1-3, the multiple high-density connection layers 1 are separated into single high-density connection layers 1 by using a dry (laser) or wet process and equipment, and the embedding arrangement is performed according to the design requirements of the substrate 2.
The high-density connection layer 1 comprises a metal wiring layer 101, and a plurality of metal wiring layers 101 are arranged on an insulating medium layer at intervals. An insulating film is provided between each two of the metal wiring layers 101. Coating photoresist on the insulating medium layer, forming a pattern opening by utilizing a photoetching process to form a patterned insulating medium layer, electroplating in the opening to form a metal wiring layer 101, and repeating the steps to form a plurality of layers of metal wiring layers 101. The high-density connecting layer 1 is simple in overall structure, can be directly completed by a packaging factory, and reduces manufacturing cost. In addition, the problem of warping caused by the fact that the thermal expansion coefficients of the silicon material and the substrate material are inconsistent in the prior art is solved. 2-8 metal wiring layers 101 can be prepared by using a Bumping process, and the wires can reach a narrow spacing of 1-20 μm, so that a high-density connection layer is formed.
As shown in fig. 2, the high-density connection layer 1 is attached to a dielectric layer 201 of the substrate 2. Firstly, the high-density connecting layer 1 is attached to the dielectric layer 201 of the substrate 2, then bonding is carried out, and the substrate 104 and the metal layer 103 are removed. The single high-density connecting layer 1 is small in size and light in weight, is embedded in the dielectric layer 201 of the substrate 2, saves space and is simple in overall structure; the single high-density connection layer 1 has high assembly density, is used for interconnection of two chips, and has high reliability and simple installation. The multilayer metal wiring layer 101 of the high-density connection layer 1 has a fine line width and a narrow pitch, which reduces errors in wiring and assembly and reduces difficulty in mounting.
Example 1 is further illustrated by the following specific embodiments, specifically according to whether a wiring layer is present at the position of the high-density interconnection layer 1 on the different dielectric layers 201 of the substrate 2, i.e., above the upper surface of the high-density interconnection layer 1 (the high-density interconnection layer 1 is attached to the surface of the dielectric layer 201 of the substrate 2).
Scheme 1
As shown in fig. 3, in the present embodiment, only one pad layer 3 is disposed above the upper surface of the high-density connection layer 1, and the wiring layer 7 is not disposed.
The two chips are a first chip 4 and a second chip 5 respectively, and the first chip 4 and the second chip 5 are horizontally and adjacently arranged on the substrate 2. The active surfaces of the first chip 4 and the second chip 5 are provided with a plurality of conductive bumps 6.
The substrate 2 includes a plurality of dielectric layers, the high-density connecting layer 1 is embedded in the first dielectric layer 2011, the first dielectric layer 2011 is provided with the pad layer 3, the pad layer 3 is arranged above the high-density connecting layer 1, and the pad layer 3 and the high-density connecting layer 1 are electrically connected through the first conductive via 8. The other circuit layer 7 is arranged below the high-density connecting layer 1.
In specific implementation, a part of the conductive bumps 6 on the first chip 4 and the second chip 5 is first connected to the pad layer 3, and the pad layer 3 is electrically connected to the outermost metal wiring layer 101 of the high-density connection layer 1 through the first conductive vias 8. To enable interconnection of the first chip 4 with the second chip 5 through the high-density connection layer 1.
Scheme 2
As shown in fig. 4, in the present embodiment, a circuit layer is disposed above the upper surface of the high-density connection layer 1, and a pad layer is disposed above the circuit layer.
The structure of the two chips, the connection structure of the substrate 2, and the like are the same as those disclosed in embodiment 1.
The substrate 2 includes a plurality of dielectric layers, the high-density connection layer 1 is embedded in the second dielectric layer 2012, the second dielectric layer 2012 is provided with a first line layer 70, the first dielectric layer 2011 above the first line layer 70 is provided with a pad layer 3, the pad layer 3 and the first line layer 70 are both arranged at the edges of the first dielectric layer 2011 and the second dielectric layer 2012, and the electrical connection is realized through the second conductive via 9. The first wiring layer 70 and the high-density connection layer 1 are electrically connected through the third conductive via 10. The other circuit layer 7 is arranged below the high-density connecting layer 1.
The first chip 4 and part of the conductive bumps 6 on the second chip 5 are connected with the pad layer 3 first, and the pad layer 3 is connected with the high-density connection layer 1 through the second conductive via 9 and the third conductive via 10, so that the first chip 4 is interconnected with the second chip 5 through the high-density connection layer 1.
The multiple chip package structures shown in schemes 1 and 2 can be applied to subsequent substrate design, which is the prior art and will not be described herein again.
Example 2
The utility model discloses a semiconductor package structure is single chip package structure, and this single chip package structure is single chip 12 and adorns in 2 surfaces of base plate for the upside-down mounting, and single chip 12 is connected with high density articulamentum 1's metal wiring layer 101 electricity.
As shown in fig. 5, the high-density connection layer 1 is disposed on a wafer-level carrier substrate 11, and the carrier substrate 11 may be one of silicon, plastic molding compound, and ABF. The carrier substrate 11 is then attached to the dielectric layer 201 of the base plate 2. The high-density connection layer 1 may be mounted at different positions of the dielectric layer 201 of the substrate 2.
As shown in fig. 6, the high-density connection layer 1 is embedded in the first dielectric layer 2011, the first dielectric layer 2011 is provided with the pad layer 3, the pad layer 3 is disposed above the high-density connection layer 1, and the pad layer 3 and the high-density connection layer 1 are electrically connected through the first conductive via 8. The other circuit layer 7 is arranged below the high-density connecting layer 1. Every two circuit layers 7 are electrically connected through a conductive through hole, and the pad layer 3 and the circuit layer 7 close to the pad layer are also electrically connected through the conductive through hole. The active surface of each single chip 12 is provided with a plurality of conductive bumps 6, a part of the conductive bumps 6 are connected with the pad layer 3, and the pad layer 3 is connected with the pad of the outermost metal wiring layer 101 of the high-density connection layer 1 through the first conductive via 8.
The flip-chip mounting of the individual chips 12 on the surface of the substrate 2 may be applied to a specific substrate design. As shown in fig. 7, for example, passive components 16 are attached to the rest of the surface of the substrate 2, and the chip or passive component is underfilled with epoxy or other filler, which can tightly bond the chip and substrate together and reduce the stress on the solder joints caused by the mismatch between the Coefficient of Thermal Expansion (CTE) of the chip and the substrate. Then, the heat sink 13 is attached; specifically, a heat conducting interface material 14 is coated on the surface of the chip 12, an adhesive material 15 is coated on the edge of the substrate 2, and then the heat sink 13 is attached to the surface of the substrate 2. The thermal interface material 14 can conduct heat emitted from the chip 12 to the heat sink 13, which helps to increase heat dissipation efficiency, and has certain viscosity, which plays a role in fixing the heat sink 13. Finally, the solder balls 17 are soldered to the back surface of the substrate 2, and the solder balls 17 are connected to the pads on the back surface of the substrate 2.
As shown in fig. 8, in the present embodiment, a circuit layer is disposed above the top surface of the high-density connection layer 1, and a pad layer is disposed above the circuit layer.
The respective structures of the chip 12 and the substrate 2 are the same as those disclosed in fig. 5 to 7.
The substrate 2 includes a plurality of dielectric layers, the high-density connection layer 1 is embedded in the second dielectric layer 2012, the second dielectric layer 2012 is provided with a first line layer 70, the first dielectric layer 2011 above the first line layer 70 is provided with a pad layer 3, the pad layer 3 and the first line layer 70 are both arranged at the edges of the first dielectric layer 2011 and the second dielectric layer 2012, and the electrical connection is realized through the second conductive via 9. The first wiring layer 70 and the high-density connection layer 1 are electrically connected through the third conductive via 10. The other circuit layer 7 is arranged below the high-density connecting layer 1.
Part of the conductive bumps 6 of the chip 12 are connected with the pad layer 3, and the pad layer 3 is connected with the high-density connection layer 1 through the second conductive vias 9 and the third conductive vias 10 to form a single chip package structure. Then, the single chip package structure is applied to a specific substrate design according to the scheme shown in fig. 7, and is not described herein again.
In specific implementation, a plurality of chip package structures in embodiment 1 and a single chip package structure in embodiment 2 may be used in combination, that is, two single chip package structures may be interconnected according to the structure in embodiment 1.
The embedded structure of 2 of high density articulamentum 1 and base plate is not limited to the technical scheme in this application embodiment 1, 2, and other do not break away from the utility model discloses the technical scheme who thinks about also should be regarded as the utility model discloses a protection scope.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of improvements and decorations can be made without departing from the technical principle of the present invention, and these improvements and decorations should also be regarded as the protection scope of the present invention.
Claims (9)
1. The semiconductor packaging structure is characterized by comprising a substrate, a high-density connecting layer embedded in the substrate and at least one chip arranged on the surface of the substrate, wherein the high-density connecting layer comprises a plurality of metal wiring layers; the semiconductor packaging structure is a plurality of chip packaging structures and/or a single chip packaging structure; the plurality of chip packaging structures are formed by inversely installing at least two horizontally adjacent chips on the surface of the substrate, and every two horizontally adjacent chips are electrically connected through a metal wiring layer of a high-density connecting layer; the single chip packaging structure is formed by inversely installing a single chip on the surface of the substrate, and the single chip is electrically connected with the metal wiring layer of the high-density connecting layer.
2. The semiconductor package structure of claim 1, wherein the substrate comprises at least one dielectric layer, a circuit layer stacked on the upper and lower surfaces of the dielectric layer, and at least one pad layer, wherein the circuit layer is electrically connected to the adjacent circuit layers, and the circuit layer is electrically connected to the pad layer; the high-density connecting layer is embedded in the dielectric layer, and the metal wiring layer of the high-density connecting layer is electrically connected with the pad layer.
3. The semiconductor package of claim 2, wherein the high-density connection layer is attached to a dielectric layer of the substrate.
4. The semiconductor package of claim 2, wherein the high-density connection layer is disposed on a carrier substrate, the carrier substrate being attached to the dielectric layer of the substrate.
5. The semiconductor package structure according to claim 3 or 4, wherein the chip is provided with a plurality of conductive bumps, and a part of the conductive bumps are electrically connected to an outermost metal wiring layer of the plurality of metal wiring layers.
6. The semiconductor package structure according to claim 5, wherein the metal wiring layer is made of copper as a conductive material, and the thickness of the copper is 1-15 μm.
7. The semiconductor package structure of claim 6, further comprising a heat spreader covering the chip and disposed on the substrate and solder balls disposed on a back surface of the substrate.
8. The semiconductor package structure of claim 7, wherein the substrate further comprises a passive component disposed thereon.
9. The semiconductor package structure of claim 4, wherein the carrier substrate is made of one of silicon, molding compound, ABF.
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| CN202222091385.XU CN217387150U (en) | 2022-08-10 | 2022-08-10 | Semiconductor packaging structure |
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| CN202222091385.XU CN217387150U (en) | 2022-08-10 | 2022-08-10 | Semiconductor packaging structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115274475A (en) * | 2022-09-27 | 2022-11-01 | 江苏芯德半导体科技有限公司 | Chip packaging method with high-density connecting layer and chip packaging structure thereof |
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2022
- 2022-08-10 CN CN202222091385.XU patent/CN217387150U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115274475A (en) * | 2022-09-27 | 2022-11-01 | 江苏芯德半导体科技有限公司 | Chip packaging method with high-density connecting layer and chip packaging structure thereof |
| CN115274475B (en) * | 2022-09-27 | 2022-12-16 | 江苏芯德半导体科技有限公司 | Chip packaging method with high-density connecting layer and chip packaging structure thereof |
| WO2024067275A1 (en) * | 2022-09-27 | 2024-04-04 | 江苏芯德半导体科技有限公司 | Packaging method for chip with high-density connecting layer, and packaging structure thereof |
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