JP2773762B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2773762B2 JP2773762B2 JP4261407A JP26140792A JP2773762B2 JP 2773762 B2 JP2773762 B2 JP 2773762B2 JP 4261407 A JP4261407 A JP 4261407A JP 26140792 A JP26140792 A JP 26140792A JP 2773762 B2 JP2773762 B2 JP 2773762B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor device
- bonding pad
- semiconductor element
- conductive material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/41—Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の製造方法
に関し、特にリードと半導体素子ボンディングパッドの
接続方法（ボンディング）に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of bonding a lead to a semiconductor element bonding pad (bonding).
【０００２】[0002]
【従来の技術】半導体装置のリードは、半導体装置の多
ピン化に伴い数が増加する為、半導体素子ボンディング
パッド（以後ボンディングパッドと記す）に近い位置ま
でリードを伸ばすと、リード先端付近では、隣りあった
リードが接触しやすくなる。そこでリードとリードの間
隔を取る為、ボンディングパッドに対するリード先端の
位置を後退させなければならず、従来のワイヤーボンデ
ィング方式では、ワイヤー長が長くなり、切れやすく、
接触もしやすくなる。そこで、図５に示す様に、絶縁性
フィルム１上にラミネートした導電箔をリード３とボン
ディングパッド５間の接続に必要なリード配線７だけが
残る様にエッチングされたＴＡＢを使って、あらかじめ
リード３とボンディングパッド５の上に作られたバンプ
６にＴＡＢのリード配線７を熱圧着することで、断線や
接触の少ない接続方法を得る様になった。2. Description of the Related Art Since the number of leads of a semiconductor device increases with the increase in the number of pins of the semiconductor device, if the lead is extended to a position close to a semiconductor element bonding pad (hereinafter referred to as a bonding pad), near the lead end, Adjacent leads can be easily contacted. Therefore, in order to increase the distance between the leads, the position of the leading end of the lead with respect to the bonding pad must be retracted.
It is easy to make contact. Therefore, as shown in FIG. 5, a conductive foil laminated on the insulating film 1 is pre-leaded by using TAB etched so that only the lead wiring 7 necessary for connection between the lead 3 and the bonding pad 5 remains. By thermocompression bonding the TAB lead wiring 7 to the bumps 6 formed on the bonding pads 3 and the bonding pads 5, a connection method with less disconnection and contact can be obtained.
【０００３】[0003]
【発明が解決しようとする課題】前述した従来のリード
とボンディングパッドの接続方法では、第１に、絶縁性
フィルムにリード配線を作っておき（ＴＡＢ）、その
後、リードとボンディングパッド上にバンプを形成し圧
着により接続する為、工程数が多く製造に時間がかか
る。第２に、リード配線と接続の安定性を考え、バンプ
はある程度の大きさが必要であり、バンプを形成するボ
ンディングパッド間の距離は、バンプの大きさを考慮し
なければならない。従ってパッド数の増大が難しい。第
３に、ＴＡＢのリード配線においてバンプとの接続する
部分は、リード配線のみで固定されておらず、バンプと
の接続までに曲がったり、隣のリード配線と接触する可
能性もあり、品質管理上問題がある。In the above-described conventional method for connecting a lead and a bonding pad, first, a lead wiring is formed on an insulating film (TAB), and then a bump is formed on the lead and the bonding pad. Since they are formed and connected by pressure bonding, the number of steps is large and the production takes time. Second, the bumps need to have a certain size in consideration of the stability of the lead wiring and the connection, and the distance between the bonding pads forming the bumps must take into account the size of the bumps. Therefore, it is difficult to increase the number of pads. Third, in the TAB lead wiring, the portion to be connected to the bump is not fixed only by the lead wiring, and may be bent by the connection to the bump or contact with the adjacent lead wiring. There is a problem.
【０００４】そこで、本発明の技術的課題は、上記欠点
に鑑み、製造時間を短縮した半導体装置の製造方法を提
供することにある。Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which the manufacturing time is reduced in view of the above-mentioned drawbacks.
【０００５】[0005]
【課題を解決するための手段】本発明によれば、絶縁性
フィルムをリードと半導体素子ボンディングパッドとの
間に配置して、導電性物質でラミネートし、次に所定の
リードと半導体素子ボンディングパッドとの間のみ、導
電性物質がリード配線として残る様にエッチングを行
い、リードと半導体素子パッドとが互いに電気的に接続
されることを特徴とする半導体装置の製造方法が得られ
る。According to the present invention, an insulating film is disposed between a lead and a semiconductor element bonding pad, laminated with a conductive material, and then provided with a predetermined lead and a semiconductor element bonding pad. Is performed so that the conductive material remains as the lead wiring only between the semiconductor device and the semiconductor element pad, and the lead and the semiconductor element pad are electrically connected to each other.
【０００６】即ち、本発明の半導体装置の製造方法は、
半導体装置のリードとボンディングパットの接続におい
て、絶縁性フィルムをリードとボンディングパッド間に
配置し、リード、絶縁性フィルム、半導体素子上を導電
性物質でラミネートし、次に任意のリードとボンディン
グパッド間のみ、導電性物質がリード配線として残る様
にエッチングを行い、リードとボンディングチップが電
気的に接続される製造方法となっている。That is, the method of manufacturing a semiconductor device according to the present invention comprises:
In connecting a lead and a bonding pad of a semiconductor device, an insulating film is arranged between the lead and the bonding pad, and the lead, the insulating film and the semiconductor element are laminated with a conductive material, and then, between any lead and the bonding pad. Only in such a manufacturing method, etching is performed so that the conductive material remains as lead wiring, and the lead and the bonding chip are electrically connected.
【０００７】[0007]
【実施例】次に本発明の実施例について図面を参照して
説明する。Next, an embodiment of the present invention will be described with reference to the drawings.
【０００８】図１は、本発明による半導体装置の平面図
である。図２は、本発明による半導体装置の要部断面図
である。図２に示すように、リード３と半導体素子４上
のボンディングパッド５に接触する形で、絶縁性フィル
ム１を配置し上から導電性物質２の膜で覆い、図１の様
に任意のリード３とボンディングパッド５が、導電性物
質２（リード配線）によって接続される様に不要な部分
の導電性物質膜をエッチングする。これにより、ＴＡＢ
の作製とリード３、ボンディングパッド５への接続を別
々に行わなくて済むので製造時間の短縮になり、バンプ
と接続する方法に比べ、リード３、ボンディングパッド
５との接続部のリード配線が曲がったり他のリード配線
と接触しにくい。又、図１に示すように、導電性物質２
のリード配線は、エッチングによりバンプの大きさより
微細なパターンを得られるので、ボンディングパッド５
の大きさを更に縮少でき、ボンディングパッド５の数を
増大させることが可能となる。FIG. 1 is a plan view of a semiconductor device according to the present invention. FIG. 2 is a sectional view of a main part of a semiconductor device according to the present invention. As shown in FIG. 2, an insulating film 1 is arranged in contact with a lead 3 and a bonding pad 5 on a semiconductor element 4 and covered with a conductive material 2 from above. An unnecessary portion of the conductive material film is etched so that 3 and the bonding pad 5 are connected by the conductive material 2 (lead wiring). Thereby, TAB
And the connection to the lead 3 and the bonding pad 5 need not be separately performed, so that the manufacturing time is shortened, and the lead wiring at the connection portion between the lead 3 and the bonding pad 5 is bent as compared with the method of connecting to the bump. Or contact with other lead wiring. Also, as shown in FIG.
In the lead wiring of (5), a pattern finer than the size of the bump can be obtained by etching.
Can be further reduced, and the number of bonding pads 5 can be increased.
【０００９】図３は、本発明による半導体装置の要部断
面図である。図４は、本発明による半導体装置の平面図
である。図３に示すように、リード３、絶縁性フィルム
１、半導体素子４の上部平面を同一の高さに設定、絶縁
性フィルム１とリード３、半導体素子４の端部は、密着
した状態にして実施例１と同様にリード３とボンディン
グパッド５の接続を行う。これにより、実施例１と同様
の効果が得られ、又、実施例１と比べ上部を覆う導電性
物質２の平坦性が向上し、リード３やボンディングパッ
ド５付近の断線がしにくくなる。FIG. 3 is a sectional view of a main part of a semiconductor device according to the present invention. FIG. 4 is a plan view of a semiconductor device according to the present invention. As shown in FIG. 3, the upper surfaces of the leads 3, the insulating film 1, and the semiconductor element 4 are set at the same height, and the ends of the insulating film 1, the lead 3, and the semiconductor element 4 are brought into close contact with each other. The connection between the lead 3 and the bonding pad 5 is performed in the same manner as in the first embodiment. Thus, the same effect as that of the first embodiment is obtained, and the flatness of the conductive material 2 covering the upper portion is improved as compared with the first embodiment, so that disconnection near the leads 3 and the bonding pads 5 becomes difficult.
【００１０】[0010]
【発明の効果】以上説明した様に本発明は、リードとボ
ンディングパッドの接続において、リードとボンディン
グパッドの間に絶縁性フィルムを置き、導電性物質膜を
一度に作り、その後エッチングすることで接続し、バン
プを使って接続する方法に比べ製造時間が短縮され、導
電性物質によるリード配線も微細なパターンが得られる
為、ボンディングパッドも、バンプ式に比べ縮少、数の
増大が可能となり、Ｉ／Ｏ数を多く得られる。又、リー
ド配線が曲がって接触することもなくなりより品質管理
上の問題点を１つ解決する。As described above, according to the present invention, in connecting a lead and a bonding pad, an insulating film is placed between the lead and the bonding pad, a conductive material film is formed at a time, and then the connection is performed by etching. However, compared to the method of connecting using bumps, the manufacturing time is shortened, and the fine pattern of the lead wiring made of conductive material can be obtained, so the number of bonding pads can be reduced and the number can be increased compared to the bump type. A large number of I / Os can be obtained. In addition, the lead wiring is prevented from being bent and contacted, thereby solving one problem in quality control.
【図１】本発明による半導体装置の平面図である。FIG. 1 is a plan view of a semiconductor device according to the present invention.
【図２】本発明による半導体装置の要部断面図である。FIG. 2 is a sectional view of a main part of a semiconductor device according to the present invention.
【図３】本発明による半導体装置の要部断面図である。FIG. 3 is a sectional view of a main part of a semiconductor device according to the present invention.
【図４】本発明による半導体装置の平面図である。FIG. 4 is a plan view of a semiconductor device according to the present invention.
【図５】従来方法による半導体装置のＴＡＢ接続断面図
である。FIG. 5 is a sectional view showing a conventional method of connecting a semiconductor device to a TAB.
１ 絶縁性フィルム ２ 導電性物質 ３ リード ４ 半導体素子 ５ ボンディングパッド ６ バンプ ７ リード配線 DESCRIPTION OF SYMBOLS 1 Insulating film 2 Conductive substance 3 Lead 4 Semiconductor element 5 Bonding pad 6 Bump 7 Lead wiring
Claims (1)
ンディングパッドとの間に配置して、導電性物質でラミ
ネートし、次に所定のリードと半導体素子ボンディング
パッドとの間のみ、導電性物質がリード配線として残る
ようにエッチングを行い、かつ、リードと半導体素子パ
ッドとが互いに電気的に接続されることを特徴とする半
導体装置の製造方法。An insulating film is disposed between a lead and a semiconductor element bonding pad, laminated with a conductive material, and then the conductive material is provided only between a predetermined lead and the semiconductor element bonding pad. A method of manufacturing a semiconductor device, wherein etching is performed so as to remain as wiring, and leads and semiconductor element pads are electrically connected to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4261407A JP2773762B2 (en) | 1992-09-30 | 1992-09-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4261407A JP2773762B2 (en) | 1992-09-30 | 1992-09-30 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06112279A JPH06112279A (en) | 1994-04-22 |
| JP2773762B2 true JP2773762B2 (en) | 1998-07-09 |
Family
ID=17361444
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4261407A Expired - Lifetime JP2773762B2 (en) | 1992-09-30 | 1992-09-30 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2773762B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9972559B2 (en) * | 2016-05-19 | 2018-05-15 | Hyundai Motor Company | Signal block and double-faced cooling power module using the same |
-
1992
- 1992-09-30 JP JP4261407A patent/JP2773762B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06112279A (en) | 1994-04-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6208021B1 (en) | Semiconductor device, manufacturing method thereof and aggregate type semiconductor device | |
| US5530282A (en) | Semiconductor device having a multilayer interconnection structure | |
| JP2002110898A (en) | Semiconductor device | |
| KR20070088050A (en) | Pad section of semiconductor device | |
| JP2000101016A (en) | Semiconductor integrated circuit device | |
| JPH079953B2 (en) | Method for manufacturing semiconductor device | |
| KR100813623B1 (en) | Flexible film semiconductor package and method for manufacturing the same | |
| JPS61274333A (en) | Semiconductor device | |
| JP2773762B2 (en) | Method for manufacturing semiconductor device | |
| JPH06204390A (en) | Semiconductor device | |
| KR100243376B1 (en) | Semiconductor package &manufacturing method thereof | |
| US6118173A (en) | Lead frame and a semiconductor device | |
| JPH0547836A (en) | Mounting structure of semiconductor device | |
| JP2747260B2 (en) | Ceramic composite lead frame and semiconductor device using the same | |
| JPH0777256B2 (en) | Resin-sealed semiconductor device | |
| JP2568057B2 (en) | Integrated circuit device | |
| JPH0719797B2 (en) | Semiconductor device mounting tool | |
| JPH1022329A (en) | Semiconductor device | |
| JP2583405B2 (en) | Lead frame for semiconductor device | |
| JPH08191129A (en) | Semiconductor device | |
| JP2005175260A (en) | Semiconductor device and manufacturing method thereof | |
| JP2008294318A (en) | Semiconductor device, and manufacturing method thereof | |
| JPH05166894A (en) | Semic0nductor integrated circuit and inspecting, probe card | |
| JPS60145656A (en) | Solid-state image pickup device and manufacture thereof | |
| JPH02156647A (en) | Tape carrier for tab |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980325 |