JP2583405B2 - Lead frame for semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame and, more particularly, to a lead frame for a semiconductor device which prevents a wire touch between metal wiring connecting a semiconductor chip and an inner lead during resin sealing.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been used in a wide range of fields including industrial equipment and consumer equipment as the degree of integration has been improved. For this reason, a semiconductor device having a package with a shape that is easy to use for each device such as miniaturization, thinning, and increase in the number of pins has been commercialized.

When configuring these packages,
A lead frame using a conductive material is used. The lead frame includes a method of punching a thin metal plate by a press to obtain a desired shape and a method of etching. A semiconductor chip is mounted on the island of the lead frame, and its electrodes and inner leads arranged around the island are electrically connected by wire bonding using a thin metal wire, and these are sealed with a resin. Or it is hermetically sealed.

However, with the increase in the number of pins, the number of thin metal wires to be connected increases, and the pitch of the thin wires becomes narrow. Therefore, there is a problem of edge touch for touching the corner between the thin metal wire and the corner of the semiconductor chip or wire touch between the thin metal wires. Had become.

[0005] An example of a lead frame with improved edge touch is described in Japanese Patent Application Laid-Open No. 59-181656. Referring to FIG. 3 which is a cross-sectional view of a semiconductor device in which the lead frame described in the publication is resin-sealed, a lead frame including a die pad 11 and a lead pin 12 has a semiconductor chip 13 on an upper surface of the die pad 11. Is installed.

The outer peripheral edge of the upper surface of the die pad 11 and the upper surface of the distal end of the inner lead 14 of the lead pin 12 are bonded to each other by bonding with an insulating film 15 disposed in a ring shape. The thickness of the insulating film 15 is formed to be at least larger than the thickness of the semiconductor chip 13.

[0007] The electrodes of the semiconductor chip 13 and the inner leads 14 corresponding to the electrodes are connected to each other across the insulating film 15 by bonding wires 16 and then sealed by a mold resin 17.

As described above, the bonding wire 16
Since the inner leads 14 and the electrodes of the semiconductor chip 13 are connected across the insulating film 15 which is thicker than the height of the semiconductor chip 13, the bonding wires 16 hang down and the corners of the semiconductor chip 13 and the die pad 11 It is devised not to touch the corner.

On the other hand, in another conventional example which is an extension of the above-mentioned conventional example, referring to FIG. 4 (a) showing a plan view and FIG.
A semiconductor chip 13 is mounted on 1, and electrodes 17 a, 17 b, and 17 c are arranged on the semiconductor chip 13 in a zigzag manner in three rows inward from the peripheral edge.

[0010] The inner leads corresponding to these three rows of electrodes are also three types of inner leads 14 whose tips are located at different distances from the edge of the semiconductor chip 13.
a, 14b, and 14c are provided, and insulating tapes 15a, 15b, and 15c having the same thickness are adhered to the upper surfaces of the respective tips. The inner lead 14a and the electrode 17a, the inner lead 14b and the electrode 17b, and the inner lead 14c and the electrode 17c are connected to each other across these insulating tapes.

With such an electrode arrangement, the effect is substantially the same as that obtained when the pitch between the electrodes is reduced, and the number of pins is increased.

[0012]

Problems to be Solved by the Invention
The lead frame of the conventional semiconductor device described in Japanese Patent No. 181656 has an effect of preventing edge touch, but the pitch between electrodes and the pitch between inner leads are narrowed to the limit with respect to a lead frame having a large number of pins. Although a margin for the upper space is ensured, it cannot be said that it is enough to avoid a risk of a wire touch at the time of resin sealing due to a loose metal wire.

[0013] On the other hand, in the case of another conventional example, it is possible to use a stiff metal wire due to the progress of wire bonding technology, and the danger of edge touch has been eliminated.
Touch between wires still exists. That is,
The distance between the electrode and the inner lead becomes longer,
The thin metal wire b is longer than 6a and the thin metal wire c is longer than the thin metal wire 16b. Therefore, when the fluid resin flows on the upper and lower surfaces of the lead frame when the semiconductor chip mounted on the lead frame is sealed with the resin, for example, the thin metal wire 16c may touch the thin metal wire 16b. In addition, all of these insulating tapes have the same thickness, so that the touch is further reduced. There has been a problem that an electrical short circuit occurs due to this wire touch, and the semiconductor device becomes defective.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described drawbacks, and to prevent a thin metal wire with slack from touching an adjacent metal wire by a resin flow at the time of resin sealing, thereby improving reliability. To provide a lead frame for a semiconductor device with high reliability.

[0015]

A feature of the lead frame for a semiconductor device according to the present invention is that it has an inner lead group disposed around a lead frame made of a conductive material and is mounted on a die pad of the lead frame. The electrode groups arranged in a staggered manner in a plurality of rows along the periphery of the semiconductor chip are connected to the corresponding inner lead group using thin metal wires having different lengths in each row, and in the plurality of rows. Correspondingly, in a semiconductor device lead frame in which at least one end upper surface of the lead group is bonded to one of a plurality of insulating tapes arranged so as to surround the die pad, the plurality of insulating tapes are An object of the present invention is to connect the inner lead groups with different thicknesses.

Further, the plurality of insulating tapes are stepwise so that a tape disposed at a position closest to the die pad is the thinnest and a tape disposed at a position farthest from the die pad is thickest. The tape thickness is changed.

Further, among the electrode groups arranged in a staggered manner in the plurality of rows, the electrode group in the row closest to the periphery of the semiconductor chip is the inner group for bonding the thinnest insulating tape to the upper surface of the tip. Selectively connected so as to be connected to the lead group, respectively, so that the electrode group in the row farthest from the periphery of the semiconductor chip is connected to the inner lead group that adheres the thickest insulating tape to the top surface of the tip. Wire bonding is performed.

Still further, the thickest insulating tape is set to one of a thickness equal to or higher than the height of the semiconductor chip, and the thickness of the remaining insulating tape is set according to the set value. Are also set stepwise lower.

[0019]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1A is a partial plan view of a first embodiment of a semiconductor device lead frame according to the present invention.
FIG. 2B is a partial cross-sectional view taken along a cutting line AA ′ of the semiconductor device lead frame shown in the plan view of FIG. 1. Both the plan view and the cross-sectional view show the lead frame 1.
Are shown, and other parts are repetitions of these states.

Referring to FIGS. 1 (a) and 1 (b), the difference from the conventional example is that a ring (in the drawing, the inner lead) is formed on the inner lead around the die pad on which the semiconductor chip is mounted. (Only a part is shown), and the thickness of the insulating tapes arranged in three rows is thicker as the insulating tapes are arranged outside.

That is, in this lead frame, the semiconductor chip 1 is mounted on the die pad 6, and the electrodes 2a, 2b, 2c are arranged on the semiconductor chip 1 in three rows inward from the peripheral edge. Are arranged.

The inner leads corresponding to these three rows of electrodes are arranged such that the tips of the inner leads are located at the shortest distance from the edge of the semiconductor chip 13.
And three types of inner leads located at different distances, such as a middle lead inner lead 4b located at a longer distance than the lead and a short lead inner lead 4c located at a longer distance than the lead. Leads are provided.

Further, an insulating tape 5a is adhered to the upper surface of the tip of the inner lead 4a, an insulating tape 5b is bonded to the upper surface of the tip of the inner lead 4b, and an insulating tape 5c is bonded to the upper surface of the tip of the inner lead 4b. ing.
The thin metal wire 3a is connected to the electrode 2a of the semiconductor chip 1 across the insulating tape 5a from the upper surface of the inner lead 4a outside the edge of the bonded insulating tape 5a. Similarly, the thin metal wire 3b is connected to the electrode 2b of the semiconductor chip 1 from the upper surface of the inner lead 4b across the insulating tape 5b, and the thin metal wire 3c is connected to the electrode 2b of the semiconductor chip 1 from the upper surface of the inner lead 4c. It is connected to the electrode 2c.

That is, in order to arrange the three types of insulating tapes on the inner leads, it is necessary to secure a space for bonding on the inner leads outside the edge of each insulating tape. The space between the insulating tapes needs to be large enough to avoid contact with the capillary during bonding in consideration of the above three types of thickness. As a result, at least the gap with the other insulating tape is widened, and as a result, the tip of the inner lead can be cut off at a point slightly protruding from the edge of the insulating tape. Is obtained.

Referring again to FIG. 1B, as described above, the thickness of the insulating tape 5a is the thinnest about 0.05 m.
m, the thickness of the insulating tape 5b is about 0.2
mm, and the thickness of the insulating tape 5c is larger than that of 5b and is about 0.1 mm.
It is arranged to be 4 mm and adhered.

Therefore, the metal wiring 3b straddling the thicker insulating tape 5b is wired relatively higher than the metal wiring 3a bridging the thinnest insulating tape 5a, and is further positioned relatively higher than the metal wiring 3b. Thick insulating tape 5
Metal wiring 3c straddling c is wired.

According to the present embodiment, since a difference in height is generated between the adjacent fine metal wires, a structure in which the wire touch due to the dripping of the fine metal wire is hardly generated.

Referring to FIG. 2, which shows a partial cross-sectional view of the semiconductor device lead frame of the second embodiment, the cross-sectional view also shows a part of the main part of the lead frame 1 in this case. Is a repetition of these states.

This embodiment is a modification of the first embodiment. The difference is that the thickness of the insulating tapes arranged in three rows is equal to or higher than the height of the semiconductor chips. That is.

That is, the thickness of the insulating tape 5a is set to be the same as the height of the semiconductor chip 1, the thickness of the insulating tape 5b is set to about 0.6 mm, and the thickness of the insulating tape 5c is set to about 1 mm. It is.

Further, since the thin metal wires 3a, 3b and 3c laid across the insulating tapes 5a, 5b and 5c which have been increased due to the increase in thickness become longer, the inner leads 4a, 4b and 4c so that the distance from the die pad 6 is as short as possible.
By extending the inner lead length toward the die pad 6 so as to provide a minimum space for the capillary to move up and down, deterioration of the electrical impedance characteristics is minimized.

In this embodiment, the insulating tapes 5a, 5a
Since the heights of b and 5c are equal to or greater than the height of the semiconductor chip 1, both wire touch and edge touch can be easily performed even when a thin metal wire having a lower rigidity than a normal thin metal wire is used. There are advantages that can be avoided.

In FIG. 1A of the first embodiment, the thickest insulating tape 5c disposed on the outermost side is at the same height as the semiconductor chip 1, and FIG. 2A of the second embodiment. Then, the thickest insulating tape 5c disposed on the outermost side
Has a thickness higher than that of the semiconductor chip 1, but is not limited thereto. The thickness may be lower than that of the semiconductor chip 1 if it is an ordinary thin metal wire, or may be higher. May be determined in consideration of the slack of the thin metal wire.

[0035]

As described above, in the lead frame for a semiconductor device of the present invention, a plurality of types of inner leads arranged around the lead frame are formed by an insulating tape having a different thickness for each type. The tape thickness is gradually adjusted so that the insulating tape disposed at the position closest to the die pad edge is the thinnest and the insulating tape disposed at the farthest position is the thickest. Since the arrangement is changed, it is possible to prevent the slack thin metal wire from touching the adjacent thin metal wire due to the resin flow at the time of resin sealing, and to provide a highly reliable semiconductor device lead frame. .

[Brief description of the drawings]

FIG. 1A is a plan view showing a main part of a first embodiment. FIG. 2B is a cross-sectional view taken along line AA ′ in FIG.

FIG. 2 is a sectional view showing a main part of a second embodiment.

FIG. 3 is a cross-sectional view showing a main part of a semiconductor device using a conventional lead frame.

FIG. 4A is a plan view showing a main part of another conventional example. (B) It is sectional drawing in the cutting line AA 'of said (a) figure.

[Explanation of symbols]

1,13 Semiconductor chips 2a, 2b, 2c, 17, 17a, 17b, 18c
Electrodes 3a, 3b, 3c, 16, 16a, 16b, 16c
Fine metal wires 4a, 4b, 4c, 14, 14a, 14b, 14c
Inner lead 5a, 5b, 5c, 15, 15a, 15b, 15c
Insulating tape 6,11 Die pad 12 Lead

Claims (4)

(57) [Claims] An inner lead group is disposed around a lead frame made of a conductive material, and is arranged in a plurality of rows in a staggered manner along a periphery of a semiconductor chip mounted on a die pad of the lead frame. The plurality of electrodes are connected to the corresponding inner lead group using thin metal wires having different lengths for each row, and a plurality of insulations arranged so as to surround the die pad corresponding to the plurality of rows. In a semiconductor device lead frame in which at least the top end of the lead group is bonded to one of the conductive tapes, the plurality of insulating tapes may have different thicknesses to connect the inner lead group. Characteristic lead frame for semiconductor device. 2. The method according to claim 1, wherein the plurality of insulating tapes are stepped so that a tape disposed closest to the die pad is thinnest and a tape disposed farthest away is thickest. 2. The lead frame for a semiconductor device according to claim 1, wherein said lead frame is provided with a different tape thickness. 3. The inner electrode group of the plurality of rows of electrodes arranged in a staggered manner, wherein the electrode group of the row closest to the periphery of the semiconductor chip adheres the thinnest insulating tape to the top surface of the tip. Selectively connected so as to be connected to the lead group, respectively, so that the electrode group in the row farthest from the periphery of the semiconductor chip is connected to the inner lead group that adheres the thickest insulating tape to the top surface of the tip. 2. The lead frame for a semiconductor device according to claim 1, wherein the lead frame is wire-bonded. 4. The thickest insulating tape is set to one of a thickness equal to or higher than the height of the semiconductor chip, and the thickness of the remaining insulating tape is also set according to the set value. 2. The lead frame for a semiconductor device according to claim 1, wherein each of the lead frames is set stepwise lower.