JP7081702B2 - Lead frames and semiconductor devices - Google Patents

Description

The present invention relates to lead frames and semiconductor devices.

In recent years, there has been a demand for miniaturization and thinning of semiconductor devices mounted on a substrate. In order to meet such demands, a so-called QFN is conventionally configured by using a lead frame, sealing a semiconductor element mounted on the mounting surface with a sealing resin, and exposing a part of the lead on the back surface side. Various (Quad Flat Non-lead) type semiconductor devices have been proposed.

However, in the case of a QFN having a conventional general structure, the package becomes larger as the number of terminals increases, so that there is a problem that it becomes difficult to secure mounting reliability. On the other hand, as a technique for realizing a multi-pin QFN, a package in which external terminals are arranged in two rows is being developed (see, for example, Patent Document 1). Such a package is also called a DR-QFN (Dual Row QFN) package.

Japanese Unexamined Patent Publication No. 2006-19767

In recent years, in producing a DR-QFN package, it has been required to increase the number of lead portions (number of pins) without changing the chip size. On the other hand, conventionally, a method of increasing the package size has been adopted in order to increase the number of pins. However, there is a limit to increasing the package size because there are restrictions on mounting the package on electronic devices.

The present invention has been made in consideration of such a point, and an object of the present invention is to provide a lead frame and a semiconductor device capable of increasing the number of terminals (number of pins) without increasing the package size. And.

The present invention is a lead frame, and includes a die pad on which a semiconductor element is mounted, a plurality of inner pad portions provided around the die pad, and a plurality of outer pad portions provided around the die pad. The inner pad portion is located closer to the die pad than the outer pad portion, and the plurality of inner pad portions are arranged at equal intervals with a first spacing from each other, and the plurality of outer pad portions are arranged at equal intervals. Is a lead frame characterized in that they are arranged at equal intervals with a second interval from each other, and the first interval is narrower than the second interval.

The present invention is a lead frame characterized in that the first spacing is 0.400 mm or more and 0.500 mm or less.

The present invention is a lead frame characterized in that the second interval is 0.500 mm or more and 0.600 mm or less.

In the present invention, a first internal terminal and a first external terminal are formed on the front surface and the back surface of each inner pad portion, and a second internal terminal and a second external terminal are formed on the front surface and the back surface of each outer pad portion, respectively. Is a lead frame characterized by being formed.

The present invention is a semiconductor device, and is mounted on the die pad, a plurality of inner pad portions provided around the die pad, a plurality of outer pad portions provided around the die pad, and the die pad. A semiconductor element, a connecting member that electrically connects the semiconductor element to the inner pad portion or the outer pad portion, the die pad, the plurality of inner pad portions, the plurality of outer pad portions, and the semiconductor. The element and the sealing resin for sealing the connecting member are provided, the inner pad portion is located closer to the die pad than the outer pad portion, and the plurality of inner pad portions are first to each other. The plurality of outer pad portions are arranged at equal intervals with a second spacing from each other, and the first spacing is narrower than the second spacing. It is a characteristic semiconductor device.

The present invention is a semiconductor device characterized in that the first interval is 0.400 mm or more and 0.500 mm or less.

The present invention is a semiconductor device characterized in that the second interval is 0.500 mm or more and 0.600 mm or less.

In the present invention, a first internal terminal and a first external terminal are formed on the front surface and the back surface of each inner pad portion, and a second internal terminal and a second external terminal are formed on the front surface and the back surface of each outer pad portion, respectively. Is a semiconductor device characterized by being formed.

According to the present invention, the total number (number of pins) of the inner pad portion and the outer pad portion can be increased.

FIG. 1 is a plan view showing a lead frame according to an embodiment of the present invention. FIG. 2 is a bottom view showing a lead frame according to an embodiment of the present invention. FIG. 3 is a cross-sectional view showing a lead frame according to an embodiment of the present invention (cross-sectional view taken along the line III-III of FIG. 1). FIG. 4 is a plan view showing a semiconductor device according to an embodiment of the present invention. FIG. 5 is a bottom view showing a semiconductor device according to an embodiment of the present invention. FIG. 6 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention (VI-VI line cross-sectional view of FIG. 4). 7 (a)-(e) are cross-sectional views showing a method of manufacturing a lead frame according to an embodiment of the present invention. 8 (a)-(e) are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 9 is a partially enlarged bottom view showing a lead frame according to a comparative example.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 8. In each of the following figures, the same parts are designated by the same reference numerals, and some detailed description may be omitted.

Configuration of Lead Frame First, the outline of the lead frame according to the present embodiment will be described with reference to FIGS. 1 to 3. 1 to 3 are diagrams showing lead frames according to the present embodiment.

As shown in FIG. 1, each lead frame 10 includes a unit lead frame 10a, which is a region corresponding to the semiconductor device 20 (described later). A support member 13 is interposed between the unit lead frames 10a, and the unit lead frames 10a are connected to each other by the support member 13. Although one unit lead frame 10a is shown in FIG. 1, in reality, a plurality of unit lead frames 10a are arranged vertically and horizontally in a matrix.

As shown in FIGS. 1 to 3, the lead frame 10 includes a planar rectangular die pad 11 and a plurality of first lead portions 12A and a plurality of second lead portions 12B provided around the die pad 11. There is. In FIG. 1, the region surrounded by the alternate long and short dash line corresponds to the unit lead frame 10a. In each unit lead frame 10a, one die pad 11 and a plurality of first lead portions 12A and a plurality of second lead portions 12B surrounding the die pad 11 are arranged.

The die pad 11 has a substantially square shape in a plane, and a semiconductor element 21 described later is mounted on the surface thereof. The length L1 of one side of the die pad 11 can be, for example, 1.0 mm or more and 6.5 mm or less. In the present embodiment, the planar shape of the die pad 11 is square, but the die pad 11 is not limited to this and may be rectangular. Further, suspension leads 14 are connected to the four corners of the die pad 11, and the die pad 11 is connected and supported by the support member 13 via the four suspension leads 14. Each suspension lead 14 is tilted at an angle of 45 ° on a plane with respect to the side of the die pad 11. The back surface of the hanging lead 14 is thinned by half etching. In the present specification, the "front surface" refers to the surface on the side on which the semiconductor element 21 is mounted, and the "back surface" refers to the surface on the side connected to an external mounting board (not shown). Further, half-etching means etching the material to be etched halfway in the thickness direction thereof. The thickness of the material to be etched after half-etching is, for example, 30% or more and 70% or less, preferably 40% or more and 60% or less of the thickness of the material to be etched before half-etching.

In the present embodiment, the central portion of the die pad 11 is not half-etched and has a thickness equivalent to that of the metal substrate before processing. Specifically, the thickness of the central portion of the die pad 11 can be 0.05 mm or more and 0.5 mm or less, although it depends on the configuration of the semiconductor device 20. The peripheral portion 11a of the die pad 11 is thinned over the entire circumference by half-etching. Further, a plurality of through grooves 11b are formed in the peripheral edge portion 11a along each side of the die pad 11. By providing the through groove 11b, the adhesion between the die pad 11 and the sealing resin 23 (described later) can be improved.

Further, each first lead portion 12A and each second lead portion 12B are connected to the semiconductor element 21 via a bonding wire 22 as described later, and are arranged between the first lead portion 12A and the die pad 11 via a space. ing. Each of the first lead portions 12A and each second lead portion 12B extends from the support member 13 along either the X direction or the Y direction, and each first lead portion 12A extends from each of the second lead portions 12B. It is configured longer than. Here, the X direction and the Y direction are two directions parallel to each side of the die pad 11 in the plane of the lead frame 10, and the X direction and the Y direction are orthogonal to each other. Further, the Z direction is a direction perpendicular to both the X direction and the Y direction.

The first lead portions 12A and the second lead portions 12B are alternately arranged along the periphery of the die pad 11. The adjacent first lead portions 12A and second lead portions 12B have a shape that is electrically insulated from each other after the semiconductor device 20 (described later) is manufactured. Further, the first lead portion 12A and the second lead portion 12B have a shape that is electrically insulated from the die pad 11 after the semiconductor device 20 is manufactured. Of these, the first lead portion 12A has an inner pad portion (terminal portion) 53, and the second lead portion 12B has an outer pad portion (terminal portion) 63. External terminals 17A and 17B electrically connected to an external mounting board (not shown) are formed on the back surfaces of the inner pad portion 53 and the outer pad portion 63, respectively. Each of the external terminals 17A and 17B is exposed to the outside from the semiconductor device 20 after the semiconductor device 20 (described later) is manufactured.

In this case, the plurality of inner pad portions 53 and the plurality of outer pad portions 63 are arranged substantially alternately around the die pad 11. Further, the inner pad portion 53 and the outer pad portion 63 are arranged in two rows when viewed from a plane. That is, the plurality of inner pad portions 53 and the plurality of outer pad portions 63 are arranged on different straight lines, and the straight line in which the plurality of inner pad portions 53 are arranged and the straight line in which the plurality of outer pad portions 63 are arranged are different. Parallel to each other. Further, around the die pad 11, relatively long first lead portions 12A and relatively short second lead portions 12B are alternately arranged over the entire circumference. As a result, the problem that the inner pad portion 53 of the first lead portion 12A and the outer pad portion 63 of the second lead portion 12B are short-circuited to the adjacent first lead portion 12A and the second lead portion 12B is prevented.

Next, the configurations of the first lead portion 12A and the second lead portion 12B will be further described with reference to FIGS. 1 to 3.

As shown in FIGS. 1 to 3, the relatively long first lead portion 12A has a connection lead 52 having a relatively narrow width and the above-mentioned inner pad portion 53 having a relatively wide width. ing. An internal terminal (first internal terminal) 15A is formed on the surface of the inner pad portion 53. The internal terminal 15A is a region electrically connected to the semiconductor element 21 via the bonding wire 22 as described later. A plated portion for improving the adhesion to the bonding wire 22 may be provided on the internal terminal 15A. Further, the above-mentioned external terminal (first external terminal) 17A is formed on the back surface of the inner pad portion 53.

The connection lead 52 is located on the outer side (support member 13 side) of the inner pad portion 53, and its outer end portion is connected to the support member 13. A part of the connection leads 52 is composed of only a straight portion 57 extending perpendicularly to the support member 13 to which the connection leads 52 are connected. Further, some of the other connection leads 52 are composed of a straight line portion 57 connected to the support member 13 and an inclined portion 58 connected to the straight line portion 57 and extending in an inclined manner with respect to the straight line portion 57.

As shown in FIG. 3, the connection leads 52 of the first lead portion 12A are each formed thinly from the back surface side by half etching. On the other hand, the inner pad portion 53 has the same thickness as the die pad 11 and the support member 13 without being half-etched.
As described above, since the thickness of the connection lead 52 is thinner than the thickness of the inner pad portion 53, the narrow first lead portion 12A can be formed with high accuracy, and the semiconductor device 20 which is small and has a large number of pins can be formed. Obtainable.

Each inner pad portion 53 is located closer to the die pad 11 than each outer pad portion 63. Further, the plurality of inner pad portions 53 have the same planar shape as each other. Specifically, the inner pad portion 53 has a shape in which a semicircular portion on the die pad 11 side and a rectangular portion on the connection lead 52 side are combined. The length D1 along the longitudinal direction of the inner pad portion 53 may be, for example, 0.200 mm or more and 0.400 mm or less, and the width W1 of the inner pad portion 53 may be, for example, 0.150 mm or more and 0.250 mm or less. The inner lead or the like is not connected to the die pad 11 side of the inner pad portion 53, and the first lead portion 12A is terminated by the inner pad portion 53.

As shown in FIGS. 1 to 3, the relatively short second lead portion 12B has an outer pad portion 63 having a substantially uniform cross section in the length direction. The outer end portion of the outer pad portion 63 is connected to the support member 13, and the outer pad portion 63 extends perpendicularly to the support member 13. An internal terminal (second internal terminal) 15B is formed on the surface of the outer pad portion 63. The internal terminal 15B is a region electrically connected to the semiconductor element 21 via the bonding wire 22 as described later. A plated portion for improving the adhesion to the bonding wire 22 may be provided on the internal terminal 15B. Further, the above-mentioned external terminal (second external terminal) 17B is formed on the back surface of the outer pad portion 63.

The plurality of outer pad portions 63 have the same planar shape as each other. Specifically, the outer pad portion 63 has a shape in which a semicircular portion on the die pad 11 side and a rectangular portion on the support member 13 side are combined. The length D2 along the longitudinal direction of the outer pad portion 63 may be, for example, 0.200 mm or more and 0.600 mm or less, and the width W2 of the outer pad portion 63 may be, for example, 0.150 mm or more and 0.250 mm or less. The outer pad portion 63 may have the same planar shape as the inner pad portion 53, or may have a different planar shape. The inner lead or the like is not connected to the die pad 11 side of the outer pad portion 63, and the second lead portion 12B is terminated by the outer pad portion 63.

In the present embodiment, as shown in FIGS. 1 and 2, the plurality of inner pad portions 53 are arranged at equal intervals with a first interval P1 from each other. Further, the plurality of outer pad portions 63 are arranged at equal intervals with a second interval P2 from each other. In this case, the first interval P1 is narrower than the second interval P2 (P1 <P2). As a result, the plurality of inner pad portions 53 can be arranged densely in the plane, and the number of arrangements of the inner pad portions 53 can be increased. In particular, by appropriately setting the first interval P1, it is possible to prevent a problem that the inner pad portion 53 closest to the suspension lead 14 interferes with the suspension lead 14 and the inner pad portion 53 cannot be arranged in the vicinity of the suspension lead 14. be able to.

Here, the first spacing P1 and the second spacing P2 are the distances between the centers of the inner pad portions 53 and the outer pad portions 63, respectively, and are parallel to the sides (X direction or Y direction) of the die pad 11. Refers to the distance.

The first spacing P1 may be, for example, 0.400 mm or more and 0.500 mm or less, and the second spacing P2 may be, for example, 0.500 mm or more and 0.600 mm or less. Further, the first interval P1 may be 85% or more and 90% or less of the second interval P2. By setting the above range, the number (number of pins) of the inner pad portion 53 and the outer pad portion 63 can be increased without changing the size of the semiconductor device 20, and these can be arranged at high density. can. On the other hand, it is possible to prevent a problem that the inner pad portion 53 and the outer pad portion 63 are too close to each other to cause a short circuit.

The connection leads 52 of the first lead portion 12A are arranged at equal intervals with a third interval P3 from each other. This third interval P3 is equal to the second interval P2 (P3 = P2). The third interval P3 is the distance between the centers of the connection leads 52 in the width direction and is parallel to the side (X direction or Y direction) of the die pad 11.

The lead frame 10 described above is composed of a metal such as copper, a copper alloy, and a 42 alloy (Ni 42% Fe alloy) as a whole. The thickness of the lead frame 10 can be 80 μm or more and 200 μm or less, although it depends on the configuration of the semiconductor device 20 to be manufactured.

In the present embodiment, the first lead portion 12A and the second lead portion 12B are arranged along all four sides of the die pad 11 (see FIGS. 1 and 2), but the present invention is not limited to this. Instead, for example, they may be arranged along only two opposing sides of the die pad 11.

Configuration of Semiconductor Device Next, the semiconductor device according to the present embodiment will be described with reference to FIGS. 4 to 6. 4 to 6 are diagrams showing a semiconductor device (DR-QFN (Dual Row QFN) type) according to the present embodiment.

As shown in FIGS. 4 to 6, the semiconductor device (semiconductor package) 20 includes a die pad 11, a plurality of first lead portions 12A and a plurality of second lead portions 12B arranged around the die pad 11, and a die pad 11. The semiconductor element 21 mounted above is provided with a plurality of bonding wires (connecting members) 22 for electrically connecting the first lead portion 12A or the second lead portion 12B and the semiconductor element 21. Further, the die pad 11, the first lead portion 12A, the second lead portion 12B, the semiconductor element 21, and the bonding wire 22 are resin-sealed with the sealing resin 23.

Of these, the die pad 11, the first lead portion 12A, and the second lead portion 12B are manufactured from the above-mentioned lead frame 10. The first lead portion 12A has an inner pad portion 53, and the second lead portion 12B has an outer pad portion 63. The first spacing P1 of the plurality of inner pad portions 53 is narrower than the second spacing P2 of the plurality of outer pad portions 63.

In addition, the configurations of the die pad 11, the first lead portion 12A, and the second lead portion 12B are the same as those shown in FIGS. 1 to 3 described above except for the region not included in the semiconductor device 20, and therefore, here, A detailed description will be omitted.

As the semiconductor element 21, various semiconductor elements generally used in the past can be used, and the semiconductor element 21 is not particularly limited, and for example, an integrated circuit, a large-scale integrated circuit, a transistor, a thyristor, a diode, or the like can be used. The semiconductor element 21 has a plurality of electrodes 21a to which the bonding wires 22 are attached. Further, the semiconductor element 21 is fixed to the surface of the die pad 11 with an adhesive 24 such as a die bonding paste.

Each bonding wire 22 is made of a highly conductive material such as gold or copper. One end of each bonding wire 22 is connected to the electrode 21a of the semiconductor element 21, and the other end is connected to the internal terminal 15A of each first lead portion 12A or the internal terminal 15B of the second lead portion 12B, respectively. There is. The internal terminals 15A and 15B may be provided with a plated portion that improves the adhesion to the bonding wire 22.

As the sealing resin 23, a thermosetting resin such as a silicone resin or an epoxy resin, or a thermoplastic resin such as a PPS resin can be used. The thickness of the entire sealing resin 23 can be about 300 μm or more and 1200 μm or less. Further, the length L2 of one side of the sealing resin 23 (one side of the semiconductor device 20) can be, for example, 6 mm or more and 16 mm or less. In the present embodiment, the planar shape of the sealing resin 23 is square, but the planar shape of the sealing resin 23 is not limited to this, and the planar shape of the sealing resin 23 may be rectangular. In FIG. 4, the display of the portion of the sealing resin 23 located on the surface side of the die pad 11, the first lead portion 12A, and the second lead portion 12B is omitted.

Method for Manufacturing Lead Frame Next, a method for manufacturing the lead frame 10 shown in FIGS. 1 to 3 will be described with reference to FIGS. 7 (a) and 7 (e). 7 (a)-(e) are cross-sectional views (corresponding to FIG. 3) showing a method of manufacturing the lead frame 10.

First, as shown in FIG. 7A, a flat plate-shaped metal substrate 31 is prepared. As the metal substrate 31, a substrate made of a metal such as copper, a copper alloy, or a 42 alloy (Ni 42% Fe alloy) can be used. It is preferable to use a metal substrate 31 that has been degreased and cleaned on both sides thereof.

Next, the photosensitive resists 32a and 33a are applied to the entire front and back of the metal substrate 31, respectively, and dried (FIG. 7 (b)). As the photosensitive resists 32a and 33a, conventionally known ones can be used.

Subsequently, the metal substrate 31 is exposed to the metal substrate 31 via a photomask and developed to form etching resist layers 32 and 33 having desired openings 32b and 33b (FIG. 7 (c)).

Next, the metal substrate 31 is etched with a corrosion solution using the etching resist layers 32 and 33 as corrosion resistant films (FIG. 7 (d)). As a result, the outer shapes of the die pad 11, the first lead portion 12A and the second lead portion 12B are formed. At this time, by appropriately adjusting the shapes of the etching resist layers 32 and 33, the inner pad portion 53 is formed in the first lead portion 12A, and the outer pad portion 63 is formed in the second lead portion 12B. The first spacing P1 of the plurality of inner pad portions 53 is narrower than the second spacing P2 of the plurality of outer pad portions 63. The corrosion liquid can be appropriately selected according to the material of the metal substrate 31 to be used. For example, when copper is used as the metal substrate 31, a ferric chloride aqueous solution is usually used and both sides of the metal substrate 31 are used. Can be spray etched from.

Then, by peeling off and removing the etching resist layers 32 and 33, the lead frame 10 shown in FIGS. 1 to 3 can be obtained. (FIG. 7 (e)).

Manufacturing Method of Semiconductor Device Next, the manufacturing method of the semiconductor device 20 shown in FIGS. 4 and 5 will be described with reference to FIGS. 8 (a) and 8 (e).

First, the lead frame 10 is manufactured by the method shown in FIGS. 7 (a) to 7 (e) described above (FIG. 8 (a)).

Next, the semiconductor element 21 is mounted on the die pad 11 of the lead frame 10. In this case, the semiconductor element 21 is placed and fixed on the die pad 11 by using an adhesive 24 such as a die bonding paste (diaattachment step) (FIG. 8 (b)).

Next, each electrode 21a of the semiconductor element 21 and the internal terminal 15A of each inner pad portion 53 and the internal terminal 15B of the outer pad portion 63 are electrically connected to each other by a bonding wire (connecting member) 22 (wire). Bonding step) (FIG. 8 (c)).

At this time, the lead frame 10 is placed on the heat block 36 of the wire bonding apparatus. Next, the first lead portion 12A and the second lead portion 12B are heated from the back surface side by the heat block 36. At the same time, while applying ultrasonic waves through the capillary (not shown) of the wire bonding apparatus, the electrodes 21a of the semiconductor element 21, the internal terminals 15A of each inner pad 53, and the internal terminals 15B of the outer pad 63. Is electrically connected using the bonding wire 22.

Next, the sealing resin 23 is formed by injection molding or transfer molding a thermosetting resin or a thermoplastic resin on the lead frame 10 (FIG. 8 (d)). In this way, the lead frame 10, the semiconductor element 21, the first lead portion 12A, the second lead portion 12B, and the bonding wire 22 are sealed.

Next, the lead frame 10 is separated for each semiconductor device 20 by dicing the sealing resin 23 between the semiconductor elements 21. At this time, the lead frame 10 and the sealing resin 23 between the semiconductor devices 20 may be cut while rotating a blade (not shown) made of, for example, a diamond grindstone.

In this way, the semiconductor device 20 shown in FIGS. 4 and 5 is obtained (FIG. 8 (e)).

As described above, according to the present embodiment, the plurality of inner pad portions 53 are arranged at equal intervals with a first spacing P1 from each other, and the plurality of outer pad portions 63 are arranged at equal intervals with a first spacing P1 from each other. They are arranged at equal intervals with P2 open. Here, the first interval P1 is narrower than the second interval P2. As a result, the inner pad portions 53 can be densely arranged around the die pad 11, so that the total number (number of pins) of the inner pad portion 53 and the outer pad portion 63 can be increased. This makes it possible to increase the density of the semiconductor device 20.

On the other hand, as a comparative example, in the lead frame 10A shown in FIG. 9, the spacing between the plurality of inner pad portions 53 and the spacing between the plurality of outer pad portions 63 are the same (P2). In this case, the number of inner pad portions 53 to be arranged is limited.

Table 1 is a table for comparing the lead frame 10 (FIGS. 1 to 3) according to the present embodiment and the lead frame 10A (FIG. 9) according to the comparative example. Here, both the lead frame 10 (FIGS. 1 to 3) and the lead frame 10A (FIG. 9) are for manufacturing a semiconductor device 20 having a side length L2 (FIGS. 4 and 5) of 8 mm. ..

As shown in Table 1, in the lead frame 10A according to the comparative example, the number of pins per quadrant (a substantially trapezoidal region surrounded by one side of the die pad 11, a pair of suspension leads 14, and a support member 13) ( The number of the inner pad portion 53 and the outer pad portion 63) is 26, and the total number of pins (4 quadrants) is 100.

On the other hand, in the lead frame 10 according to the present embodiment, the number of pins per quadrant (the number of the inner pad portion 53 and the outer pad portion 63) is 27, and the total number of pins (4 quadrants) is 108. .. As described above, in the present embodiment, the number of pins per semiconductor device 20 can be increased.

10 Lead frame 11 Die pad 12A 1st lead part 12B 2nd lead part 15A, 15B Internal terminal 17A, 17B External terminal 20 Semiconductor device 21 Semiconductor element 22 Bonding wire (connecting member)
23 Sealing resin

Claims (7)

It ’s a lead frame.
Die pads on which semiconductor elements are mounted and
A plurality of inner pad portions provided around the die pad and
A plurality of outer pad portions provided around the die pad are provided.
The inner pad portion is located closer to the die pad than the outer pad portion.
The plurality of inner pad portions are arranged on the first straight line at intervals from each other.
Connection leads are connected to the plurality of inner pad portions, respectively.
Some of the connecting leads have a first straight line portion perpendicular to the first straight line portion and an inclined portion connected to the first straight line portion and extending at an angle with respect to the first straight line portion.
The other part of the connecting lead is composed of only a second straight line portion perpendicular to the first straight line.
A lead frame characterized in that the first straight line portion of the connection lead extends closer to the die pad than the outer pad portion. It ’s a lead frame.
Die pads on which semiconductor elements are mounted and
A plurality of inner pad portions provided around the die pad and
A plurality of outer pad portions provided around the die pad are provided.
The inner pad portion is located closer to the die pad than the outer pad portion.
The plurality of inner pad portions are arranged so as to be spaced apart from each other along one side of the die pad.
The plurality of outer pad portions are arranged so as to be spaced apart from each other along one side of the die pad.
The inner pad portion arranged at the most end in the direction along one side of the die pad and one of the outer pad portions are arranged at the same position in the direction along one side of the die pad.
The inner pad portion other than the inner pad portion arranged at the most end portion and the other outer pad portion adjacent to the inner pad portion are arranged at positions shifted in the direction along one side of the die pad. A lead frame characterized by being present. The lead frame according to claim 2, wherein at least one outer pad portion is arranged outside one of the outer pad portions in a direction along one side of the die pad. The lead frame according to any one of claims 1 to 3, wherein the plurality of inner pad portions have the same planar shape as each other. The lead frame according to any one of claims 1 to 4, wherein the plurality of outer pad portions have the same planar shape as each other. It ’s a semiconductor device,
With a die pad
A plurality of inner pad portions provided around the die pad and
A plurality of outer pad portions provided around the die pad, and
The semiconductor element mounted on the die pad and
A connecting member that electrically connects the semiconductor element to the inner pad portion or the outer pad portion,
The die pad, the plurality of inner pad portions, the plurality of outer pad portions, the semiconductor element, and a sealing resin for sealing the connection member are provided.
The inner pad portion is located closer to the die pad than the outer pad portion.
The plurality of inner pad portions are arranged on the first straight line at intervals from each other.
Connection leads are connected to the plurality of inner pad portions, respectively.
Some of the connecting leads have a first straight line portion perpendicular to the first straight line portion and an inclined portion connected to the first straight line portion and extending at an angle with respect to the first straight line portion.
The other part of the connecting lead is composed of only a second straight line portion perpendicular to the first straight line.
A semiconductor device characterized in that the first straight line portion of the connection lead extends closer to the die pad than the outer pad portion. It ’s a semiconductor device,
With a die pad
A plurality of inner pad portions provided around the die pad and
A plurality of outer pad portions provided around the die pad, and
The semiconductor element mounted on the die pad and
A connecting member that electrically connects the semiconductor element to the inner pad portion or the outer pad portion,
The die pad, the plurality of inner pad portions, the plurality of outer pad portions, the semiconductor element, and a sealing resin for sealing the connection member are provided.
The inner pad portion is located closer to the die pad than the outer pad portion.
The plurality of inner pad portions are arranged so as to be spaced apart from each other along one side of the die pad.
The plurality of outer pad portions are arranged so as to be spaced apart from each other along one side of the die pad.
The inner pad portion arranged at the most end in the direction along one side of the die pad and one of the outer pad portions are arranged at the same position in the direction along one side of the die pad.
The inner pad portion other than the inner pad portion arranged at the most end portion and the other outer pad portion adjacent to the inner pad portion are arranged at positions shifted in the direction along one side of the die pad. A semiconductor device characterized by being present .

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