JPH0547836A - Mounting structure of semiconductor device - Google Patents
Mounting structure of semiconductor deviceInfo
- Publication number
- JPH0547836A JPH0547836A JP20071991A JP20071991A JPH0547836A JP H0547836 A JPH0547836 A JP H0547836A JP 20071991 A JP20071991 A JP 20071991A JP 20071991 A JP20071991 A JP 20071991A JP H0547836 A JPH0547836 A JP H0547836A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor device
- lead frame
- leads
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に係り、さら
に詳しくは、半導体素子とリードフレームとの接続方式
を改良しさらに、接合性を高めたさせた半導体装置の実
装構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a mounting structure of a semiconductor device in which a connecting method between a semiconductor element and a lead frame is improved and a bonding property is enhanced.
【０００２】[0002]
【従来の技術】最近の電子機器は、小形化、軽量化、高
機能化が著しく、これに伴って電子機器に搭載される半
導体装置も、小形、表面実装形、高密度実装の要求が強
くなっている。2. Description of the Related Art Recent electronic devices have been remarkably miniaturized, lightened and highly functional, and accordingly, semiconductor devices mounted on the electronic devices are also strongly required to be small, surface mount type and high density mount. Is becoming
【０００３】図５(a) はパッケージの四方にリードが設
けられた従来の半導体装置（以下ＱＦＰという）の一例
を示す平面図、図５(b) はそのＢ−Ｂ断面図である。図
において、1は半導体素子、2は半導体素子1の電極に対
応してリードフレーム（図示せず）に形成されたリード
で、以下半導体素子1と接続する側をインナーリード2
a、その反対側をアウターリード2bということがある。
3は金、アルミニウム等からなり、半導体素子1の電極
とこれに対応したリード2とを接続するワイヤである。4
は半導体素子1 、インナーリード2a及びワイヤ3を封止
したパッケージである。このような半導体装置は、リー
ドフレームのデバイスホール内に半導体素子1を搭載
し、ボンディングツールを用い半導体素子1の各電極と
これに対応したリード2とをそれぞれワイヤ3で接続す
る。ついで、これら各素子の劣化を防止するため、エポ
キシ樹脂などによりパッケージ4し、各リード2を必要な
長さでリードフレームから切断し、図５(b) 図に示すよ
うにフォーミングする。FIG. 5 (a) is a plan view showing an example of a conventional semiconductor device (hereinafter referred to as QFP) in which leads are provided on four sides of the package, and FIG. 5 (b) is its BB cross-sectional view. In the figure, 1 is a semiconductor element, 2 is a lead formed on a lead frame (not shown) corresponding to the electrode of the semiconductor element 1, and the side to be connected to the semiconductor element 1 will be referred to as an inner lead 2 hereinafter.
The opposite side is sometimes called outer lead 2b.
3 is a wire made of gold, aluminum or the like, which connects the electrode of the semiconductor element 1 and the lead 2 corresponding thereto. Four
Is a package in which the semiconductor element 1, the inner lead 2a and the wire 3 are sealed. In such a semiconductor device, the semiconductor element 1 is mounted in a device hole of a lead frame, and each electrode of the semiconductor element 1 and the corresponding lead 2 are connected by a wire 3 using a bonding tool. Then, in order to prevent deterioration of each of these elements, the package 4 is made of epoxy resin or the like, each lead 2 is cut from the lead frame with a required length, and forming is performed as shown in FIG. 5 (b).
【０００４】[0004]
【発明が解決しようとする課題】前途のように、半導体
装置は小形化、高密度実装の要求が高まっており、上途
のＱＦＰ形の半導体装置においては、現在既にリードの
数は200 本を越えておりさらに高密度化のすう勢にあ
る。As mentioned above, there is an increasing demand for miniaturization and high-density mounting of semiconductor devices, and the number of leads in the QFP type semiconductor devices in the future is already 200. It is over, and there is a trend toward higher density.
【０００５】しかしながら、リードフレームのインナリ
ード2aのピッチＰは、エッチング能力から板厚ｔの２倍
程度、即ちＰ≒２ｔが限界であり、このような制約のた
めファインピッチ化することは困難である。一方、半導
体素子1の電極とインナーリード2aの先端部との間隔を
広くすればインナーリード2aの数をある程度増加するこ
とができるが、このためにはワイヤ3を長くしなければ
ならない。しかし、ワイヤ3を長くすると隣接するワイ
ヤ3と接触して短絡したり、パッケージ4の際に倒れたり
するため、一般にワイヤ3の長さは2.5mm程度とされてい
る。However, the pitch P of the inner leads 2a of the lead frame is limited to about twice the plate thickness t, that is, P.apprxeq.2t, due to the etching capability, and it is difficult to achieve a fine pitch due to such restrictions. is there. On the other hand, the number of the inner leads 2a can be increased to some extent by widening the distance between the electrodes of the semiconductor element 1 and the tips of the inner leads 2a. For this purpose, the wires 3 must be lengthened. However, when the wire 3 is lengthened, the wire 3 comes into contact with an adjacent wire 3 to cause a short circuit, or the package 4 falls down. Therefore, the length of the wire 3 is generally set to about 2.5 mm.
【０００６】このように、従来のリードフレームを用い
てワイヤでボンディングする方式の半導体装置において
は、リードのピッチ及びワイヤの長さに技術的限界があ
り、リードの数をこれ以上増加することは困難であっ
た。As described above, in the conventional semiconductor device in which the wire bonding is performed using the lead frame, there is a technical limit in the pitch of the leads and the length of the wires, and it is impossible to increase the number of leads any more. It was difficult.
【０００７】本発明は、上記の課題を解決すべくなされ
たもので、キャリアフィルムに接続した半導体素子をリ
ードフレームに実装することにより、狭ピッチ、多リー
ドの半導体装置の実装構造を得ることを目的としたもで
ある。The present invention has been made to solve the above-mentioned problems, and a mounting structure of a narrow pitch, multi-lead semiconductor device is obtained by mounting a semiconductor element connected to a carrier film on a lead frame. It was a purpose.
【０００８】[0008]
【課題を解決するための手段】本発明が係る半導体装置
は、半導体素子の電極へ絶縁性フィルムに形成した回路
パターンのインナーリードをそれぞれ接続して外形切断
したＴＡＢ式半導体装置と、多数のリードを有するリー
ドフレームとからなり、前記ＴＡＢ式半導体装置の回路
パターンのアウターリードをリードフレームのリードに
それぞれ接続して樹脂で封止したものである。A semiconductor device according to the present invention includes a TAB type semiconductor device in which inner leads of a circuit pattern formed on an insulating film are connected to electrodes of a semiconductor element, and the outer shape is cut, and a large number of leads. And a lead frame having a resin, and the outer leads of the circuit pattern of the TAB type semiconductor device are connected to the leads of the lead frame and sealed with resin.
【０００９】またリードフレームのインナーリードには
んだバンプを設け、あるいはＴＡＢ式半導体装置のアウ
ターリードにこのはんだバンプに対応して凹部を設けた
ものである。Further, the inner lead of the lead frame is provided with a solder bump, or the outer lead of the TAB type semiconductor device is provided with a recess corresponding to the solder bump.
【００１０】[0010]
【実施例】図１(a) は本発明実施例の縦断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 (a) is a vertical sectional view of an embodiment of the present invention.
【００１１】図において、10はキャリアフィルムに設け
た回路パターンのインナーリード13aに半導体素子1 を
接続した半導体装置（以下ＴＡＢ式半導体装置という）
である。このＴＡＢ式半導体装置10は図４(a) に示すよ
うに、ポリイミドフィルム等からなり、所定の間隔で多
数のデバイスホール12が設けられた長尺（例えば300
ｍ）のキャリアフィルム11に、各デバイスホール12ごと
に銅箔等からなる多数の回路パターン13を形成してその
一端をデバイスホール12に突出させ、インナーリード13
a とする。そして、デバイスホール12に半導体素子1を
配設し、その各電極にボンディングツールによりインナ
ーリード13aを接続して、回路パターン13を１点鎖線14
の位置で切断したものである。この状態を図４(b) 示
す。なお、回路パターン13の下面には例えば錫メッキが
施してある。15はテスト用パッド、16はキャリアフィル
ム11を搬送するためのスプロケット穴である。2 はリー
ドフレームのリード（以下単にリードフレームという）
で、その上面にははんだメッキが施されている。4 は、
例えばエポキシ樹脂で封止したパッケージである。In the figure, 10 is a semiconductor device in which a semiconductor element 1 is connected to inner leads 13a of a circuit pattern provided on a carrier film (hereinafter referred to as a TAB type semiconductor device).
Is. As shown in FIG. 4 (a), this TAB semiconductor device 10 is made of a polyimide film or the like and is long (for example, 300 mm) provided with a large number of device holes 12 at predetermined intervals.
In the carrier film 11 of m), a large number of circuit patterns 13 made of copper foil or the like are formed for each device hole 12, one end of which is projected into the device hole 12, and the inner lead 13
Let a. Then, the semiconductor element 1 is arranged in the device hole 12, and the inner lead 13a is connected to each electrode of the semiconductor element 1 by a bonding tool to form the circuit pattern 13 by the chain line 14
It was cut at the position. This state is shown in FIG. 4 (b). The lower surface of the circuit pattern 13 is plated with tin, for example. Reference numeral 15 is a test pad, and 16 is a sprocket hole for carrying the carrier film 11. 2 is the lead of the lead frame (hereinafter simply referred to as the lead frame)
And, the upper surface is plated with solder. 4 is
For example, a package sealed with an epoxy resin.
【００１２】上記のようなＴＡＢ式半導体装置10をリー
ドフレーム2に実装するには、リードフレームのデバイ
スホールにＴＡＢ式半導体装置10の半導体素子1を、そ
の能動面を上にして配設し、図１(c) に示すように各ア
ウターリード13b をリードフレーム2に整合させる。そ
して図１(b) に示すようにヒータを内蔵したボンディン
グツール20によりアウターリード13bを加圧かつ加熱す
れば、アウタリード13bに設けた錫メッキとリードフレ
ーム2に設けられたはんだメッキとが溶融し両者は強固
に熱圧着される。To mount the TAB type semiconductor device 10 as described above on the lead frame 2, the semiconductor element 1 of the TAB type semiconductor device 10 is disposed in the device hole of the lead frame with its active surface facing upward. Each outer lead 13b is aligned with the lead frame 2 as shown in FIG. 1 (c). Then, as shown in FIG. 1B, when the outer lead 13b is pressed and heated by the bonding tool 20 having a built-in heater, the tin plating provided on the outer lead 13b and the solder plating provided on the lead frame 2 are melted. Both are firmly thermocompression bonded.
【００１３】各アウターリード13bとリードフレーム2と
の接合が終ったときは、半導体素子1、回路パターン13
を含むキャリアフィルム11及びリードフレームのインナ
ーリード2aを例えばエポキシ樹脂で封止してパッケージ
4し、リード2のアウターリード2bを切断してフォーミン
グすれば半導体装置の製造は終了する。When the outer leads 13b and the lead frame 2 are joined together, the semiconductor element 1 and the circuit pattern 13 are formed.
The carrier film 11 including the above and the inner lead 2a of the lead frame are sealed with, for example, an epoxy resin to package
Then, the outer lead 2b of the lead 2 is cut and formed to complete the manufacturing of the semiconductor device.
【００１４】図２は本発明の他の実施例の要部を示すも
ので、図２(a) は側面図、図２(b)は平面図である。本
実施例はリードフレームのインナーリード2aの上にはん
だバンプ5を形成したものである。リードフレームのイ
ンナーリード2aを上記のように構成したことによりリー
ドフレームのインナーリード2aとＴＡＢ式半導体装置の
アウターリード 13bとの間にはんだ量が増えるため確実
に接合できさらに強度を向上することができる。2A and 2B show the essential parts of another embodiment of the present invention. FIG. 2A is a side view and FIG. 2B is a plan view. In this embodiment, the solder bumps 5 are formed on the inner leads 2a of the lead frame. By configuring the inner lead 2a of the lead frame as described above, the amount of solder is increased between the inner lead 2a of the lead frame and the outer lead 13b of the TAB type semiconductor device, so that reliable bonding can be achieved and the strength can be further improved. it can.
【００１５】図３は本発明のさらに他の実施例の要部を
示すもので図３(a)は側面図、図３(b) は平面図であ
る。本実施例においてはリードフレームのインナーリー
ド上に図２の実施例の場合と同様にはんだバンプ5を設
けると共に、ＴＡＢ式半導体装置のリードにリードフレ
ームのバンプと対応する位置にハーフエッチング等によ
り凹部13cを設けこの凹部13cとリードフレームのはんだ
バンプ5を合わせ両者を接合するようにしたものであ
る。3A and 3B show the essential parts of still another embodiment of the present invention. FIG. 3A is a side view and FIG. 3B is a plan view. In this embodiment, the solder bumps 5 are provided on the inner leads of the lead frame in the same manner as in the embodiment of FIG. 2, and the leads of the TAB type semiconductor device are recessed at positions corresponding to the bumps of the lead frame by half etching or the like. 13c is provided so that the recess 13c and the solder bump 5 of the lead frame are aligned with each other to join them.
【００１６】このように構成したことにより、ＴＡＢ式
半導体装置のリード13とリードフレームのリード2との
位置合わせが容易になり、そのうえ接合強度を高めるこ
とができる。With this structure, the lead 13 of the TAB semiconductor device and the lead 2 of the lead frame can be easily aligned with each other, and the bonding strength can be increased.
【００１７】[0017]
【発明の効果】以上の説明から明らかなように、本発明
はワイヤを使用せず、狭ピッチ、多リードが可能なＴＡ
Ｂ式半導体装置のアウターリードをリードフレームのリ
ードに接続するようにしたので、半導体素子とリードフ
レームのリードの先端部との間隔を広げることができ、
このためリードの数を増加することができる。またワイ
ヤを使用しないのでピッチを小さくしても短絡事故を生
ずることもない。As is apparent from the above description, the present invention does not use a wire and is a TA capable of a narrow pitch and multiple leads.
Since the outer lead of the B type semiconductor device is connected to the lead of the lead frame, the distance between the semiconductor element and the tip of the lead of the lead frame can be widened,
Therefore, the number of leads can be increased. Further, since no wire is used, a short circuit accident does not occur even if the pitch is reduced.
【００１８】さらに、ＴＡＢ式半導体装置を使用したの
で、半導体素子の特性試験が容易である。Further, since the TAB type semiconductor device is used, the characteristic test of the semiconductor element is easy.
【００１９】また、リードフレームのインナーリードに
はんだバンプを設け、あるいはＴＡＢ式半導体装置のア
ウターリードにこのはんだバンプに対応して凹部を設け
ることにより位置合わせが容易で接合強度を高めること
ができる等、実施による効果大である。Further, by providing solder bumps on the inner leads of the lead frame or by providing recesses on the outer leads of the TAB type semiconductor device corresponding to these solder bumps, alignment can be facilitated and the bonding strength can be increased. The effect is large.
【図１】(a) は本発明実施例の断面図。 (b) はその要部の側面図。 (c) は平面図。FIG. 1A is a sectional view of an embodiment of the present invention. (b) is a side view of the main part. (c) is a plan view.
【図２】(a) は本発明の他の実施例の要部を示す側面
図。 (b) はその平面図。FIG. 2A is a side view showing a main part of another embodiment of the present invention. (b) is a plan view.
【図３】(a) は本発明のさらに他の実施例の要部を示す
側面図。 (b) はその平面図。FIG. 3 (a) is a side view showing a main part of still another embodiment of the present invention. (b) is a plan view.
【図４】(a) はＴＡＢ式半導体装置の一例の平面図。 (b) はそのＡ−Ａ断面図。FIG. 4A is a plan view of an example of a TAB semiconductor device. (b) is the AA sectional view.
【図５】(a) は従来のＱＦＰ形半導体装置の一例を示す
平面図。 (b) はそのＢ−Ｂ断面図。FIG. 5A is a plan view showing an example of a conventional QFP type semiconductor device. (b) is the BB sectional drawing.
1： 半導体素子 2： リードフレーム 2a： リードフレームのインナーリード 2b： リードフレームのアウターリード 3： ワイヤ 4： パッケージ 5： はんだバンプ 10： ＴＡＢ式半導体装置 11： キャリアフィルム 12： デバイスホール 13： 回路パターン 13a： インナーリード 13b： アウターリード 13c： 凹部 15： テスト用パット 16： スプロケット穴 20： ツール 1: Semiconductor element 2: Lead frame 2a: Inner lead of lead frame 2b: Outer lead of lead frame 3: Wire 4: Package 5: Solder bump 10: TAB type semiconductor device 11: Carrier film 12: Device hole 13: Circuit pattern 13a: Inner lead 13b: Outer lead 13c: Recess 15: Test pad 16: Sprocket hole 20: Tool
Claims (3)
成した回路パターンのインナーリードをそれぞれ接続し
て外形切断したＴＡＢ式半導体装置と、多数のリードを
有するリードフレームとからなり、前記ＴＡＢ式半導体
装置の回路パターンのアウターリードを前記リードフレ
ームのリードにそれぞれ接続して樹脂で封止したことを
特徴とする半導体装置の実装構造。1. A TAB semiconductor device comprising a TAB type semiconductor device in which inner leads of a circuit pattern formed on an insulating film are respectively connected to electrodes of a semiconductor element and the outer shape is cut, and a lead frame having a large number of leads. A mounting structure of a semiconductor device, wherein outer leads of a circuit pattern of the device are respectively connected to leads of the lead frame and sealed with resin.
はんだバンプを形成したことを特徴とする請求項１記載
の半導体装置の実装構造。2. The mounting structure for a semiconductor device according to claim 1, wherein solder bumps are formed on the inner leads of the lead frame.
はんだバンプ形成すると共に、前記ＴＡＢ式半導体装置
の前記はんだバンプと対応する位置に凹部を設けてなる
請求項１記載の半導体装置の実装構造。3. The mounting structure for a semiconductor device according to claim 1, wherein a solder bump is formed on an inner lead of the lead frame, and a recess is provided at a position corresponding to the solder bump of the TAB type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20071991A JPH0547836A (en) | 1991-08-09 | 1991-08-09 | Mounting structure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20071991A JPH0547836A (en) | 1991-08-09 | 1991-08-09 | Mounting structure of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0547836A true JPH0547836A (en) | 1993-02-26 |
Family
ID=16429069
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20071991A Pending JPH0547836A (en) | 1991-08-09 | 1991-08-09 | Mounting structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0547836A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5474958A (en) * | 1993-05-04 | 1995-12-12 | Motorola, Inc. | Method for making semiconductor device having no die supporting surface |
| US5732465A (en) * | 1994-07-15 | 1998-03-31 | Shinko Electric Industries Co., Ltd. | Method of manufacturing one side resin sealing type semiconductor devices |
| JP2008177618A (en) * | 2004-11-11 | 2008-07-31 | Sharp Corp | Flexible wiring board, semiconductor device and electronic equipment using the wiring board |
| US7977805B2 (en) | 2004-11-11 | 2011-07-12 | Sharp Kabushiki Kaisha | Flexible wiring substrate, semiconductor device and electronic device using flexible wiring substrate, and fabricating method of flexible wiring substrate |
| US8834364B2 (en) | 2006-11-01 | 2014-09-16 | Resmed Sensor Technologies Limited | System and method for monitoring cardiorespiratory parameters |
-
1991
- 1991-08-09 JP JP20071991A patent/JPH0547836A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5474958A (en) * | 1993-05-04 | 1995-12-12 | Motorola, Inc. | Method for making semiconductor device having no die supporting surface |
| US5732465A (en) * | 1994-07-15 | 1998-03-31 | Shinko Electric Industries Co., Ltd. | Method of manufacturing one side resin sealing type semiconductor devices |
| US5918746A (en) * | 1994-07-15 | 1999-07-06 | Shinko Electric Industries Co., Ltd. | Carrier frame used for circuit boards |
| EP0692820B1 (en) * | 1994-07-15 | 2002-10-02 | Shinko Electric Industries Co. Ltd. | Carrier and method of manufacturing one sided resin sealed semiconductor devices using said carrier |
| JP2008177618A (en) * | 2004-11-11 | 2008-07-31 | Sharp Corp | Flexible wiring board, semiconductor device and electronic equipment using the wiring board |
| US7977805B2 (en) | 2004-11-11 | 2011-07-12 | Sharp Kabushiki Kaisha | Flexible wiring substrate, semiconductor device and electronic device using flexible wiring substrate, and fabricating method of flexible wiring substrate |
| US8834364B2 (en) | 2006-11-01 | 2014-09-16 | Resmed Sensor Technologies Limited | System and method for monitoring cardiorespiratory parameters |
| US10893811B2 (en) | 2006-11-01 | 2021-01-19 | Resmed Sensor Technologies Limited | System and method for monitoring cardiorespiratory parameters |
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